Predictive Compact Model Research Articles

Predictive compact model for stress-induced on-product overlay correction

On-product overlay (OPO) is an important indicator of device yield. In this work, we show that stressed thin films used in semiconductor manufacturing can be an important contributor to OPO at multiple length scales. Depending on the stress level, film thickness, and the mask design, the overlay impact can be a few nanometers for the exposure of the next lithography layer. A predictive compact model based on pattern density is developed to accurately predict this overlay impact. The model is then verified using short-loop dual damascene wafers with stress split. The predictive model opens a new opportunity for model-based mask correction during optical proximity correction to increase the overlay margin for subsequent lithography exposures.

Temperature Dependence of On-State Inter-Terminal Capacitances (C<sub>gd</sub> and C<sub>gs</sub>) of SiC MOSFETs and Frequency Limitations of their Measurements

Inter-terminal capacitances (ITCs) have major influence on the dynamic performance of power SiC MOSFETs. Knowledge of the exact values for the ITCs is required in order to perform accurate and predictive compact model simulations of their dynamic performance. Since commercial SiC MOSFETs are capable of operating in a wide range of temperatures, it is important to know the values of ITCs in the whole temperature range of operation. Direct measurements of the ITCs with standard equipment is possible only at low current levels (i.e. in the off-state (Vgs < Vth) for Vds > 0 V), however their values in the on-state (Vgs>Vth) also influence the MOSFETs switching performance. In this work, ITCs of a planar SiC MOSFET in the on-state are studied by the means of a calibrated TCAD model, revealing substantial temperature dependence in the range of 300-450 K. In the first approximation, this temperature dependence of the ITCs can be explained by a weaker temperature dependence of the MOSFET channel resistance in comparison to its JFET and epitaxial layer resistances. In addition, it is shown that at high frequencies stray inductances of the TO-247-3 package result in a change of the extracted values of the on-state ITCs. This effect is already notable at 1 MHz.

RRAM-Based Analog Approximate Computing

Approximate computing is a promising design paradigm for better performance and power efficiency. In this paper, we propose a power efficient framework for analog approximate computing with the emerging metal-oxide resistive switching random-access memory (RRAM) devices. A programmable RRAM-based approximate computing unit (RRAM-ACU ) is introduced first to accelerate approximated computation, and an approximate computing framework with scalability is then proposed on top of the RRAM-ACU. In order to program the RRAM-ACU efficiently, we also present a detailed configuration flow, which includes a customized approximator training scheme, an approximator-parameter-to-RRAM-state mapping algorithm, and an RRAM state tuning scheme. Finally, the proposed RRAM-based computing framework is modeled at system level. A predictive compact model is developed to estimate the configuration overhead of RRAM-ACU and help explore the application scenarios of RRAM-based analog approximate computing. The simulation results on a set of diverse benchmarks demonstrate that, compared with a x86–64 CPU at 2 GHz, the RRAM-ACU is able to achieve 4.06– $196.41 {\times }$ speedup and power efficiency of 24.59–567.98 GFLOPS/W with quality loss of 8.72% on average. And the implementation of hierarchical model and X application demonstrates that the proposed RRAM-based approximate computing framework can achieve >12.8 $\times$ power efficiency than its pure digital implementation counterparts (CPU, graphics processing unit, and field- programmable gate arrays).

A Predictive Compact Model of Bipolar RRAM Cells for Circuit Simulations

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators.

MASTAR VA: A predictive and flexible compact model for digital performances evaluation of CMOS technology with conventional CAD tools

This work presents the methodology employed in order to make the MASTAR model (Model for Assessment of CMOS Technologies And Roadmaps [1]), used within the frame of the International Technology Roadmap for Semiconductor (ITRS), compatible with conventional CAD tools. As an example, we used the updated model together with ELDO for the evaluation of digital and SRAM performance.

Compact modeling of vertical hall-effect devices: electrical behavior

This paper presents the development of a design-oriented compact model of vertical Hall-effect sensors integrated in CMOS technologies. Such a model makes easier the design of integrated Hall systems, permitting designers to co-simulate the Hall sensing element with the biasing and processing electronics thanks to a single electrical simulator. Here focus is put on the electrical behavior, i.e. the resistive behavior of a 5-contact vertical Hall device. The model is based both on theoretical considerations and on FEM numerical simulations performed with COMSOL®. The result is a new predictive compact model, written in Verilog-A, with 7 input terminals and 14 parameters, mainly sensor geometrical and technological parameters. These parameters can be easily extracted from measurements carried out on a single sensor. The compact model has been validated by FEM simulations, as well as by comparing its response with experimental results obtained from a vertical Hall device fabricated in a CMOS 0.35 μm technology. The root mean square error of the model with respect to experimental results obtained on a wide range of typical sensor biasing conditions is below 2 %. Such a resistive model opens the way to an efficient, complete compact model of the vertical Hall device, i.e. including the Hall-effect as well as all the second-order galvanomagnetic effects.

Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes

In this paper, we provide an extensive experimental and theoretical study of the benefits of patterned ground shield interconnect transmission lines over more conventional layouts in advanced integrated-circuit processes. As part of this experimental work, we present the first comparative study taken on truly differential transmission line test structures. Our experimental results obtained on transmission lines with patterned ground shields are compared against a predictive compact equivalent-circuit model. This model employs exact closed-form expressions for the inductances, and describes key performance figures such as characteristic impedance and attenuation loss with excellent accuracy

Physics-based wideband predictive compact model for inductors with high amounts of dummy metal fill

A computationally efficient physics-based wideband predictive inductor compact model is presented that is capable of evaluating the impact on inductance and quality factor of dummy metal fill-cells. In a modern integrated-circuit process, high amounts of these fill-cells are required to meet metal density rules and guarantee adjacent circuit integrity. The predictions made with this model are shown to be in agreement with data measured on symmetrical octagonal inductors realized in a 90-nm CMOS process with varying amounts of dummy metal fill-cells. We further provide all inductance equations, list additional sources of eddy current losses, and discuss layout modifications, which would further improve the performance of the integrated inductors

PREDICTMOS – a predictive compact model of small-geometry MOSFETs for circuit simulation and device scaling calculations

In circuit design and device scaling investigations, there is still a demand for improved analytical models of MOSFETs with less fitting parameters and a good scalability. In this paper, PREDICTMOS-a predictive compact model for structure oriented simulation of MOS devices is presented which has been developed by use of strongly physics-based model equations. For threshold voltage, surface potential in weak inversion, and currents in strong inversion including the saturation regime, the equations have been derived using our recently published conformal mapping techniques for solving the two-dimensional Poisson equation, and a new way to solve the transistor current differential equation. They make use of real structural parameters without any need of physically meaningless fitting parameters. This results in a strong link between electrical parameters and the process and layout data of the device and an excellent scalability while keeping physical insight. PREDICTMOS has been implemented in the ELDO circuit simulator. Its results in comparison with numerical device simulations and measurements show good agreement down to dimensions of 0.1 μm .