Power Supply Rejection Research Articles

Analysis and Design of Low-Noise Radio-Frequency Power Amplifier Supply Modulator for Frequency Division Duplex Cellular Systems

This paper describes an analysis of power supply rejection and noise improvement techniques for an envelope-tracking power amplifier. Although the envelope-tracking technique improves efficiency, its power supply rejection ratio is much lower than that of average power tracking or a fixed-supply power amplifier. In FDD systems with the envelope-tracking technique, the low power supply rejection ratio generates much output noise in the RX band and degrades the receiver’s sensitivity. An SM is designed by using a 130 nm CMOS process, and the chip die area is 2 × 2 mm2 with a 25-pin wafer-level chip-scale package. The designed SM achieved peak efficiencies of 78–83% for LTE signals with a 5.8 dB PAPR and various channel bandwidths. For the low-output-noise-supply modulator, noise reduction techniques using resonant-frequency tuning and a notch filter are employed, and the measured results show maximum 1.8/5/5.3/3.8/3 dB noise reduction in LTE bands B17/B5/B2/B3/B7, respectively.

Curvature-Compensated Bandgap Voltage Reference with Low Temperature Coefficient

Resistance errors in bandgap reference (BGR) circuits often cause deviations in design indicators, and it is true that utilizing various compensation techniques mitigates the impact of resistance errors. In this paper, an original BGR circuit with 180 nm BCD processing is presented, which uses an improved high-order compensation and curvature compensation. The proposed BGR contains four main blocks, including a start-up stage, a first-order temperature compensation stage, a high-order temperature compensation stage, and a curvature compensation stage. Meanwhile, a trimming resistor array structure is designed to revise the temperature coefficient (TC) deviation of the test output voltage from the theoretical design value. Through wafer-level laser trimming technology, the measurement results are achieved with very little difference from the theoretical design value. The proposed BGR provides a stable reference voltage at 1.25 V with a low TC and strong power supply rejection (PSR). Within temperatures ranging from −45 °C to 125 °C, the measured TC shows an optimal value at 4.2 ppm/°C and the measured PSR shows −100 dB.

Recent advances in LDO chip research

Abstract. With the rapid development of integrated circuit technology and the wide application of Internet of things devices, the demand for power management chips is increasing. Low-dropout regulators (LDO) play an important role in modern electronic devices. It provides a stable low output voltage while maintaining low power consumption. Recently some progress has been made in the research of LDO chips, focusing on improving power efficiency, reducing static current, and enhancing transient response. The study shows that the static current has been significantly reduced by using the subthreshold MOS tube and dynamic current bias technology. In terms of power supply rejection ratio (PSRR), by improving the circuit design, the PSRR of LDO can be maintained above -80 dB under various conditions. In addition, improvements to the transient response result in significantly optimized overshoot and recovery times of the output voltage, ensuring voltage stability when the load changes rapidly. These advances enable LDO chips to meet the demanding requirements of high-performance and Internet of things device applications. Future challenges include further reducing static current, improving PSRR performance in high-frequency environments, and effectively addressing thermal management issues.

Design of Voltage–Current Reference Source in CMOS Technology

A design methodology for a resistorless low-power two-in-one voltage and current reference source working in subthreshold and moderate regions is described. The presented novel universal reference voltage–current source was implemented in ten different designs for seven different CMOS technologies. Six versions of these designs were silicon-proven using four different CMOS technologies. The example of implementation in 130 nm technology provides a reference current of 5 µA and reference voltage of 800 mV at supply voltages ranging from 0.9 V to 2.0 V with a total current consumption of 15 µA. The proposed circuit occupies a 1200 µm2 chip area and achieves 280 and 118 ppm/°C for all process corners and temperature variation from −40 °C to 125 °C. The power supply rejection ratio of output IREF without any filtering capacitor at 100 Hz and 10 MHz is 128 dB and 100 dB, respectively. The equivalent output current noise in the bandwidth from 1 Hz to 10 MHz reaches 9.1 nARMS.

A 600-mA Multifeedback Loop Capacitorless Low-Dropout Regulator With a –40-dB Power Supply Rejection at 1 MHz With 27.5-μA Quiescent Current Consumption

A 600-mA Multifeedback Loop Capacitorless Low-Dropout Regulator With a –40-dB Power Supply Rejection at 1 MHz With 27.5-μA Quiescent Current Consumption

A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference

—A low temperature coefficient (TC), low power subthreshold CMOS voltage reference (CVR) over a wide temperature range is presented in this paper. The proposed circuit employs the voltage difference between the two inputs of the operational amplifier as the proportional to absolute temperature (PTAT) voltage and the complementary to absolute temperature (CTAT) voltage, which is obtained by the ΔVGS of different-threshold transistors biased in the subthreshold region. The proposed CVR was designed in the 0.18-μm CMOS process with a total area of 0.0049 mm2. It achieves an average temperature coefficient (TC) of 10.3 ppm/°C over a temperature range of −40 °C–120 °C, with a TC of 4.9 ppm/°C at the TT corner. The measured power supply rejection ratio (PSRR) is −65 dB at 10 Hz and −30 dB at 1 MHz, while the power consumption is 59 nW at a supply voltage of 1 V. The average line sensitivity (LS) is 0.16 %/V, and the LS is 0.09 %/V at the TT corner.

A −184 dB PSRR and 2.47 [formula omitted] noise self biased bandgap reference based on FVF structure

A high power supply rejection ratio (PSRR), low noise and low-power self-biased bandgap voltage reference (BGR) is presented in this paper. In response to the trade-off between power consumption and output noise, a feedback depth enhancement technique is proposed for mitigating the effect of the resistor on output noise and offset voltage. The PSRR is enhanced by a novel self regulating technology based on an improved flipped voltage follower (FVF). The designed BGR was verified under post-simulation for various process corners, voltages and temperatures (PVT). It was using 0.18μm BiCMOS process, occupying an active area of 0.016 mm2. The BGR operates normally at 3.0 V – 3.6 V with a quiescent current of 3.6 μA. The best untrimmed TC is 22.04 ppm/∘C and the rms noise is only 2.47 μVrms from 0.1 Hz to 10 Hz. The PSRR is −184 dB@1 Hz and −50 dB@1 MHz when VIN = 3.0 V.

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.

Noise Aware Fully Integrated Low Power and Low Inrush Current Fast Transient Response LDO

The complexity of Systems-on-Chip (SoC) designs necessitates robust linear regulator architectures to ensure stable operations and efficient power management in modern devices. In response to this demand, low-dropout (LDO) voltage regulators have emerged as a focal point for their scalability and superior performance across diverse application domains. This paper proposes an LDO linear regulator characterized by high power supply rejection ratio (PSR) and rapid transient response. The design of this LDO emphasizes low power consumption and minimal inrush current while incorporating advanced techniques to enhance PSR and stability across varying frequencies. Despite its compact footprint and low-power profile, this LDO achieves remarkable PSR across a broad spectrum of frequencies. To achieve swift transient response, the proposed design integrates variable biasing and transient boost capacitance. The variable bias structure enhances the slew rate and PSR of the LDO, contributing to its overall performance optimization. Additionally, the strategic placement and utilization of transient-boost capacitance leverage its voltage characteristics to bolster transient response without introducing additional quiescent current, thereby further enhancing circuit stability.

A power-efficient fast-transient OCL-LDO with adaptive super source follower and active capacitor compensation management

This paper presents a flipped voltage follower (FVF) based output-capacitor-less low-dropout regulator (OCL-LDO) with fast transient response, high power supply rejection (PSR), and low quiescent current for noise-sensitive circuits in internet-of-things (IoTs). An adaptive super source follower (ASSF) is proposed to effectively reduce the output impedance of the voltage buffer under heavy-loading conditions while keeping a low quiescent current under light-loading conditions. The active capacitor compensation management (ACCM) is proposed to solve the charge-sharing problem caused by the floating capacitors in the dynamic capacitor compensation circuit. The proposed OCL-LDO has been designed and fabricated in 22-nm CMOS technology. It can stabilize with load current ranging from 0 to 12 mA while consuming only 4.8-μA quiescent current. when the load current steps from 0.1 to 10 mA within 3.8 ns, the measured voltage undershoot is 55 mV and the recovery time is about 60 ns.

A 1.87 µW Capacitively Coupled Chopper Instrumentation Amplifier with a 0.36 mV Output Ripple and a 1.8 GΩ Input Impedance for Biomedical Recording

Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input impedance. The amplifier can easily saturate due to the chopper ripple of the CCIA, especially in extremely low noise problems. Therefore, ripple attenuation is required when designing CCIAs. To record biomedical information, a CCIA with a low power consumption and a low noise, low output ripple, and high input impedance (Zin) is presented in this paper. By introducing a ripple attenuation loop (RAL) including the chopping offset amplifier and a low pass filter, the chopping ripple can be reduced to 0.36 mV. To increase the Zin of the CCIA up to 1.8 GΩ, an impedance boost loop (IBL) is added. By using 180 nm CMOS technology, the 0.123 mm2 CCIA consumes 1.87 µW at a supply voltage of 1 V. According to the simulation results using Cadance, the proposed CCIA architecture achieves a noise floor of 136 nV/√Hz, an input-referred noise (IRN) of 2.16 µVrms, a closed-loop gain of 40 dB, a power supply rejection ratio (PSRR) of 108.6 dB, and a common-mode rejection ratio (CMRR) of 118.7 dB. The proposed CCIA is a helpful method for monitoring neural potentials.

Multi-zero pole dynamically compensated LDO with low quiescent current

This paper presents an LDO design tailored to the various power domains of CPUs. In contemporary CPU designs, different functional modules typically necessitate distinct voltage levels, thus requiring a flexible and adjustable power management approach. An LDO with an internally compensated super source follower (SSF) and a multi-zero-pole compensated loop stability is proposed. The SSF is used to reduce the output impedance of the LDO, enhancing its carry-under-load capability. The loop is then transformed into a multi-zero-pole system through Miller compensation, feed-forward compensation, and zero-pole tracking compensation techniques, enabling the LDO to achieve stability and reliability under different loads. The LDO proposed in this study was designed using a 110 nm CMOS process. The LDO can operate within a temperature range of −40–150 °C, with a low quiescent current of 57 μA. The power supply rejection ratio of the circuit is −22 dB at 1 MHz. When the load current jumps from 5 mA to 300 mA within 40 μs, the output voltage experiences an undershoot of 271 mV, an overshoot of 174 mV, and a maximum adjustment time of 100 μs. The load regulation is 0.00267 mV/mA, and the line regulation is 1 mV/V.

A novel LDO circuit with high-speed current detection

Abstract This paper proposes a Low Dropout Regulator (LDO) circuit with high-speed current detection. The current detection circuit utilizes a latch-based structure to expedite comparisons and perform detection. Its primary objective is overcurrent protection in certain practical applications, achieving current limit functionality. The LDO circuit structure can stably provide a 5 V output voltage under a 9 V input voltage, with a maximum output current limit of 70 mA. In practical applications, the circuit can function with a load current of 40 mA, resulting in an output voltage (Vout) of 4.96 V. In the design of the LDO circuit, the Error Amplifier (EA) module departs from conventional internal structures, employing a dual-potential folded cascode common-gate common-source amplifier. This choice enhances parameters such as EA gain and Power Supply Rejection Ratio (PSRR). The gain achieves 98 dB, and the low-frequency PSR reaches 92 dB. Simultaneously, the dual potential configuration significantly economizes the layout area required in practical implementations. The LDO is designed using a 0.18 μm standard CMOS process.

Design and simulation of a bioimpedance detection analog front-end targeting medical applications

This paper presents the design of a bio-impedance detection analog front-end system, which is critical for continuous monitoring of physiological signals in the prevention and treatment of diseases such as coronary heart disease in the context of an aging population. The analog front-end system employs a capacitive-coupled chopper instrumentation amplifier with a fully differentially folded cascode operational amplifier as the core amplifier, and a common-mode feedback loop is introduced to improve the common-mode rejection ratio due to the high requirement for noise suppression. The power supply voltage of the design is 3.3V, achieving a total current consumption of 45uA and a total power consumption of 0.15mW. The core operational amplifier provides a maximum open-loop gain of 58 dB and a -3dB bandwidth of 8.2KHz. The power supply rejection ratio for the positive supply and ground achieved values of 102dB and 108dB, respectively. The common-mode rejection ratio of the chopper instrumentation amplifier can reach 109 dB, which is critical for suppressing common-mode noise.

Segment-compensated Bandgap Reference Generator with Low-temperature Drift

Abstract In this paper, a segment-compensated low-temperature-drift bandgap reference generator is proposed and designed to get the high-order nonlinear temperature characteristics for the bandgap reference circuit. Based on the Nuvoton 0.35 μm BCD process, the circuit is simulated and analyzed. The result is that a temperature coefficient of 1.12 ppm/℃ over the range of -40℃ to 125℃ is obtained, which is much lower than the 6.88 ppm/℃ before compensation. It is demonstrated that the power supply rejection ratio is 141.3 dB at 1, 000 HZ, low-frequency open-loop gain is 75 dB, and a phase margin is 57°.

A 1.65‐nW 11.14‐ppm/°C self‐biased subthreshold CMOS voltage reference with temperature compensation circuit

SummaryThis paper presents a subthreshold CMOS voltage reference (VR) that utilizes self‐biased circuits. This voltage reference includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. The proposed CMOS voltage reference is designed using a standard 0.18‐μm CMOS process and has a small area of only 0.005 mm2. Post‐layout simulation results demonstrate that the power consumption of the circuit at room temperature (25°C) is only 1.65 nW at a power supply voltage of 1 V. In this case, the voltage reference output is 316.56 mV, with an average temperature coefficient (TC) of 11.14 ppm/°C in a wide temperature range from −40°C to 140°C. Furthermore, the line sensitivity (LS) of the circuit is 0.024%/V, and the power supply rejection ratio (PSRR) of the circuit is −86.5 dB at 10 Hz. In summary, the subthreshold CMOS voltage reference structure proposed in this paper demonstrates excellent performance characteristics, such as low power consumption, a small area, and high‐temperature stability. These features make it a promising candidate for voltage reference for low‐power applications with significant changes in environmental temperature.

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS

This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising common-mode and power-supply rejection, a fully differential ring amplifier is employed as the residue amplifier. Additionally, a correlation-based calibration is implemented, which involves injecting pseudo-random dither signals into each multiplying digital-to-analog converter (MDAC) stage to enhance linearity. Fabricated in a 28-nm CMOS process, the 1.25-GS/s 10-bit ADC achieves a spurious-free dynamic range (SFDR) of 70.7 dB and a signal-to-noise-and-distortion ratio (SNDR) of 50.3 dB at Nyquist input. The core conversion circuits of the ADC consume only 30.2 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 90 fJ/conversion-step and a Schreier FoM of 153.5 dB, respectively.

A Rail-to-Rail Operational Amplifier for Transimpedance Optoelectronic Conversion

The transimpedance conversion circuit is an important part of the fluorescent optical fiber temperature sensor, which is used for rare earth fluorescence detection. Transimpedance conversion circuits can benefit from the wide input range, high gain, low input offset voltage, and high common-mode rejection ratio of rail-to-rail operational amplifiers. In this paper, a constant transconductance rail-to-rail operational amplifier is designed and implemented based on the 0.18 μm CMOS process. According to the simulation results, the transconductance change rate of the operational amplifier is 4.8%, and its gain is 140 dB. The input offset voltage of this operational amplifier is 0.41 μV. Both the power supply rejection ratio and the common-mode rejection ratio have values above 140 dB, with the common-mode rejection ratio reaching as high as 165.4 dB. The transimpedance conversion circuit consists of the operational amplifier designed in this paper. The test results show that the operational amplifier has a certain application value in the transimpedance amplification circuit.

A push–pull FVF LDO with full‐spectrum PSR and fast transient response

AbstractA push–pull low‐dropout regulator based on flipped voltage follower is proposed and designed in 65 nm CMOS, which has a push‐current mode and a pull‐current one. The push‐current mode with 1.2‐V input and 1‐V output effectively drives load circuits that are sensitive to supply noise. The pull‐current one with 1.2‐V input and 0.2‐V output effectively drives load circuits that are sensitive to ground noise. Both operating modes feature full‐spectrum power supply rejection (PSR) below −12 dB and achieve 2.4‐ns transient response time over load current (IL) of 10 µA to 20 mA. The presented design achieves a fast transient response and a high‐frequency PSR with a low‐gain fast loop (loop‐I), and enhances the low‐frequency PSR and the line/load regulation with a high‐gain slow loop (loop‐II). Furthermore, the circuit features a load regulation less than 0.09 mV/mA over IL of 10 µA to 20 mA and a line regulation less than 0.01 mV/mV, within a 120‐mV ripple applied to supply/ground. This design consumes a 58‐µA quiescent current (IQ) in both push‐current and pull‐current modes. The low‐dropout regulator works well over the load capacitor (CL) of 0 to 30 pF.

A Sub-1-V Nanopower MOS-Only Voltage Reference

A novel low-power MOS-only voltage reference is presented. The Enz–Krummenacher–Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The proposed voltage reference consists of a specific current generator and a 5-bit trimmable load. Thanks to the good match between the current source stage and the output stage, the nonlinear temperature dependence of carrier mobility is automatically canceled out. The circuit is designed using 55 nm COMS technology. The operating temperature ranges from −40 °C to 120 °C. The average temperature coefficient of the output voltage can be reduced to 21.7 ppm/°C by trimming. The power consumption is only 23.2 nW with a supply voltage of 0.8 V. The line sensitivity and the power supply rejection ratio at 100 Hz are 0.011 %/V and −89 dB, respectively.