Power Overhead Research Articles

A 3.66 μW 12-bit 1 MS/s SAR ADC with mismatch and offset foreground calibration

This paper presents a 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with foreground calibration for digital-to-analog converter (DAC) mismatch and comparator static offset errors. The proposed foreground calibration utilizes the redundancy to facilitate the detection of DAC weight errors, and compensates for deviations of offset and DAC weights from the ideal value in the analog domain respectively. Benefit from the choice of 0.3 fF unit capacitance, the calibration achieves a 90% reduction in DAC power overhead over the conventional method. The effectiveness of this method is demonstrated by simulations in which differential non-linearity (DNL) is reduced from −1.28 LSB to −0.53 LSB and integral non-linearity (INL) is reduced from 2.20 LSB to 1.08 LSB. The ADC implemented in 40 nm CMOS consumes 3.66 μW from a 1 V supply, and achieves an improved signal-to-noise and distortion ratio (SNDR) of from 59.68 dB to 66.67 dB and a figure of merit (FoM) of 2.07 fJ/conversion-step at Nyquist rate.

Slope-assisted Based Fast Strain Measurement Method for Power Overhead Lines of Distribution Internet of Things in Electricity

A distributed optical fiber sensor based on Brillouin scattering can measure the strain along the optical fiber. In order to improve the real-time performance of strain measurement for optic-electric composite overhead lines in the distribution Internet of Things in electricity, the slope-assisted technique is introduced into the demodulation of Brillouin frequency shift. In this technique, the Brillouin frequency shift can be calculated according to the Brillouin gain corresponding to a single frequency and then the strain along the optical fiber can be obtained. The least squares technique based on the pseudo-Voigt model and the slope-assisted technique are implemented, and the Brillouin frequency shift along the optical fiber with different signal-to-noise ratios (SNRs) is calculated by using the two methods. The results reveal that the slope-assisted technique has high accuracy at high SNR and at the same time both the computation time and the spectrum measurement time of this method are far less than that of the least squares technique based on the pseudo-Voigt model.

A High-Linearity Adaptive-Bias SiGe Power Amplifier for 5G Communication

This brief presents an adaptive-bias power amplifier (PA) in 0.13 μm SiGe BiCMOS for fifth-generation (5G) communication. An improved adaptive bias circuitry with small area and power overhead is exploited to fulfill the stringent linearity requirement while maintaining high back-off efficiency. The parasitic effects of peripheral interconnections for large-scale transistors are investigated, and a symmetrical layout with bilateral bypass capacitors is adopted to suppress the imbalance. The proposed PA covers the N257 and N258 bands with over 30-dB gain from 22.5 to 32.5 GHz. The measured output-referred 1-dB compression point (OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) is 20.1 dBm at 24 GHz and keeps higher than 18.5 dBm up to 31 GHz. The power-added efficiency at 6 dB back-off from OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> is as high as 11.5% at 24 GHz, benefited from the adaptive-bias scheme. Measured with 64-QAM signals, the PA demonstrates the EVM approximate to -25.8 dB with average output power higher than 13 dBm at 24, 26, 28, and 30 GHz.

A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication

Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell.

Low mismatch high-speed charge pump for high bandwidth phase locked loops

This paper presents a low mismatch high-speed charge pump for high bandwidth phase locked loop (PLL). A novel mismatch compensation technique is used for reducing the current mismatch without having any extra area and power overhead. Proposed circuit is designed for 100 μA charge pump current (ICP) and it achieves less than 1% mismatch current across all process corners for an output voltage compliance range of 0.2–1 V. A prototype circuit of 1 GHz PLL is designed in 65 nm CMOS technology for testing the proposed charge pump. It achieves −81.2 dBc spur-level at reference frequency of 250 MHz. In locked condition of the PLL, proposed charge pump consumes 176 μW power from 1.2 V supply including the reference current. Area occupied by proposed design is 72 × 35 μm2.

CONCEALING-Gate: Optical Contactless Probing Resilient Design

Optical probing, though developed as silicon debugging tools from the chip backside, has shown its capability of extracting secret data, such as cryptographic keys and user identifications, from modern system-on-chip devices. Existing optical probing countermeasures are based on detecting any device modification attempt or abrupt change in operating conditions during asset extraction. These countermeasures usually require additional fabrication steps and cause area and power overheads. In this article, we propose a novel low-overhead design methodology to prevent optical probing. It leverages additional operational logic gates, termed as “CONCEALING-Gates,” inserted as neighbor gates of the logic gates connected to the nets carrying asset signals. The switching activity of the asset carrying logic is camouflaged with the switching activity of the concealing-gate. The input signal and placement in the layout of the concealing-gates must be selected in such a way that they remain equally effective in preventing different variants of optical probing, i.e., electro-optical frequency mapping and Electro-optical probing. The methodology is suitable for the existing ASIC/FPGA design flow and fabrication process, since designing new standard logic cells is not required. We have performed a comprehensive security evaluation of the concealing-gates using a security metric developed based on the parameters that are crucial for optical probing. The attack resiliency of the logic cells, protected by concealing-gates, is evaluated using an empirical study-based simulation methodology and experimental validation. Our analysis has shown that in the presence of concealing-gates, logic cells achieve high resiliency against optical contactless probing techniques.

Halide perovskite memristors as flexible and reconfigurable physical unclonable functions

Physical Unclonable Functions (PUFs) address the inherent limitations of conventional hardware security solutions in edge-computing devices. Despite impressive demonstrations with silicon circuits and crossbars of oxide memristors, realizing efficient roots of trust for resource-constrained hardware remains a significant challenge. Hybrid organic electronic materials with a rich reservoir of exotic switching physics offer an attractive, inexpensive alternative to design efficient cryptographic hardware, but have not been investigated till date. Here, we report a breakthrough security primitive exploiting the switching physics of one dimensional halide perovskite memristors as excellent sources of entropy for secure key generation and device authentication. Measurements of a prototypical 1 kb propyl pyridinium lead iodide (PrPyr[PbI3]) weak memristor PUF with a differential write-back strategy reveals near ideal uniformity, uniqueness and reliability without additional area and power overheads. Cycle-to-cycle write variability enables reconfigurability, while in-memory computing empowers a strong recurrent PUF construction to thwart machine learning attacks.

Data-Level Parallelism Oriented Memory Access and On-Chip Buffering Mechanisms for a Loop Accelerator

Memory access latency is always a bottleneck for the performance improvement of data-intensive applications. Exploiting the memory access patterns of Data-Level Parallelism(DLP) is a promising way for loop accelerators to reduce the latency significantly. This paper proposes two DLP-oriented data provisioning mechanisms to alleviate memory access latency: 1) DLP-oriented memory access(DoMA) for efficiently utilizes the available memory bandwidth. 2) a data access patterns aware on-chip buffer(PABUF) for exploiting reuse in a user-transparent manner. Unlike those loop accelerators using traditional DMA to access global memory, DoMA efficiently reduces the transmission of useless data by adjusting the size of requests intelligently. In addition, PABUF, which manages data using DLP’s memory access patterns without software engineering efforts, allows the loop accelerators to access data in parallel. Experiments show that when our mechanisms are integrated into a loop accelerator based on Rocket Chip Coprocessor(RoCC), it can achieve 4.20x-10.65x(6.81x on average) speedups with negligible overhead of power and area compared to L1 Cache.

Optimal Multi-Operation Energy Management in Smart Microgrids in the Presence of RESs Based on Multi-Objective Improved DE Algorithm: Cost-Emission Based Optimization

Today, in various leading power utilities in developing countries, achieving optimal operational energy management and planning, taking into account the costs reduction of generation, transmission and distribution of electricity, and also reducing the emission of an environmental pollutant becomes more and more important. Optimal use of renewable energy sources (RESs) is an effective way to achieve these goals. In this regard, in this research article, an improved multi-objective differential evolutionary (IMODE) optimization algorithm is suggested and performed to dispatch electricity generations in a smart microgrid (MG) system, taking into account economy and emission as competitive issues. In this paper, a nonlinear equation of multi-objective optimization issue with various equality and inequality limitations is formulated in order to lower the total operational costs of the MG considering environmental pollution effects simultaneously. In order to address the issue of optimal operation of the MG in single-objective and multi-objective forms, an intelligent method according to the improved differential evolutionary (IDE) optimization is utilized and performed and the proposed algorithm is implemented on different problems. First, it is assumed that there is no limit to the exchange of power overhead, and secondly, the limitation of power exchange with the upstream grid is considered. In multi-objective mode, these two modes are also considered. In order to show the impact of renewable energy on the cost, in the third part of the simulations, the operation is solved with maximum participation of renewable energy sources. In the final section, the sensitivity analysis on the number of populations in this problem is performed. The obtained results of the simulation are compared to differential evolutionary (DE) and particle swarm optimization (PSO) techniques. The effectiveness of the suggested multi-operational energy management method is confirmed by applying a study case system.

Design and analysis of high performance and low power FFT for DSP datapath using Vedic Multipliers

ABSTRACT Fast Fourier Transform is one of the most efficient methods of performing computation in Digital signal processing blocks. These computations are basically performed by the inherent floating-point multiplier units residing inside the butterfly units of any FFT. To optimise an FFT for higher efficiency and performance, it is inevitable to use highly efficient adder and multiplier units within the datapath architecture of a FFT processor. This work proposes high-performance FFT units designed using optimised Vedic multiplier units for DSP processor cores. Choice of Vedic multiplier decreases power and delay overheads of design which leads to production of an efficient FFT. A comparative analysis is presented for 24-bit Vedic multiplier using nine adder variants. A separate analysis of inherent adders is also done. Using the two best proposed Vedic multipliers, FFT units of 8, 16 and 64-point are designed respectively. The designed FFT units are compared for dynamic power, area and delay with existing designs and an analysis is presented. Power efficiency of nearly 25% and delay efficiency of around 50% is achieved with respect to the existing designs. The design is simulated on Virtex-7 FPGA using Verilog HDL.

Binary Precision Neural Network Manycore Accelerator

This article presents a low-power, programmable, domain-specific manycore accelerator, Binarized neural Network Manycore Accelerator (BiNMAC), which adopts and efficiently executes binary precision weight/activation neural network models. Such networks have compact models in which weights are constrained to only 1 bit and can be packed several in one memory entry that minimizes memory footprint to its finest. Packing weights also facilitates executing single instruction, multiple data with simple circuitry that allows maximizing performance and efficiency. The proposed BiNMAC has light-weight cores that support domain-specific instructions, and a router-based memory access architecture that helps with efficient implementation of layers in binary precision weight/activation neural networks of proper size. With only 3.73% and 1.98% area and average power overhead, respectively, novel instructions such as Combined Population-Count-XNOR , Patch-Select , and Bit-based Accumulation are added to the instruction set architecture of the BiNMAC, each of which replaces execution cycles of frequently used functions with 1 clock cycle that otherwise would have taken 54, 4, and 3 clock cycles, respectively. Additionally, customized logic is added to every core to transpose 16×16-bit blocks of memory on a bit-level basis, that expedites reshaping intermediate data to be well-aligned for bitwise operations. A 64-cluster architecture of the BiNMAC is fully placed and routed in 65-nm TSMC CMOS technology, where a single cluster occupies an area of 0.53 mm 2 with an average power of 232 mW at 1-GHz clock frequency and 1.1 V. The 64-cluster architecture takes 36.5 mm 2 area and, if fully exploited, consumes a total power of 16.4 W and can perform 1,360 Giga Operations Per Second (GOPS) while providing full programmability. To demonstrate its scalability, four binarized case studies including ResNet-20 and LeNet-5 for high-performance image classification, as well as a ConvNet and a multilayer perceptron for low-power physiological applications were implemented on BiNMAC. The implementation results indicate that the population-count instruction alone can expedite the performance by approximately 5×. When other new instructions are added to a RISC machine with existing population-count instruction, the performance is increased by 58% on average. To compare the performance of the BiNMAC with other commercial-off-the-shelf platforms, the case studies with their double-precision floating-point models are also implemented on the NVIDIA Jetson TX2 SoC (CPU+GPU). The results indicate that, within a margin of ∼2.1%--9.5% accuracy loss, BiNMAC on average outperforms the TX2 GPU by approximately 1.9× (or 7.5× with fabrication technology scaled) in energy consumption for image classification applications. On low power settings and within a margin of ∼3.7%--5.5% accuracy loss compared to ARM Cortex-A57 CPU implementation, BiNMAC is roughly ∼9.7×--17.2× (or 38.8×--68.8× with fabrication technology scaled) more energy efficient for physiological applications while meeting the application deadline.

Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty

Due to limited on-chip caching, data-driven applications with large memory footprint encounter frequent cache misses. Such applications suffer from recurring miss penalty when they re-reference recently evicted cache blocks. To meet the worst-case performance requirements, Network-on-Chip (NoC) routers are provisioned with input port buffers. However, recent studies reveal that these buffers remain underutilised except during network congestion. Trace buffers are Design-for-Debug (DfD) hardware employed in NoC routers for post-silicon debug and validation. Nevertheless, they become non-functional once a design goes into production and remain in the routers left unused. In this article, we exploit the underutilised NoC router buffers and the unused trace buffers to store recently evicted cache blocks. While these blocks are stored in the buffers, future re-reference to these blocks can be replied from the NoC router. Such an opportunistic caching of evicted blocks in NoC routers significantly reduce the miss penalty. Experimental analysis shows that the proposed architectures can achieve up to 21 percent (16 percent on average) reduction in miss penalty and 19 percent (14 percent on average) improvement in overall system performance. While we have a negligible area and leakage power overhead of 2.58 and 3.94 percent, respectively, dynamic power reduces by 6.12 percent due to the improvement in performance.

Frequency-Domain-Multiplexing Single-Wire Interface and Harmonic-Rejection-Based IF Data De-Multiplexing in Millimeter-Wave MIMO Arrays

Recently, mm-wave multi-in multi-out (MIMO) arrays are garnering significant attention because of their ability to form multiple spatial beams, achieving significantly higher data rates compared to traditional phased array-based approaches. Furthermore, scalable MIMO arrays can provide many other functionalities, such as full digital beamforming and per-power amplifier (PA) digital pre-distortion. In this work, an MIMO four-element TX array architecture is presented with a frequency-domain multiplexing-based single-wire interface (SWI), breaking the tradeoff between channel-to-channel isolation and single wire (SW) bandwidth (BW). The concept of harmonic-rejection mixing (HRM) is used to de-multiplex the four modulated signals simultaneously from the SW using a single passive mixer driven by a multi-phase local oscillator (LO). The two-stage harmonic recombination circuits are implemented in baseband and, hence, achieve high channel-to-channel isolation with a low power overhead. A 60-GHz four-element TX prototype demonstrates the proposed architecture in 45-nm RF silicon-on-insulator (RFSOI) CMOS. The frequency-division-multiplexed (FDM)-based SWI can support 8-GHz total intermediate frequency (IF) BW across the four channels with 30-40-dB channel-to-channel isolation. Each TX element in the array achieves 20-35-dB conversion gain and +8.8-10.9-dBm OP1dB while consuming 225 mW/element.

DYRE: a DYnamic REconfigurable solution to increase GPGPU\u2019s reliability

General-purpose graphics processing units (GPGPUs) are extensively used in high-performance computing. However, it is well known that these devices’ reliability may be limited by the rising of faults at the hardware level. This work introduces a flexible solution to detect and mitigate permanent faults affecting the execution units in these parallel devices. The proposed solution is based on adding some spare modules to perform two in-field operations: detecting and mitigating faults. The solution takes advantage of the regularity of the execution units in the device to avoid significant design changes and reduce the overhead. The proposed solution was evaluated in terms of reliability improvement and area, performance, and power overhead costs. For this purpose, we resorted to a micro-architectural open-source GPGPU model (FlexGripPlus). Experimental results show that the proposed solution can extend the reliability by up to 57%, with overhead costs lower than 2% and 8% in area and power, respectively.

A holistic approach to power efficiency in a clock offset based Intrusion Detection Systems for Controller Area Networks

Controller Area Network (CAN) is an in-vehicle communication protocol, which provides an efficient and reliable communication link between Electronic Control Units (ECUs) in real time. Recent studies have shown that attackers can take remote control of the targeted vehicle by exploiting the vulnerabilities of the CAN protocol. Motivated by this fact, we propose an Intrusion Detection System (IDS), called Clock Offset-based IDS (COIDS), to monitor in-vehicle network activities to detect any intrusion. Precisely, COIDS measures and then exploits the clock offset of transmitter ECU’s clock for fingerprinting ECU. COIDS next leverages the derived fingerprints to construct a baseline of ECU’s normal clock behavior using an active learning technique. Based on the baseline of normal behavior, COIDS uses the Cumulative Sum method to detect any abnormal deviation in clock offset. Further, COIDS uses a sequential change-point detection technique to determine the exact time of intrusion. Generally, COIDS has to run on every ECU to monitor the network behavior. This can turn out to be a significant power overhead for a hardware-constrained ECU. Thus, we next develop a cooperative game model to optimize the active time duration of COIDS in an ECU. We performed exhaustive experiments on real world publicly available datasets primarily to assess the effectiveness of COIDS against a wide range of in-vehicle network attacks. Our results show that COIDS detects intrusions faster than the best performed IDS in the state-of-the-art. Further, the results show that our designed cooperative game model significantly reduces the power overhead of the ECU without compromising the performance.

Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks

Logic locking has emerged as a promising solution to protect integrated circuits against piracy and tampering. However, the security provided by existing logic locking techniques is often thwarted by Boolean satisfiability (SAT)-based oracle-guided attacks. Criteria for successful SAT attacks on locked circuits include: (i) the circuit under attack is fully combinational, or (ii) the attacker has scan chain access. To address the threat posed by SAT-based attacks, we adopt the dynamically obfuscated scan chain (DOSC) architecture and illustrate its resiliency against the SAT attacks when inserted into the scan chain of an obfuscated design. We demonstrate, both mathematically and experimentally, that DOSC exponentially increases the resiliency against key extraction by SAT attack and its variants. Our results show that the mathematical estimation of attack complexity correlates to the experimental results with an accuracy of 95% or better. Along with the formal proof, we model DOSC architecture to its equivalent combinational circuit and perform SAT attack to evaluate its resiliency empirically. Our experiments demonstrate that SAT attack on DOSC-inserted benchmark circuits timeout at minimal test time overhead, and while DOSC requires less than 1% area and power overhead.

Real-Time Error Detection in Nonlinear Control Systems Using Machine Learning Assisted State-Space Encoding

Successful deployment of autonomous systems in a wide range of societal applications depends on error-free operation of the underlying signal processing and control functions. Real-time error detection in nonlinear systems has mostly relied on redundancy at the component or algorithmic level causing expensive area and power overheads. This paper describes a real-time error detection methodology for nonlinear control systems for detecting sensor and actuator degradations as well as malfunctions due to soft errors in the execution of the control algorithm on a digital processor. Our approach is based on creation of a redundant check state in such a way that its value can be computed from the current states of the system as well as from a history of prior observable state values and inputs (via machine learning algorithms). By checking for consistency between the two, errors are detected with low latency. The method is demonstrated on two test case simulations - an inverted pendulum balancing problem and a sliding mode controller driven brake-by-wire (BBW) system. In addition, hardware results from error injection experiments in an ARM core representation on an FPGA and artificial sensor degradations on a self-balancing robot prove the practical feasibility of implementation.

Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems

The explosion of IoT and wearable devices determined a rising attention toward energy harvesting as source for powering these systems. In this context, many applications cannot afford the presence of a battery because of size, weight, and cost issues. Therefore, due to the intermittent nature of ambient energy sources, these systems must be able to save and restore their state, in order to guarantee progress across power interruptions. In this work, we propose a specialized backup/restore controller that dynamically tracks the memory accesses during the execution of the program. The controller then commits the changes to a snapshot in a nonvolatile memory (NVM) when a power failure is detected. Our approach does not require complex hybrid memories and can be implemented with standard components. Results on a set of benchmarks show an average 8× reduction in backup size. Thanks to our dedicated controller, the backup time is further reduced by more than 100×, with an area and power overhead of only 0.4% and 0.8%, respectively, with respect to a low-end IoT node.

Proof-of-Contribution consensus mechanism for blockchain and its application in intellectual property protection

Blockchain has received a lot of attention recently for its characteristics of decentralization, immutability, traceability, etc., making it a promising technology for the development of various applications, especially the management of various digital information. However, most current blockchain systems exhibit problems such as high computational overhead and centralization of power. Reliance on cryptocurrency in many public blockchain-based applications is another factor that has hindered the application of blockchain technology in areas other than the financial sectors. This paper proposes a new blockchain consensus mechanism based on the contributions of participants. The proposed consensus mechanism, which is called proof-of-contribution (PoC), quantifies user behaviors and actions in a blockchain-based application as contribution values calculated through an algorithm. The node that has the highest contribution value in each round of consensus gets the right to generate the next new block. PoC preserves the properties of decentralization and resistance to hard fork and does not rely on cryptocurrency, making it attractive over cryptocurrency-based consensus mechanisms like proof-of-work (PoW) for a wide variety of applications that do not have to involve cryptocurrency. Contribution values can be abstracted from applications and used in the underlying blockchain consensus process to improve the security and trustworthiness of the applications. Intellectual property (IP) protection is one such application to apply the blockchain technology and the PoC consensus mechanism. However, existing blockchain-based IP protection systems are mostly developed based on public blockchain platforms such as the Ethereum while some others are developed as consortium blockchains, thus exhibiting inherent defects such as high system requirements, long consensus delay, and low user participation. In this paper, we will use IP protection as the application scenario to illustrate the development of our PoC consensus mechanism and will compare PoC to some existing consensus mechanisms. Experimental results will show that the proposed PoC consensus mechanism preserves most of the main security characteristics of blockchain and is superior to existing consensus mechanisms, making it more secure and efficient to use blockchain technology for digital information management.

Digitally Assisted Secondary Switch-and-Compare Technique for a SAR ADC

This brief presents a secondary switch-and-compare technique to improve the energy efficiency of a SAR ADC with minimal area and power overheads. The method exploits the self-calibrated comparator in the SAR ADC to generate a supplementary LSB. Instead of a C-DAC, this switching scheme produces voltage change required to evaluate the supplementary LSB at the calibration node of the comparator. The (N+1) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> bit logic proficiently controls the secondary switching and assists the comparator in resolving the augmented LSB. A proof-of-concept (9+1)-bit 20 kS/s SAR ADC is designed in a standard 180 nm CMOS technology to demonstrate the proposed technique. The post-layout simulation results achieve energy efficiency of 51.2 fJ/conv.-step at 562 nW of average power consumption from V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 1.8 V.