Power Sleep Mode Research Articles

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

Data-retention flip-flops (DR-FF) provide an efficient state retention capability for any processor with frequent active-to-sleep mode transitions. This paper proposes new ultra-low-power balloon-based DR-FFs operating over a wide supply voltage range achieving a sleep mode power consumption as low as 380 fW, an improvement of 185× over the previously reported CMOS DR-FFs. The proposed DR-FFs have significantly lower transition mode energy consumption compared to prior-art non-volatile DR-FFs (> 18×). The proposed DR-FFs consume the lowest total energy (sleep, store and restore modes) for sleep mode times less than 520 ms. Additionally, the designed DR-FFs are comparable with most of the NV-FFs in literature for sleep times of up to 100 s, while eliminating the drawbacks of Non-volatile data retention FFs (higher/multiple supplies, integration/endurance issues).

An Ultra-Low Power 2.4 GHz Transmitter for Energy Harvested Wireless Sensor Nodes and Biomedical Devices

We present a 2.4GHz ultra-low power energy-harvested narrowband transmitter (TX) for wireless sensing and biomedical devices. We used a 434 MHz RF energy for resonant cavity based wireless power transfer (WPT). An efficiency tracking loop maximizes the power transfer efficiency of WPT and achieves an efficiency of 11.5%. The TX comprises a voltage-controlled power oscillator (VCPO) and a loop antenna which is patterned over a flexible Parylene C substrate to achieve biocompatibility. The loop antenna acts as a radiator as well as an inductive element for the VCPO, eliminating a power amplifier stage and bulky off-chip matching network. The TX is designed for low active and sleep mode power consumption to support both continuous-data mode or deeply duty cycled burst-data mode of transmission. Implemented in 0.18 μm CMOS, the TX supports OOK and FSK modulations with the sleep mode power dissipation of 128 pW. Our active RF TX consumes an active-mode power of 70 μW at 10 Mbps while radiating -33 dBm of power, resulting in an energy efficiency of 7 pJ/bit, which is the best reported till date.

An ultrasonically controlled switching system for power management in implantable devices.

In this paper, we present an ultrasonically controlled switching system that can save the battery power for implantable devices by turning the system on and off, on-demand. Ultrasonic control is employed to reduce the device size, increase the penetration depth, and reduce misalignment sensitivity associated with alternative techniques using permanent magnet and RF signal. As a proof-of-concept demonstration, a 665kHz ultrasonic signal is used to activate a piezoelectric receiver which in turn switches a battery-powered RF system on-and-off. In-vitro tests show a reliable switching functionality at distances of up to 8cm while consuming 43.5 nW (14.5nA current consumption with 3V power supply) when the system is in off-state, a factor of 10-100 times lower than the sleep-mode power consumption of typical RF SoC systems. The dimension of fabricated prototype is 6.3 × 16.7 × 2‍mm3 allowing it to be easily incorporated into many existing implantable devices.

Joint Management of Energy Consumption, Maintenance Costs, and User Revenues in Cellular Networks With Sleep Modes

We target the maximization of the operator profitability in a LTE cellular network with e-NodeBs (eNBs) exploiting sleep mode power states. The profitability is composed of different terms, namely, the electricity bill due to the eNBs energy consumption, the maintenance costs due to the application of power states to the eNBs, and the revenues from providing a given throughput to users. After showing that all these components are strictly interdependent, we formulate the problem of maximizing the profitability for a set of eNBs. In addition, we propose an algorithm, called energy maintenance revenue algorithm (EMRA), as a practical solution of the optimization problem. Results, obtained over different cellular scenarios, prove that EMRA outperforms previous algorithms, which instead focus solely on the energy bill, the maintenance costs, or the revenues in isolation, i.e., without considering them all together. Moreover, EMRA can be adapted to different network conditions and to different scenarios, bringing always a revenue for the network operator.

Energy and Spectral Efficiency of Cellular Networks With Discontinuous Transmission

Cell discontinuous transmission (DTX) has been proposed as a solution to reduce the energy consumption of cellular networks. This paper investigates the impact of network traffic load on the spectral and energy efficiency of cellular networks with DTX. The signal-to-interference-plus-noise ratio (SINR) distribution as a function of traffic load is derived first. Then, the sufficient condition for ignoring thermal noise and simplifying the SINR distribution is investigated. Based on the simplified SINR distribution, the network spectral and energy efficiency as functions of network traffic load are derived. It is shown that the network spectral efficiency increases monotonically in traffic load, while the optimal network energy efficiency depends on the ratio of the sleep-mode power consumption to the active-mode power consumption of base stations. If the ratio is larger than a certain threshold, the network energy efficiency increases monotonically with network traffic load and is maximized when the network is fully loaded. Otherwise, the network energy efficiency first increases and then decreases in network traffic load. The optimal load can be identified with a binary search algorithm. The power ratio threshold depends solely on the path loss exponent $\alpha$ , e.g., 56% for $\alpha = 4$ . All these analytic results are further validated by the numerical simulations.

Sleep-Mode Voltage Scaling

In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low-power (sleep) mode when idle and preserving application state either by retaining the data in situ in Static Random Access Memory (SRAM) or by checkpointing it to F lash . However, both of these approaches have notable drawbacks. In situ data retention requires the SRAM to remain powered in sleep mode, while checkpointing to F lash involves significant energy and time overheads. This article proposes a new ultra-low-power sleep mode for microcontrollers that overcomes the limitations of both of these approaches. Our technique, H ypnos , is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10× lower) than the typical operating voltage of the microcontroller. H ypnos exploits this observation by performing extreme voltage scaling when the microcontroller is in sleep mode. We implement and evaluate H ypnos for the TI MSP430G2452 microcontroller and show that the Microcontroller (MCU) draws only 26nA in the proposed sleep mode, which is 4× lower than a baseline sleep mode that preserves SRAM contents. Further, to reduce the overheads associated with performing the voltage scaling, we propose the use of an energy harvesting source for providing the scaled supply voltage and demonstrate (using a light sensing photodiode) that the current consumption in the proposed sleep mode can be reduced to 1nA, which is 100× lower than the current consumption in the baseline low-power mode. We also show that the decrease in sleep-mode power consumption translates to a reduction in application-level energy consumption by as much as 6.45×. By decreasing the average power consumption to such minuscule levels, H ypnos takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

A +10 dBm BLE Transmitter With Sub-400 pW Leakage for Ultra-Low Duty Cycles

A 2.4 GHz transmitter in 65 nm CMOS is optimized for extremely low duty-cycle regimes. Negative gate biasing of the main PA transistor in sleep mode achieves a 30× reduction in sleep-mode power without incurring on-performance degradation. The PA achieves a peak output power of +10.9 dBm and a total TX efficiency of 43.7%. A phase-locked loop is integrated, with direct modulation capability for the 1 Mbps GFSK modulation of Bluetooth Low Energy (BLE). The transmitter also includes a digital baseband with BLE support. Low voltage operation down to 0.68 V results in savings of both active switching power and leakage. Extensive power gating of all the blocks results in a total leakage of 370 pW for an on/off power ratio of 7.4×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> .

A 4.7nW 13ppm/°C Self-Biased Wakeup Timer Using a Switched-Resistor Scheme.

Miniaturized computing platforms typically operate under restricted battery capacity due to their size [1]. Due to low duty cycles in many sensing applications, sleep-mode power can dominate the total energy budget. Wakeup timers are a key always-on component in such sleep modes and must therefore be designed with aggressive power consumption targets (e.g., <10nW). Also, accurate timing generation is critical for peer-to-peer communication between sensor platforms [1]. Although a 32kHz crystal oscillator can provide low power [2] and accurate long-term stability, the requirement of an off-chip component complicates system integration for small wireless sensor nodes (WSNs).

A Micro Inertial Energy Harvesting Platform With Self-Supplied Power Management Circuit for Autonomous Wireless Sensor Nodes

A 0.25 cm 3 autonomous energy harvesting micro-platform is realized to efficiently scavenge, rectify and store ambient vibration energy with batteryless cold start-up and zero sleep-mode power consumption. The fabricated compact system integrates a high-performance vacuum-packaged piezoelectric MEMS energy harvester with a power management IC and surface-mount components including an ultra-capacitor. The power management circuit incorporates a rectification stage with ~30 mV voltage drop, a bias-flip stage with a novel control system for increased harvesting efficiency, a trickle charger for permanent storage of harvested energy, and a low power supply-independent bias circuitry. The overall system weighs less than 0.6 grams, does not require a pre-charged battery, and has power consumption of 0.5 µW in active-mode and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$&lt; $</tex></formula> 10 pW in sleep-mode operation. While excited with 1 g vibration, the platform is tested to charge an initially depleted 70 mF ultra-capacitor to 1.85 V in 50 minutes (at 155 Hz vibration), and a 20 mF ultra-capacitor to 1.35 V in 7.5 min (at 419 Hz). The end-to-end rectification efficiency from the harvester to the ultra-capacitor is measured as 58–86%. The system can harvest from a minimum vibration level of 0.1 g.

Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment

Retention registers have been widely used in power gated designs to store data during sleep mode. However, their excessive area and leakage power render it imperative to minimize the total retention storage size. The current industry practice replaces all registers with singlebit retention ones, which significantly limits the design freedom and yields suboptimal designs. Toward this, for the first time in the literature, we propose the concept and the design of multibit retention registers, with which only selected registers need to be replaced. The technique can significantly reduce the number of bits that need to be stored and thus the leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode by 84% along with additional mode transition latency of 6 to 11 clock cycles, compared with the singlebit retention register-based design.

From Transistors to NEMS

A rapidly growing class of battery constrained electronic applications are those with very long sleep periods, such as structural health monitoring systems, biomedical implants, and wireless border security cameras. The traditional method for sleep-mode power reduction, transistor power gating, has drawbacks, including performance loss and residual leakage. This article presents a thorough evaluation of a new nanotechnology-enabled power gating structure, CMOS-compatible NEMS switches, in the presence of aggressive supply voltage scaling. Due to the infinite off-resistance of the NEMS switches, the average power consumption of an FFT processor performing 1 FFT per hour drops by around 30 times compared to a transistor-based power gating implementation. Additionally, the low on-resistance and nanoscale size means even with current prototypes, area overhead is as much as 5 times lower, with much room for improvement. The major drawback of NEMS switches is the high activation voltage, which can be many times higher than typical CMOS supply voltages. We demonstrate that with a charge pump, these voltages can be generated on-die, and the energy and bootup delay overhead is negligible compared to the FFT processing itself. These results show that NEMS-based power-gating warrants further investigation and the fabrication of a prototype.

Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability

The new IEEE 802.3az Energy Efficient Ethernet (EEE) standard will improve significantly the energy efficiency of 10 Gbps copper transceivers by the introduction of a sleep mode for idle transmission times. The next step towards energy saving seems to be the application of similar concepts to Optical Ethernet, both for short and long range links. To this aim, this paper starts by proposing an analytical model to estimate the energy consumption of a link that uses a sleep-mode power saving mechanism. This model can be useful to answer a number of questions that need to be carefully studied. Otherwise, the complexity of optical components could be increased for the sake of an energy saving that could turn out negligible. In the rest of the paper we analyze three key questions to try to shed some light on this design decision: (a) is the new copper EEE actually outperforming the current regular optical Ethernet in terms of energy saving in such a way that optical PHYs (transceivers) actually need a green upgrade to remain more energy efficient than their copper counterparts? (b) How much energy saving could be actually achieved by EE optical Ethernet? (c) What is the transition time required to achieve a substantial energy saving at medium traffic loads on EE 10 Gb/s optical Ethernet links? The answer to the latter question sets a concrete goal for short-term research in fast on–off laser technology.

Low-Power Programmable FPGA Routing Circuitry

We consider circuit techniques for reducing field-programmable gate-array (FPGA) power consumption and propose a family of new FPGA routing switch designs that are programmable to operate in three different modes: high-speed, low-power, or sleep. High-speed mode provides similar power and performance to traditional FPGA routing switches. In low-power mode, speed is curtailed in order to reduce power consumption. Leakage is reduced by 28%-52% in low-power versus high-speed mode, depending on the particular switch design selected. Dynamic power is reduced by 28%-31% in low-power mode. Leakage power in sleep mode, which is suitable for unused routing switches, is 61%-79% lower than in high-speed mode. Each of the proposed switch designs has a different power/area/speed tradeoff. All of the designs require only minor changes to a traditional routing switch and involve relatively small area overhead, making them easy to incorporate into current commercial FPGAs. The applicability of the new switches is motivated through an analysis of timing slack in industrial FPGA designs. It is observed that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance.

Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating

The exponential increase in leakage power due to technology scaling has made power gating an attractive design choice for low-power applications. In this paper, we explore this design style in large combinational circuit blocks and latch-to-latch datapaths and introduce a novel power gating approach to yield an improved power-performance tradeoff. We first present a multiple sleep mode power gating technique where each mode represents a different point in the wake-up overhead versus leakage savings design space. We show that the high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. The multiple-mode feature allows a processor to enter power saving modes more frequently, hence, resulting in enhanced leakage savings. We apply the multimode power gating technique to datapaths where the degree of applied power gating becomes progressively stronger (harder) along the datapath. This configuration allows us to further balance wake-up overhead with leakage savings by exploiting the fact that logic circuits deep in the datapath have higher wakeup margin and hence can be strongly gated. Simulations show that multiple sleep mode capability provides an extra 17% reduction in overall leakage compared to traditional single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit.