Savings In Power Consumption Research Articles

Design and Experimental Evaluations on Energy Efficient Control Allocation Methods for Overactuated Electric Vehicles: Longitudinal Motion Case

The energy-efficient control allocation (EECA) scheme was previously proposed to distribute control efforts for overactuated systems by explicitly incorporating efficiency functions and working modes of redundant actuators. In this paper, three different real-time EECA schemes, namely adaptive EECA (A-EECA), KKT-based, and rule-based EECA, are proposed and compared for longitudinal speed tracking control of an electric ground vehicle (EGV) with two pairs of in-wheel motors. Two additional power resistor packs inserted in the dc circuits are applied to modify the operating efficiencies of two rear in-wheel motors, which are calibrated for experimental validations of the three EECA designs on a prototype EGV. In terms of the vehicle speed tracking performances, actuator dynamic responses, and total energy consumptions, both simulation and experimental results are evaluated and compared for the three distinct EECA methods. For the same EGV speed tracking effects, both simulation and experimental results indicate different power consumption savings are achieved by three EECA designs with different dynamic responses.

Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits

Low-power, compact, and high-performance NP dynamic CMOS circuits are presented in this paper assuming a 16 nm carbon nanotube transistor technology. The performances of two-stage pipeline 32-bit carry lookahead adders are evaluated based on HSPICE simulation with the following four different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, carbon nanotube MOSFET (CN-MOSFET) domino logic, and CN-MOSFET NP dynamic CMOS. While providing similar propagation delay, the total area of CN-MOSFET NP dynamic CMOS adder is reduced by 35.53%, 77.96%, and 15.52% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino adders, respectively. Miniaturization of the CN-MOSFET NP dynamic CMOS circuit reduces the dynamic switching power consumption by 80.54%, 95.57%, and 25.66% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino circuits, respectively. Furthermore, the CN-MOSFET NP dynamic CMOS adder provides up to 99.98% savings in leakage power consumption as compared to the other adder circuits that are evaluated in this study.

Modernization of the plant: Control of the compressor motor speed

This paper describes the modernization by installing frequency converters, their features and benefits as well as the disadvantages of the existing solutions and the advantages of the upgraded status. The existing state was such that the motors were switched on through the contactor and were always working at full capacity. In the new solution, one motor will be switched on through frequency converters, thus working with a particular intensity, depending on the need. This will bring savings in power consumption as well as in the maintenance.

Performance of low power Domino Circuits using pseudo dynamic buffer

this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit for different logic function, loading condition, clock frequency and power supply. Our proposed circuit reduces power consumption and power delay product of the domino circuit as compare to other domino circuit proposed earlier. All the simulation result is carried out TSMC -0.18μm CMOS technology at 1.8V power supply.

Design of the coarse-grained reconfigurable architecture DART with on-line error detection

This paper presents the implementation of the coarse-grained reconfigurable architecture (CGRA) DART with on-line error detection intended for increasing fault-tolerance. Most parts of the data paths and of the local memory of DART are protected using residue code modulo 3, whereas only the logic unit is protected using duplication with comparison. These low-cost hardware techniques would allow to tolerate temporary faults (including so called soft errors caused by radiation), provided that some technique based on re-execution of the last operation is used. Synthesis results obtained for a 90nm CMOS technology have confirmed significant hardware and power consumption savings of the proposed approach over commonly used duplication with comparison. Introducing one extra pipeline stage in the self-checking version of the basic arithmetic blocks has allowed to significantly reduce the delay overhead compared to our previous design.

SAR Algorithm Method in Photovoltaic System using MPPT

Every solar energy harvester systems has got two sources of energy loss: the MPPT circuit and the dc–dc converter. To increase the efficiency of the PV energy harvester, the energy losses from the MPPT circuit and the dc–dc converter need to be minimized. Here a new MPPT algorithm called successive approximation register is introduced. This MPPT algorithm has got a power down mode and a fast tracking time, to achieve low power consumption and energy savings. With this MPPT algorithm energy losses from the MPPT circuit can be minimized and this technique can be greatly applicable to low power application systems mainly as well as for high power application. DOI: http://dx.doi.org/10.11591/ijpeds.v3i4.4556

Perspectives on greenhouse gas emission estimates based on Australian wastewater treatment plant operating data

Primary operating data were collected from forty-six wastewater treatment plants (WWTPs) located across three states within Australia. The size range of plants was indicatively from 500 to 900,000 person equivalents. Direct and indirect greenhouse gas emissions were calculated using a mass balance approach and default emission factors, based on Australia's National Greenhouse Energy Reporting (NGER) scheme and IPCC guidelines. A Monte Carlo-type combined uncertainty analysis was applied to the some of the key emission factors in order to study sensitivity. The results suggest that Scope 2 (indirect emissions due to electrical power purchased from the grid) dominate the emissions profile for most of the plants (indicatively half to three quarters of the average estimated total emissions). This is only offset for the relatively small number of plants (in this study) that have significant on-site power generation from biogas, or where the water utility purchases grid electricity generated from renewable sources. For plants with anaerobic digestion, inventory data issues around theoretical biogas generation, capture and measurement were sometimes encountered that can skew reportable emissions using the NGER methodology. Typically, nitrous oxide (N(2)O) emissions dominated the Scope 1 (direct) emissions. However, N(2)O still only accounted for approximately 10 to 37% of total emissions. This conservative estimate is based on the 'default' NGER steady-state emission factor, which amounts to 1% of nitrogen removed through biological nitrification-denitrification processing in the plant (or indicatively 0.7 to 0.8% of plant influent total nitrogen). Current research suggests that true N(2)O emissions may be much lower and certainly not steady-state. The results of this study help to place in context research work that is focused on direct emissions from WWTPs (including N(2)O, methane and carbon dioxide of non-biogenic origin). For example, whereas non-biogenic CO(2) contributions are relatively minor, it appears that opportunities to reduce indirect emissions as a result of modest savings in power consumption are at least in the same order as those from reducing N(2)O emissions. To avoid potentially high reportable emissions under NGER guidelines, particularly for methane, the onus is placed on WWTP managers to ensure that accurate plant monitoring operating records are kept.

A new concept of planar self-reconfigurable modular robot for conveying microparts

Modularity and self-healing are two interesting properties that could help to design more flexible conveyors of micro-objects. In the Smart Blocks project, we propose to design a 2D modular and self-reconfigurable robot composed of centimeter-scale sliding blocks that embed their own actuators and control electronics. This article presents a proof-of-concept of the linkage and of the traveling system as well as an algorithm able to reconfigure a set of blocks from a spatial configuration to another one. Prototype blocks have been realized using electro-permanent magnets which show a good motion speed while saving power consumption during the linkage. Our reconfiguration algorithm is implemented in a simulator software showing in real-time the reconfiguration of the robot.

Performance modeling and evaluation of IEEE 802.11 IBSS power save mode

The IEEE 802.11 standard defines a power management algorithm for wireless LAN. In the power management for Independent Basic Service Set (IBSS), time is divided into Beacon Intervals (BIs) and each BI is divided into an Announcement Traffic Indication Message (ATIM) window and a data window. The stations that have successfully transmitted an ATIM frame within the ATIM window compete to transmit data frames in the rest of the BI. This paper analyzes the performance of the IEEE 802.11 Power Save Mode (PSM) in single hop ad hoc networks using a discrete-time Markov chain for a data frame transmission together with the corresponding ATIM frame transmission. The paper presents an analytical model to compute the throughput, average delay and power consumption in IEEE 802.11 IBSS in PSM under ideal channel and saturation conditions. The impact of network size on the throughput, delay and power consumption of the IEEE 802.11 DCF in Power Save Mode is also analyzed. This can be used to find an efficient scheme that can maximize the network throughput while saving power consumption for resource constrained ad hoc wireless networks. The analytical work is validated with simulation results obtained from Qualnet 5.0.1 network simulator.

Design and Implementation of a State-Driven Operating System for Highly Reconfigurable Sensor Networks

Due to the low-cost and low-power requirement in an individual sensor node, the available computing resources turn out to be very limited like small memory footprint and irreplaceable battery power. Sensed data fusion might be needed before being transmitted as a tradeoff between procession and transmission in consideration of saving power consumption. Even worse, the application program needs to be complicated enough to be self-organizing and dynamically reconfigurable because changes in an operating environment continue even after deployment. State-driven operating system platform offers numerous benefits in this challenging situation. It provides a powerful way to accommodate complex reactive systems like diverse wireless sensor network applications. The memory usage can be bounded within a state transition table. The complicated issues like concurrency control and asynchronous event handling capabilities can be easily achieved in a well-defined behavior of state transition diagram. In this paper, we present an efficient and effective design of the state-driven operating system for wireless sensor nodes. We describe that the new platform can operate in an extremely resource constrained situation while providing the desired concurrency, reactivity, and reconfigurability. We also compare the executing results after comparing some benchmark test results with those on TinyOS.

A Hybrid of Force and Position Control with Energy Saving in the Electro-Hydraulic System

Generally, the electro-hydraulic system (EHS) has force and position controls. The control of these parameters to the desired value multiple PID controllers are often used, which are sensitive to changes in system parameters. In addition, the existing EHS is often used as a single proportional direction control valve (PDCV) to control those parameters that cause loss and waste energy. Therefore, in this paper, a fuzzy controller is proposed to control force and position. Simultaneously, the EHS that is used for control will be added the inverter to adjust the speed of the electric motor (EM) to drive a fixed displacement gear pump, and a proportional pressure relief valve (PPRV), in order to save energy. A proposed fuzzy controller and the EHS are implemented to the hydraulic press. The experimental results showed that the hybrid of force and position control by using a fuzzy controller has a superior performance compared to the multiple PID controllers. Moreover, the proposed EHS is also more effective in saving power consumption than conventional EHS.

Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses

In this brief, an efficient implementation of reconfigurable warped digital filter with variable low-pass, high-pass, bandpass, and bandstop responses is presented. The warped filters, obtained by replacing each unit delay of a digital filter with an all-pass filter, are widely used for various audio processing applications. However, warped filters require first-order all-pass transformation to obtain variable low-pass or high-pass responses, and second-order all-pass transformation to obtain variable bandpass or bandstop responses. To overcome this drawback, the proposed method combines the warped filters with the coefficient decimation technique. The proposed architecture provides variable low-pass or high-pass responses with fine control over cut-off frequency and variable bandwidth bandpass or bandstop responses at an arbitrary center frequency without updating the filter coefficients or filter structure. The design example shows that the proposed variable digital filter is simple to design and offers substantial savings in gate counts and power consumption over other approaches.

Energy-efficient inter-frequency small cell discovery techniques for LTE-advanced heterogeneous network deployments

Heterogeneous network, or HetNet, deployments are one of the key enablers in providing ubiquitous coverage and capacity enhancements for LTE-Advanced networks. They play an important role in achieving high data rate and quality of service requirements defined for next generation wireless networks. In this article we evaluate various cell discovery techniques tailored for energy-efficient detection of small cells deployed in a carrier other than the serving macrocell. The presented schemes are evaluated using extensive system simulations conducted in a 3GPP LTE-Advanced HetNet scenario. Shortcomings of the currently standardized mechanism are analyzed, and advantages of the evaluated schemes are presented. Both the offloading opportunity utilization and savings in UE battery power consumption are analyzed. The results show that using the considered flexible, adaptive, and intelligent schemes for small cell discovery, significant UE power savings can be achieved with small loss in offloading - giving benefits both on system level as well as in user experience.

A Novel Lattice Architecture for High Speed Discrete MultiTone (DMT) Modulation

The Discrete MultiTone (DMT) modulation system is an attractive method for a high speed data transmission over a non- flat channel with possible colored noise. The IFFT is used in its transmitter in order to divide the available frequency spectrum into large independent narrow band sub-channels. A high speed and an efficient lattice architecture is proposed to implement the IFFT. This will speed up the DMT transmitter, so that, it can be easily used in any real time data transmission application. The proposed IFFT lattice architecture achieves approximately 58%, 39%, and 50% savings in gate count, power consumption, and area compared to the state of the art IFFT architectures that use conventional lattice structure. The proposed IFFT lattice architecture can perform high speed data transmission at 118 MHz. This allows the DMT transmitter to be easily integrated in any real time data transmission system.

A Switched-Capacitor Front-End for Velocity-Selective ENG Recording

Multi-electrode cuffs (MECs) have been proposed as a means for extracting additional information about the velocity and direction of nerve signals from multi-electrode recordings. This paper discusses certain aspects of the implementation of a system for velocity selective recording (VSR) where multiple neural signals are matched and summed to identify excited axon populations in terms of velocity. The approach outlined in the paper involves the replacement of the digital signal processing stages of a standard delay-matched VSR system with analogue switched-capacitor (SC) delay lines which promises significant savings in both size and power consumption. The system specifications are derived and two circuits, each composed of low-noise preamplifiers connecting to a 2nd rank SC gain stage, are evaluated. One of the systems provides a single-ended SC stage whereas the other system is fully differential. Both approaches are shown to provide the low-noise, low-power operation, practically identical channel gains and sample delay range required for VSR. Measured results obtained from chips fabricated in 0.8 μ m CMOS technology are reported.

Softcore Processor Optimization According to Real-Application Requirements

Nowadays, embedded processor cores are integrated into most system-on-chip (SoC). Processor cores can be designed to be dedicated for an SoC. However, reusing of generic processors is often preferred due to time to market constraint. Such processors have drawbacks in terms of hardware complexity and power consumption. Indeed, some of their instructions and hardware resources are useless. These area and energy inefficiencies are problematic for low-cost and low-energy systems. In this paper, we propose a methodology for automatically reducing processor functionalities and the resulting hardware complexity according to real-application requirements. This approach was evaluated on two open-source processor cores. The results show that the average area and power consumption savings are over 20% on both application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) technologies.

An elastic error correction code technique for NAND flash-based consumer electronic devices

Multi-level cell (MLC) NAND flash-based consumer electronic devices suffer from random multiple bit errors that grow exponentially with the increase of program/erase counts. Numerous error correction codes (ECCs) have been developed to detect and correct these multiple erroneous bits within a codeword, such as bose-chaudhuri-hocquenghem (BCH) and reed-solomon (RS) codes. However, most of these existing techniques do not take into account the uneven distribution of bit errors over flash pages, thus they cannot meet varying correction needs of the flash memories during its lifetime. Specifically, weak ECCs are eventually unable to correct some particular pages' bit errors beyond their correction capabilities, while powerful ECCs can protect each page longer yet incur unnecessary computation overhead too early. In this paper, an elastic error correction code (EECC) technique is proposed, which can progressively enhance the error correction capability for each page when performing program operation. In particular, based on a scalable coding mapping model, EECC technique can enhance the ECC level progressively, by allowing each page to employ changeable ECC parity in its own spare out-of-band area according to its own remaining lifetime as well as the hot level of the data in it. In this way, this technique not only meets the changing error correction demands for different page, but also obtains a good reliability-performance tradeoff. Analytically and experimentally, the results demonstrate EECC scheme is efficient in many aspects of performance, and particularly is able to make significant power consumption savings without degrading the error correction capability <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .

Static Switching Dynamic Buffer Circuit

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

Injection Based Dynamic Power Management and a Policy for Multiprocessor Systems

Power consumption has become a critical issue in designing computer systems. Dynamic power management is an approach that aims to reduce power consumption at system level by selectively placing components into low power states. Time-out and prediction based policies are often adopted in practical systems. However, they have to accurately determine the time in low power state and otherwise the saved power consumption is not worth the loss of performance. In this paper, a power management for multiprocessor systems is proposed to optimally reduce the power consumption of multiple processors. The key feature of the proposed power management is that how long to place a processor into low power state is determined in advance but not decided when a processor becomes idle. Thus, many off-time quanta are pre-determined beforehand. The proposed power management schedules the off-time quanta to processors and a processor is placed into low power state if an off-time quantum is assigned to it. It seems that processors execute special tasks which just reduce the power supplied to them. Hence, the off-time quanta are also named sleep tasks, which are virtual and injected into the original task traffic. By doing so, the inaccurate time length of sleep tasks hardly impacts on the performance, because if a processor is blocked by a sleep task there is another one available except that all the others are blocked at the same time. Then a probabilistic policy is also proposed to optimally assign sleep tasks from the waiting queue to the processors for minimum loss of performance. In the proposed policy, high priority is given to real tasks and sleep tasks are serviced only on necessity. The analysis of the probabilistic policy is performed on a queueing model and shows that the policy is asymptotically optimal. The proposed power management and policy are further examined in empirical studies.

Power Optimized Divide-By-2/3 Counter Based Clock Design Using Multiplexer

This paper proposes a advanced method of extended true-single-phase-clock (E-TSPC) based divide- by-2/3 counter design for providing low supply voltage and low power consumption. The counting logic and the mode selection control can be desingned by the help of single transistor using wired OR method. The proposed method mainly focus on for saving power consumption and it reduces the critical path between the E-TSPC flip flops (FFs) for improving the operating frequency of the counter. E-TSPC will reduce the design time, Layout area, in power-delay-product and increase the operation speed can be achieved by the proposed design and expected 1.0 to 2.0% of power reduction. The E-TSPC Prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications.