Savings In Power Consumption Research Articles

A New MIMO Scheme for Saving Power Consumption

A New MIMO Scheme for Saving Power Consumption

Utilizing waste heat from data centers with adsorptive heat transformation – Heat exchanger design and choice of adsorbent

The electricity and water consumption of data centers is growing on a global scale. A shift towards liquid cooled racks in combination with thermally driven cooling can help to reduce the electricity and water demand associated with the necessary heat rejection. To quantify the potential of adsorptive heat transformation devices in reducing the electricity and water demand, the prediction of thermal efficiency, heat flow rates and energy efficiency ratio is required. To this end, a numerical model is newly developed using basic adsorption heat exchanger theory. This model can predict the necessary performance indicators with respect to temperatures and volume flow rates, heat exchanger design and adsorbent. The full performance map of a market-available adsorption chiller (71 points) and own measurements are used for calibration and rigorous validation of the model. An average deviation (experiment vs. calculation) of 8.3 % in terms of thermal efficiency and 7.2 % in terms of heat flow rates is achieved, indicating a very good agreement for a wide range of temperatures. At a moderate liquid cooled rack outlet temperature of 50 °C, a heat rejection temperature of 26 °C and a cold aisle inlet temperature of 18 °C the cooling power of the silica gel reference chiller of 5.3 kW can be increased by 59 % to 8.5 kW at a partial energy efficiency ratio (pumps and control, no fans) of > 20 by assuming MIL-100(Fe) as adsorbent on a flat-tube lamella heat exchanger. The model can be used in subsequent annual system simulations to quantify the savings in electrical power and water consumption, which strongly depend on the ambient conditions.

Secure transmission design in cooperative NOMA networks: Orienting toward user requirements

AbstractThis paper presents a full‐duplex and multi‐antenna relay‐aided transmission scheme for the user‐oriented perspective in cooperative non‐orthogonal multiple access (NOMA) systems. Relying on the service requirements, two legitimate users with security demands (SU) and quality of service (QoS) demands (QU) are paired for NOMA execution. The security of SU is enhanced through inverse power allocation of the conventional NOMA. The QoS requirements for QU are guaranteed, simultaneously. Then, the precoding design at the multi‐antenna relay has been exploited to improve the reliability demands of SU. Closed‐form expressions for SU's outage probability (OP) and intercepted probability, as well as QU's OP, are derived. The security–reliability trade‐off is also presented. Additionally, performance analysis under the half‐duplex and multi‐antenna scheme is provided as a benchmark for comparison. Finally, numerical simulations are performed to confirm the accuracy of the theoretical derivations under different schemes. Results demonstrate the superiority of the proposed scheme over benchmark schemes in terms of improving the security and reliability of SU, as well as saving power consumption of the system.

Security Enabled New Term Weight Measure Technique with Data Driven for Next Generation Mobile Computing Networks

In the field of ASIC and FPGA, Machine Learning (ML) techniques play a major role and become predominant for accurate results for different applications like big data analysis and automotive electronics, and driverless vehicles which are required speed and power savings. Due to increasing the demand for higher accuracy, low power, low area consumption, and higher throughput for the complexity of the designs in the latest technology, the proposed system is fulfilling these demands in ASIC and FPGA domains, reconfigurable hardware architecture has been proposed it consists of an ML-based Support Vector Machine (SVM), high-speed AHB protocol and Floating point (FP) operations and also the system has the flexibility to communicate with I2C and I2S protocols. In order to increase throughput with minimal latency, the proposed architecture with AHB protocol and AHB to APB bridge is incorporated between the fabric dynamically reconfigurable multi-processor (FDPM) and peripherals along with security algorithms using SHA-256bits and AES. In order to perform ML-based applications, the proposed system is incorporated double-precision floating point (DPFP) arithmetic operations. The overall proposed architecture is developed in Verilog HDL and quality checking using the LINT tool and Clock Domain Crossing (CDC) using Spyglass tool and synthesized using DC compiler for ASIC and Vivado Design Suite 2018.1 for FPGA implementation and verification. The entire design is interfaced with the Zynq processor and SDK tool to verify data transfer between hardware and software. The obtained results show the generated custom accelerator is able to compute any complex ML classifiers for a larger amount of data. The obtained results are compared with existing state-of-art results and found that 18 % improvement in throughput, a 21 % improvement in power consumption savings, and a 34 % reduction in latency.

Multiarmed Bandit Algorithms on Zynq System-on-Chip: Go Frequentist or Bayesian?

Multiarmed Bandit (MAB) algorithms identify the best arm among multiple arms via exploration-exploitation trade-off without prior knowledge of arm statistics. Their usefulness in wireless radio, Internet of Things (IoT), and robotics demand deployment on edge devices, and hence, a mapping on system-on-chip (SoC) is desired. Theoretically, the Bayesian-approach-based Thompson sampling (TS) algorithm offers better performance than the frequentist-approach-based upper confidence bound (UCB) algorithm. However, TS is not synthesizable due to Beta function. We address this problem by approximating it via a pseudorandom number generator (PRNG)-based architecture and efficiently realize the TS algorithm on Zynq SoC. In practice, the type of arms distribution (e.g., Bernoulli, Gaussian) is unknown, and hence, a single algorithm may not be optimal. We propose a reconfigurable and intelligent MAB (RI-MAB) framework. Here, intelligence enables the identification of appropriate MAB algorithms in an unknown environment, and reconfigurability allows on-the-fly switching between algorithms on the SoC. This eliminates the need for parallel implementation of algorithms resulting in huge savings in resources and power consumption. We analyze the functional correctness, area, power, and execution time of the proposed and existing architectures for various arm distributions, word length, and hardware-software codesign approaches. We demonstrate the superiority of the RI-MAB algorithm and its architecture over the TS and UCB algorithms.

Optimization of re-configurable multi-core processors and security based on field programmable gate arrays

<div align="center">n system-on-a-chip based complex processors has the problem of multithreading and miss-functionality due to their complexity and high-speed operations. In order to minimize these problems, the proposed design has machine learning based algorithms and cryptography systems for security has been incorporated. In the proposed work, the security level has been taken care of in three different stages such as data integrity, data authentication, and private and public keys encryption and decryption. In order to increase throughput with minimal latency, the proposed architecture with advanced high-performance protocol and advanced high-performance and advanced peripheral bus bridge is incorporated between the fabric dynamically re configurable multi-processor and peripherals along with security algorithms using secure hash algorithm (SHA-256) bits and advanced encryption standard (AES). In order to perform machine learning based applications, the proposed system is incorporated double-precision floating point arithmetic operations. The overall proposed architecture is developed in verilog hybrid deep learning (HDL) and quality checking using the LINT tool. The entire design is interfaced with the Zynq processor and software development kit (SDK) tool to verify data transfer between hardware and software. The obtained results are compared with existing state-of-art results and found that 18% improvement in throughput, a 21% improvement in power consumption savings, and a 34% reduction in latency.</div>

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

GREEN COMMUNICATIONS

Green communication is an innovative research area to find radio communication and networking solutions that can significantly improve energy efficiency and resource efficiency of wireless communications without compromising the QoS of users. It contributes to global environment improvement and achieves commercial benefits for telecommunication operators. The main goal of designing green base stations is to save energy and reduce power consumption while guaranteeing user service and coverage and ensuring the base station's capability for evolution. In a wireless network base station, power consumption is the biggest issue. With global warming and energy crises becoming the most compelling environmental challenges, green solutions are a common issue to be handled. Hence, the primary focus of the “Green cellular network” is saving power in base stations to “care for planet and operator’s valet.” we reviewed a few techniques for saving power consumption and improving energy efficiency in base stations. However, many technical challenges for base station architecture redesign, heterogeneous network deployment, radio resource management, etc., need to be addressed for energy-efficient base stations.

Information Quality Improvement With Task Selection Algorithm For IoT Energy Harvesting Devices

The purpose of study is to propose a task selection algorithm that both keeps information quality and saves power consumption in IoT energy harvesting devices. The proposed algorithm not only keeps stable information quality but saves power loss also. The sensor node operation is divided into four tasks depending on the input data including battery capacity, solar panel charging current, and input sensor data variation. The task selector based on a neural network consists of an input layer, a hidden layer of 20 neurons, and an output layer. The proposed algorithm is different from the predefined task algorithm, which mainly focused on deep sleep mode or scheduled tasks. Our proposed algorithm helps the sensor node to be more adaptive to the environment based on real-time execution at each node. The collected information amount varies according to the input data variation. The experiment results show that the proposed algorithm collects higher quality information at large input data variation. The battery lifetime is also improved by up to 22%.

Enhanced NSGA-II for multi-objective energy-saving flexible job shop scheduling

To achieve green targets, manufacturing enterprises need to propose an effective energy-saving strategy for production scheduling. In this paper, a multi-objective energy-saving flexible job shop-scheduling problem (MO_EFJSP) is formulated with three criteria of optimizing the makespan, the total delay time and the total power consumption. To efficiently solve the MO_EFJSP, an enhanced non-dominated sorting genetic algorithm II (ENSGA-II) is developed. The proposed ENSGA-II has two main innovative aspects: i) the diversity of children population in a local search is achieved by performing different neighborhood search procedures on the sparse solution space so that the accuracy of the current solution is improved; ii) the weighted method is applied to select the desirable compromised solution from the Pareto solution set. By conducting extensive computational experiments based on benchmark instances and real-world case studies, it is verified that the proposed ENSGA-II is applicable for saving power consumption in a flexible job shop system. Consequently, this study makes a significant contribution to the field of green (energy-saving or energy-efficient) production scheduling.

Mechanical, microstructural and energetic evaluation of conventional and one-part alkali-activated mixtures with raw sugarcane bagasse ash

This study aimed to develop eco-friendly alkali-activated mixtures utilizing blast furnace slag (BFS) and unground sugarcane bagasse ash (SBA). One-part mixtures comprising BFS, SBA, and sodium metasilicate as dry materials were compared to conventional mixtures. Mortars and pastes were prepared with SBA replacement ratios up to 70%. At 3-days compressive strength, an increase for mixtures with 10% and 30% SBA was observed. The techniques of XRD, TG, FTIR and SEM were used to identify chemical and morphological changes caused by SBA incorporation. Utilizing raw SBA eliminated processes, saved power consumption and made employing this waste feasible.

Linear colliders based on laser-plasma accelerators

Laser-plasma accelerators are capable of sustaining accelerating fields of 10–100 GeV/m, 100–1000 times that of conventional technology and the highest fields produced by any of the widely researched advanced accelerator concepts. Laser-plasma accelerators also intrinsically accelerate short particle bunches, several orders of magnitude shorter than that of conventional technology, which leads to reductions in beamstrahlung and, hence, savings in the overall power consumption to reach a desired luminosity. These properties make laser-plasma accelerators a promising accelerator technology for a more compact, less expensive high-energy linear collider providing multi-TeV polarized leptons. In this submission to the Snowmass 2021 Accelerator Frontier, we discuss the motivation for a laser-plasma-accelerator-based linear collider, the status of the field, and potential linear collider concepts up to 15 TeV. We outline the research and development path toward a collider based on laser-plasma accelerator technology, and highlight near-term and mid-term applications of this technology on the collider development path. The required experimental facilities to carry out this research are described. We conclude with community recommendations developed during Snowmass.

P‐141: Late‐News Poster: Chroma Remapping Power Saving Technique for OLEDs

This paper proposes a novel image processing algorithm that maintains perceivable luminance as much as possible while it significantly reduces EL power consumption of OLED based upon a well‐known Helmholtz‐Kohl effect which is one of the representative theories based on human visual system's (HVS) characteristics of recognizing higher saturation images to be brighter. Proposed method effectively resolves various image artifacts incurred by the modification of ‘saturation’ value in each pixel, by carefully analyzing various image artifacts in each of problematic cases. Experimental results show that we have achieved a score of 4.18 based upon a subjective image quality evaluation methodology (Mean Opinion Score) and an average of 15.3% of EL power consumption savings were achieved in 20 evaluation images at the same time.

Improving Aquaculture Water Quality Using Dual-Input Fuzzy Logic Control for Ammonia Nitrogen Management

In this paper, a closed-loop control system using dual-input fuzzy logic theory is proposed to improve the water quality of aquaculture. The new closed-loop control system is implemented on a Raspberry-Pi-embedded platform using Python programming. The proposed closed-loop control system integrates an RS485 function, a database transfer module, a simulating variable group function, and a trigger function import to achieve savings in human resources, power, and water consumption. The proposed closed-loop control system is equipped with an ammonia nitrogen sensor and solenoid valves for the water exchange. The experimental results demonstrate that the intelligent controller can rapidly eliminate ammonia nitrogen within the range of 2.0 ppm and maintain robust control in response to changes in ammonia nitrogen excretion from a school of fish. The experimental results provide insights into the relationship between tank capacity, water exchange solenoid valves, and ammonia nitrogen degradation time, which can be used to optimize aquaculture density and improve industrialization. The experimental results demonstrate that the savings for power and water can be achieved above 95%.

SwitchX: Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars

Memristive crossbars can efficiently implementBinarized Neural Networks(BNNs) wherein the weights are stored in high-resistance states (HRS) and low-resistance states (LRS) of the synapses. We proposeSwitchXmapping of BNN weights onto ReRAM crossbars such that the impact of crossbar non-idealities, that lead to degradation in computational accuracy, are minimized. Essentially,SwitchXmaps the binary weights in such a manner that a crossbar instance comprises of more HRS than LRS synapses. We find BNNs mapped onto crossbars withSwitchXto exhibit better robustness against adversarial attacks than the standard crossbar-mapped BNNs, the baseline. Finally, we combineSwitchXwith state-aware training (that further increases the feasibility of HRS states during weight mapping) to boost the robustness of a BNN on hardware. We find that this approach yields stronger defense against adversarial attacks than adversarial training, a state-of-the-art software defense. We perform experiments on a VGG16 BNN with benchmark datasets (CIFAR-10, CIFAR-100 and TinyImagenet) and useFast Gradient Sign Method(ε = 0.05 to 0.3) andProjected Gradient Descent(\(\epsilon =\frac{2}{255}\)to\(\frac{32}{255},~\alpha =\frac{2}{255}\)) adversarial attacks. We show thatSwitchXcombined with state-aware training can yield upto ∼35% improvements in clean accuracy and ∼6–16% in adversarial accuracies against conventional BNNs. Furthermore, an important by-product ofSwitchXmapping is increased crossbar power savings, owing to an increased proportion of HRS synapses, which is furthered with state-aware training. We obtain upto ∼21–22% savings in crossbar power consumption for state-aware trained BNN mapped viaSwitchXon 16 × 16 and 32 × 32 crossbars using the CIFAR-10 and CIFAR-100 datasets.

Design of a Smart Cabin Lighting System Based on Internet of Things

With the rapid advancements in mobile devices and wireless network technologies, the Internet of Things (IoT) has become more powerful and popular than ever. The aim of IoT is to efficiently control various types of objects through wireless communications. This paper aims to design an IoT-based smart lighting system that reduces development costs and saves power consumption. Unlike public open spaces, the focus of this paper is on ship cabin spaces. As ship cabins have unique properties, such as requiring gas-based power generation and preferring a wireless environment, designing a smart cabin lighting system is crucial and has significant commercial value. The smart cabin lighting system is designed with four features. Firstly, it can automatically control the lighting devices around people using position-sensitive devices. Secondly, it enables setting on/off and adjusting the luminance for lighting devices through Touch Keypads. Thirdly, the system can be controlled using an app to turn on/off and adjust the luminance of lighting devices. Lastly, the lighting devices equipped with sensors collect specific data on cloud servers for analysis. The underlying communication protocol used to interconnect the smart lighting devices, sensors, and Touch Keypads is Zigbee. The smart cabin lighting system can be applied to marine lighting, thus improving the commercial value of enterprises related to marine lighting.

A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process

Compared with SiGe technology, the limits of low transition frequency and low transconductance per unit current of CMOS technology result in poor noise, narrow bandwidth, and high power consumption in high-speed transimpedance amplifiers. The aforementioned issues are further exacerbated while using a low-speed low-cost photodiode. In this study, an equalization technique is proposed to increase the feedback resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {R_{F}}$ </tex-math></inline-formula> , achieving low noise and bandwidth extension of the chip. A novel inductorless bandwidth extension technique is proposed to increase the bandwidth of high-speed channel by 37.5%. In addition, a new current reuse technique is proposed to inject the output stage’s tail current into the input stage to achieve a high gain, saving power consumption by 20%. We achieve 10-Gb/s operation with a 400-fF avalanche photodiode (APD) using 65-nm CMOS technology. The bandwidth is 6.8 GHz, the transimpedance gain is 66 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol{\Omega }$ </tex-math></inline-formula> , the average input-referred noise current is 11.9 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula> Hz, and the average sensitivity is −22.4 dBm at a BER of 1e−12. The SF-TIA chip takes up 0.56 mm2 and consumes 26 mA from a 3.3-V supply.

A Power-Efficient Neuromorphic Digital Implementation of Neural–Glial Interactions

Throughout the last decades, neuromorphic circuits have incited the interest of scientists, as they are potentially a powerful tool for the treatment of neurological diseases. To this end, it is essential to consider the biological principles of the CNS and develop the appropriate area- and power-efficient circuits. Motivated by studies that outline the indispensable role of astrocytes in the dynamic regulation of synaptic transmission and their active contribution to neural information processing in the CNS, in this work we propose a digital implementation of neuron–astrocyte bidirectional interactions. In order to describe the neuronal dynamics and the astrocytes’ calcium dynamics, a modified version of the original Izhikevich neuron model was combined with a linear approximation of the Postnov functional neural–glial interaction model. For the implementation of the neural–glial computation core, only three pipeline stages and a 10.10 fixed point representation were utilized. Regarding the results obtained from the FPGA implementation and the comparisons to other works, the proposed neural–glial circuit reported significant savings in area requirements (from 22.53% up to 164.20%) along with considerable savings in total power consumption of 28.07% without sacrificing output computation accuracy. Finally, an RMSE analysis was conducted, confirming that this particular implementation produces more accurate results compared to previous studies.

Digital Prototype Filter Alternatives for Processing Frequency-Stacked Mobile Sub-Bands Deploying a Single ADC for Beamforming Satellites

This paper presents a two stage approach for the processing of frequency-stacked mobile sub-bands. The frequency stacking is performed in the analogue domain to enable the use of a wideband ADC, instead of employing multiple narrowband ADCs, to support multiple antenna elements for digital satellite beamforming. This analogue front end provides a common broadband digital interface to the on-board processor and can be configured to support multiple satellite missions, reducing the cost of commissioning a digital processor for individual satellite missions. This paper proposes a framework on the specification of digital prototype filter for the Analysis of frequency-stacked mobile sub-bands. The computational complexity of the Analysis operation, with two digital filter alternatives, are evaluated. A series of results, taken from our European Space Agency sponsored project, are presented here to demonstrate the applicability of the proposed two stage approach, reporting on the savings in power consumption when an Nth-band all-pass based recursive filter having an Infinite Impulse Response is used as the digital prototype filter.

Experimental evaluation of the performance of a domestic water heating system under Baghdad climate conditions

The aim of the current study is to evaluate the performance of a domestic water heating system for residential areas in Baghdad climatic conditions for substituting electric water heaters with solar-powered water heaters using solar collectors. Many countries, such as Iraq, are sluggish with electric power issues while receiving very high solar insolation. Solar energy is a clean, non-depleting and low-cost source that can be used especially in residential areas, which forms a great percentage of energy consumption by replacing electric water heating with solar water heating to reduce electricity usage. Therefore, six flat plate solar collectors with an absorbing area of 1.92×0.85 m with one 4 mm thick glass cover are utilized for experimental investigation under the Baghdad climatic conditions. The collector was tested under steady-state settings, which assumed that sunlight intensity, ambient temperature, and inlet-outdoor temperature difference in each collector in the system were constant throughout the operation. According to the experimental results, during the test months of November, December, January, and February, the time-weighted experimental daily average collector array efficiency is found in the range of 40 % to 60 %. Furthermore, the greater energy gain and performance of the solar collector array attain a peak value at solar noon. Additionally, a solar collector with flat plates can easily achieve relatively high water temperature levels of 70 °C in the winter season. In addition, using a solar domestic hot water system as a water heater in Baghdad climatic conditions by substituting electric water heaters is useful for saving power consumption