Post Amplifier Research Articles

A Power-Proportional, Dual-Bandwidth, and Constant-Delay Receiver Front-End for Energy-Efficient Dual-Rate Optical Links

This article presents a dual-bandwidth front-end (FE) for a rapidly reconfigurable dual data rate and power-proportional optical receiver. The proof-of-concept receiver FE is capable of operation at 8- and 4-Gb/s data rates. Implemented in 65-nm CMOS technology, the proposed FE consists of a shunt-feedback transimpedance amplifier (TIA), a configurable one-stage-to-three-stage postamplifier (PA), and an offset compensation (OC) loop. By reconfiguring the number of stages in the PA, the FE maintains a near-constant delay when its bandwidth is changed. This allows synchronization to be maintained, with limited bit errors when the target data rate is switched. The prototype receiver was measured with an optical input at 8 and 4 Gb/s. The overall FE dissipates 6.12 mW at 8 Gb/s (0.76 pJ/bit) and 2.86 mW at 4 Gb/s (0.72 pJ/bit). The measured receiver optical sensitivities for 8- and 4-Gb/s inputs at high-bandwidth (HBW) and low-bandwidth (LBW) modes are −7.7 and −9.8 dBm, respectively. The measurement results confirm the matched delay through the FE with delay variations within 8 ps.

Development of an Optoelectronic Integrated Sensor for a MEMS Mirror-Based Active Structured Light System.

Micro-electro-mechanical system (MEMS) scanning micromirrors are playing an increasingly important role in active structured light systems. However, the initial phase error of the structured light generated by a scanning micromirror seriously affects the accuracy of the corresponding system. This paper reports an optoelectronic integrated sensor with high irradiance responsivity and high linearity that can be used to correct the phase error of the micromirror. The optoelectronic integrated sensor consists of a large-area photodetector (PD) and a receiving circuit, including a post amplifier, an operational amplifier, a bandgap reference, and a reference current circuit. The optoelectronic sensor chip is fabricated in a 180 nm CMOS process. Experimental results show that with a 5 V power supply, the optoelectronic sensor has an irradiance responsivity of 100 mV/(μW/cm2) and a -3 dB bandwidth of 2 kHz. The minimal detectable light power is about 19.4 nW, which satisfies the requirements of many active structured light systems. Through testing, the application of the chip effectively reduces the phase error of the micromirror to 2.5%.

A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications

To increase the light detection and ranging (LiDAR) system spatial resolution, the multiple photodetectors are typically deployed in the receiver. An equivalent linear-array receiver with multiplexing operation scheme is presented for the direct time of flight (dToF) LiDAR applications. In particular, the analog front-end (AFE) circuit of the proposed receiver mainly consists of eight transimpedance preamplifiers (preTIAs), a dummy preTIA, a post amplifier (PA) with an 8-to-1 multiplexer, an analog output buffer and a timing discriminator. The proposed AFE circuit, which achieves a transimpedance gain of ~106 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , a bandwidth of ~220 MHz, an equivalent input-referred noise current of ~5.1 pA/Hz0.5 and a channel switchover time of 6 ns, was fabricated in a 65 nm standard CMOS technology. The associated DC power consumption is 137 mW with a power supply of 2.5 V. The total area of the proposed AFE circuit, which includes the circuit core, bias circuits and I/O PADs, is approximately equal to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.2\times 1.2$ </tex-math></inline-formula> mm2.

A Receiver Front-End for VCSEL-Based Optical Links With 49 UI Turn-On Time

A fast turn-on front-end (FE) for a burst-mode nonreturn to zero (NRZ) receiver targeting vertical cavity surface-emitting laser (VCSEL)-based optical links operating at 10 Gb/s/ch is presented. Its bandwidth and power are reconfigurable for energy-efficient burst-mode operation. The circuit design for 4.9 ns power-ON time using a power-gating approach is presented. Rapid power-ON is achieved using the regeneration of a high-speed latch, activated by a quarter-rate clock. Implemented in a 65-nm CMOS technology, the proposed FE consists of a shunt-feedback transimpedance amplifier (TIA), a configurable one-stage or four-stage postamplifier (PA) and an offset compensation loop. By reconfiguring the number of stages in the PA from four to one, power dissipation, and the FE bandwidth are reduced during periods of link inactivity while still maintaining sufficient gain to allow the detection of an incoming burst. The presented work is supported by simulation and measurement results with optical inputs at 10 Gb/s. The results demonstrate a 4.9-ns turn-on time, corresponding to 49 unit intervals (UIs). The overall FE dissipates 5.7 mW at 10 Gb/s (0.57 pJ/bit) and 1.9 mW during idle periods. The complete receiver of each channel occupies an area of 95 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times81\,\,\mu \text{m}$ </tex-math></inline-formula> . A 5% area overhead is introduced by the burst sensing circuit.

TinyLFP: A Tiny Local-Field-Potential Sensor

Efficient acquisition and analysis of neural signals play a significant role in enhancing our understanding of the brain function and its abnormalities. Neural interfaces involve electrodes inserted into the brain tissues, and also hardware circuits and software to record neural activities and analyze them. Local field potentials (LFPs) are the low frequency neural signals recorded invasively capturing the dynamic extracellular neuronal activities. The information on different bands of neural oscillations (alpha, beta, theta, and gamma) in LFP signals has been used to determine brain abnormalities. LFP signals contain components with amplitudes in the range of 10- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100 ~\mu \text{V}$ </tex-math></inline-formula> , which are small and can be easily distorted by external noise sources. With the advancements in closed-loop brain stimulation paradigms, there is a need for miniaturized sensors to capture and monitor LFP signals. The sensed LFP signals can then be used to close the feedback loop in a control system to adjust stimulation parameters in a closed-loop brain stimulation device. A LFP sensor requires a low power circuit to ensure prolonged operation. In addition, an area-efficient and low-noise front end stage needs to be formed. Considering these requirements, a single-channel, power-efficient, low-noise, compact neural sensor for acquisition of LFP signals is presented. The miniaturized LFP sensor, named TinyLFP, has a low-noise first stage instrumentation amplifier for providing a pre-amplification of 100 V/V, a band pass filter with a pass band of 4–200 Hz, and a post amplifier stage with an amplification factor of 200 V/V. Overall, the device provides a gain of around 85 dB for the signals in the range of 4 to 200 Hz to be used as the first stage of a closed loop optogenetic brain stimulation device.

A Transimpedance-to-Noise Optimized Analog Front-End With High PSRR for Pulsed ToF Lidar Receivers

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, -3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area.

A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS

This paper presents a 20-Gb/s automatic gain control (AGC) amplifier in a 0.18-μm SiGe BiCMOS for high-speed applications. The proposed AGC amplifier compactly consists of a folded Gilbert variable-gain amplifier (VGA), a post amplifier (PA), a 50-Ω output buffer, and AGC loop including an open-loop peak detector (PD), a RC low-pass filter (LPF), and an error amplifier (EA). The AGC amplifier achieves the broadband characteristic by utilizing inductive peaking and capacitive degeneration as well as fT-doubler techniques to overcome the large parasitic capacitances. The proposed AGC circuits together with a linear VGA exhibits a wide gain control range of 45 dB for the received signal strength indication (RSSI). The measured AGC amplifier achieves a maximum gain of 21 dB and a -3-dB bandwidth (BW) of 20.6 GHz, which can support up to 25.4-Gb/s data rate. For the pseudorandom bit sequence (PRBS) length 231–1 with a bit-error rate (BER) of 10−12 at 20 Gb/s, the measured input dynamic range is 26 dB (20–400mVpp) and the peak-to-peak data jitter is less than 8 ps. The AGC amplifier consumes a power of 160 mW from a 3.3-V supply voltage and occupies an area of 850 μm × 850 μm.

High Sensitivity and Dynamic-Range 25 Gbaud Silicon Receiver Chipset With Current-Controlled DC Adjustment Path and Cube-Shape Ge-on-Si PD

This paper presents a high sensitivity and dynamic range 25 Gbaud optical receiver including the CMOS transimpedance amplifier (TIA) and Ge-on-Si photodetector. In the TIA with a DC bypassing path, instead of deploying a voltage-controlled path with a fixed feedback strength, a current-controlled path with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{\mathrm {m}}$ </tex-math></inline-formula> -adjusting ability is proposed to minimize the noise amplified by the feedback loop and achieve high sensitivity. In addition, in the optical part, a Ge-on-Si photodetector with cube-shape Ge is proposed to boost the responsivity, which therefore overcomes the noise contribution from the TIA and enhance the overall sensitivity of the cascaded optical receiver. The CMOS transimpedance amplifier includes a 3-stage transimpedance pre-amplifier, a 4-stage post amplifier, a CML buffer stage and a DC offset cancellation block. Measurement results show a transimpedance of 66–71 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , a SDD21 bandwidth of 18.5 GHz, an input-referred noise current density of 11.1 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula> Hz, a BER of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\times 10^{-{12}}$ </tex-math></inline-formula> @ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$26~\mu \text{A}$ </tex-math></inline-formula> and a power consumption of 105 mW. The FOM is 5.2 which is the lowest, to the best of the authors’ knowledge. The photodetector achieves a responsivity of 0.57 A/W at 1550 nm and a bandwidth of 40 GHz. The optical receiver achieves an optical sensitivity of −11.7 dBm. Compared with the prior arts, the proposed receiver demonstrates distinct sensitivity and FOM enhancement.

Compact harmonic cavity optical parametric oscillator for optical parametric amplifier seeding.

We present a broadly tunable highly efficient frequency conversion scheme, based on a low-threshold harmonic cavity optical parametric oscillator (OPO) followed by an idler-seeded power amplifier. By choosing the cavity length of the OPO equal to the 10th harmonic of its 41 MHz Yb:KGW solid-state pump laser, a very compact optical setup is achieved. A singly-resonant cavity without output coupler results in a low oscillation threshold of only 28-100 mW in the entire signal tuning range of 1.37-1.8 µm. The 2.4-4.15 µm idler radiation is coupled out at the 41 MHz pump frequency and employed to seed a post amplifier with nearly Watt-level output power. In addition, the seeder plus power amplifier concept results in clean signal and idler pulses at the fundamental repetition rate of 41 MHz with a time-bandwidth product below 0.4 and a relative intensity noise 10 dB lower compared to the solid-state pump laser.

Orbit to Orbit Intersatellite Optical Wireless Communications with Customized Information Security Management System

This paper has presented the effect of erbium doped fiber amplifier (EDFA) as a pre and post amplifier in intersatellite wireless optical communication system and it is compared with semiconductor optical amplifier (SOA) as pre and post amplifiers in the same communication system design. The study is analyzed the effect of changing propagation distances between satellites spacing. Gain and bit error rate are investigated against the transmitter input power increase in both systems. The comparison between EDFA and SOA in intersatellite optical wireless communication system with different input parameters (input power and physical amplifier dimensions) is demonstrated. We are building information security management system using FEC, which is a digital signal processing technique used to enhance data reliability.

A 10 Gb/s noise-canceled transimpedance amplifier for optical communication receivers

This study presents a noise-canceled transimpedance amplifier (TIA) for optical receivers. The proposed structure consists of a shunt feedback common source amplifier as an input stage followed by two regulated cascodes (RGC) and finally a differential to the single-ended amplifier at the output stage. By exploiting the noise-canceling technique at the input stage, 31.8% of the total output noise is canceled. In addition, the auxiliary path’s RGC circuit, as it has a low input impedance, is utilized to cancel out the photodiode (PD) large parasitic capacitance at the input stage. The proposed TIA along with post amplifiers, including packaging components, are simulated in TSMC 90 nm RF CMOS technology at the post-layout level. The TIA average input-referred current noise is equal to $$9.5\;{\text{pA}}/\sqrt {\text{Hz}}$$. The PD capacitance is considered as 325 fF for all simulations. The transimpedance gain is equal to 60 dBΩ and the 3-dB bandwidth is equal to 7 GHz. The power consumption of the proposed TIA is 3.6 mW from a 1.2 V supply voltage. The TIA occupies a chip area of 0.036 mm2.

A 2.5-Gb/s CMOS optical receiver with wide dynamic range using dual AGCs

A 2.5-Gb/s optical receiver with wide dynamic range has been developed in a 55-nm standard CMOS technology. As the input stage of the proposed optical receiver, a transimpedance amplifier of a three-cascaded inverting topology with a feedback resistor incorporates dual automatic gain controls to broaden the input dynamic range. Followed by a post amplifier and a 50-Ω output buffer, the measured input sensitivity, overload, and dynamic range of the optical receiver are respectively − 26 dBm, 3 dBm, and 29 dB for a bit-error rate of 10−12 at 2.5 Gb/s. The whole receiver draws a total current of 36 mA from a 3.3 V supply and the chip has an area of 1176 μm × 985 μm.

A Linear-Array Receiver Analog Front-End Circuit for Rotating Scanner LiDAR Application

A linear-array receiver analog front-end (AFE) circuit, which mainly consists of 16 transimpedance amplifiers (TIAs), is presented for pulsed time-of-flight (TOF) rotating scanner light detection and ranging (LiDAR) application. In particular, a single-channel TIA with a novel cascaded combination consists of a transimpedance preamplifier biased by a power supply of 1.8 V, a post amplifier (PA), and an output buffer (OB) with a 3.3-V power supply, aiming to lower the parasitic capacitance of the input stage and widen the output swing range, respectively. Meanwhile, the input-referred noise current is investigated to evaluate the detecting capability for the weak pulse current, and the crosstalk reduction schemes in circuit design and layout design are presented for the proposed AFE circuit. The proposed AFE circuit, which achieves a high gain of 100 dBΩ, a low gain of 60 dBΩ, a simulated transimpedance gain bandwidth of approximately 450 MHz, an equivalent input-referred noise current of 2.59 pA/Hz <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sup> , a signal-to-crosstalk ratio of 40.1 dB between adjacent channels, and a minimum detectable signal of 2.5 μA at SNR = 5, was fabricated in a 0.18-μm standard CMOS technology. The total area of AFE circuit, which includes the circuit core, bandgap and bias circuits, and I/O PAD, is approximately equal to 4.80 × 0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 10-Gb/s inductorless optical receiver in 0.18-μm SiGe BiCMOS

A 10-Gb/s inductorless optical receiver featuring linear characteristic has been designed and implemented using a 0.18-μm SiGe BiCMOS process. As the input stage of the proposed optical receiver, a transimpedance amplifier (TIA) of a common-emitter and common-collector topology with a feedback resistor incorporates DC offset cancellation (DOC) and automatic gain control (AGC) to improve the linearity and broaden the input dynamic range. Followed by a post amplifier and a 50-Ω output buffer, the measured input sensitivity, overload, and dynamic range of the optical receiver are respectively −19.3 dBm, −4 dBm, and 15.3 dB for a bit-error rate of 10−12 at 10 Gb/s. The whole receiver draws a total current of 24 mA from a 3.3 V supply and the chip has an area of 826 μm × 957 μm.

A 30–75 &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\text{dB}\Omega$&lt;/tex-math&gt; &lt;/inline-formula&gt; 2.5 GHz 0.13-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu\text{m}$&lt;/tex-math&gt; &lt;/inline-formula&gt; CMOS Receiver Front-End With Large Input Capacitance Tolerance for Short-Range Optical Communication

This paper describes the design and implementation of a linear optical receiver front-end for short range optical communication applications in 0.13-μm CMOS technology. While conventional optical receivers are typically implemented using limiting amplifiers (LA), emerging optical systems are expected to employ advanced modulation schemes, which require preserving the signal envelope. The proposed linear optical receiver architecture utilizes super-Gm transimpedance amplification with common-mode restoration and constant settling time automatic gain control (AGC) with background illumination cancellation to preserve the signal linearity while tolerating capacitance up to 15 pF for large area photo-detectors. Linearity aware design of transimpedance amplifiers (TIA), variable gain control (VGA), and post amplifiers (PA) are discussed before introducing an exponential generator based on the parasitic BJTs available in the used technology. Consuming 40 mW from a 1.2 V supply in the presence of ~15 pF input capacitance, the circuit achieves a binary modulation data rate of 5 Gbps with an input sensitivity of ~ 65 μA maintaining a bit-error rate (BER) <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . S-parameter measurements show a constant -3 dB bandwidth of 2.5 GHz for a wide dynamic range of ~45 dB (30-75 dBΩ) with dB-linearity error better than ±1 dB. To demonstrate the optical functionality of the architecture, an external photodiode (PDCS70T-GS) is directly wirebonded to the chip. Optical measurements confirm a sensitivity of -9.5 dBm (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) at a highest data rate of 5 Gb/s (λ = 680 nm). The noise and linearity performance of the receiver is verified using input referred integrated noise and 1 dB-compression point measurements for different gain settings.

A folded cascade-based broadband transimpedance amplifier for optical communication systems

This paper presents a high gain CMOS transimpedance amplifier (TIA) design using staggering technique to obtain high bandwidth and low gain ripple. To provide the staggered frequency response, the proposed TIA employs a π-network as a transimpedance stage along with a novel Folded Cascade-based shunt amplifier as a post amplifier stage. Simulation of the proposed TIA for 1.8V 0.18μm CMOS technology shows that a gain of 58dBΩ with 1dBΩ gain-ripple over a bandwidth of 8.1GHz can be achieved while the whole TIA circuit consumes 38.2mW from 1.8V power supply. The simulated average input noise current spectral density is about 15pA/Hz within the TIA frequency band.

A 40-Gb/s 310-fJ/b Inverter-Based CMOS Optical Receiver Front-End

This letter presents a low-power, 40-Gb/s optical receiver front-end fabricated in a 65-nm CMOS technology. Using an inverter-based topology for both the transimpedance amplifier and the post amplifier, high energy efficiency has been obtained. Cascaded amplifiers with transconductance and transimpedance combinations are utilized to acquire a bandwidth of 29.6 GHz. A low-dropout voltage regulator is applied to reduce the supply noise of the single-ended amplifiers. The prototype chip excluding output buffer consumes only 12.4 mW (310 fJ/b) at a 1.2 V single supply, and the integrated input referred noise is 9.2 $\mu \text{A}_{\mathrm { {rms}}}$ .

Low‐power 850 nm optoelectronic integrated circuit receiver fabricated in 65 nm complementary metal–oxide semiconductor technology

The authors present a low-power 850 nm Si optoelectronic integrated circuit (OEIC) receiver fabricated in standard 65 nm complementary metal–oxide semiconductor (CMOS) technology. They analyse power consumption of previously reported CMOS OEIC receivers and determine the authors receiver architecture for low-power operation. Their OEIC receiver consists of a CMOS-compatible avalanche photodetector and electronic circuits that include an inverter-based transimpedance amplifier, a tunable equaliser and a post amplifier. With the fabricated OEIC receiver, they successfully demonstrate 8 Gb/s operation with a bit-error rate <10−12 at incident optical power of −4.5 dBm. Their OEIC receiver consumes 5 mW with 1.2 V supply voltage. To the best of their knowledge, their OEIC receiver achieves the lowest energy efficiency among 850 nm CMOS OEIC receivers.

A 35-mW 30-dB Gain Control Range Current Mode Linear-in-Decibel Programmable Gain Amplifier With Bandwidth Enhancement

This paper presents the design of a programmable gain amplifier (PGA) that serves as an interface between the receiver front-end and the baseband processor. The proposed PGA design is fabricated in a commercial 0.18- μm SiGe BiCMOS process with a topology consisting of two digitally variable gain amplifiers cascaded by a post amplifier and interconnected by differential wideband matching networks that presents an overall enhanced gain bandwidth product. By using the current mode exponential gain control technique, the proposed design achieves a broad 30-dB linear-in-decibel gain range, a gain-independent output 1-dB compression point better than -10 dBm, input/output return loss better than 13 dB, a ±0.75-dB gain flatness over a multi-decade frequency range from 2.5 MHz to 1.17 GHz, a measured in-band group-delay variation of 30 ps, a 35-mW power consumption, and a 0.25- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core die area.

An inductorless CMOS single‐to‐differential transimpedance amplifier with gain‐enhanced topology and postamplifier

ABSTRACTThis article presents an inductorless single‐to‐differential (S2D) transimpedance amplifier (TIA) with gain‐enhanced topology and postamplifier (PA) for the front‐end of an optical communication receiver. Using the regulated cascode topology with S2D converter, the proposed TIA can avoid the use of extra balance–unbalance (balun) converter. In addition, by incorporating dual active feedback in the cascaded gain stages of PA, the bandwidth of the proposed circuit can be effectively extended without using any inductor. Using a standard 90 nm CMOS process, the proposed circuit exhibits a maximum transimpedance gain of 59 dB Ω and the −3 dB bandwidth of 9.6 GHz. Operated at a supply voltage of 1.2 V, the power consumption of the fabricated circuit is only 45 mW, and maximum usable data rate is 12.5‐Gb/s. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2953–2958, 2014