Positive Bias Temperature Instability Characteristics Research Articles

Investigation of Positive Bias Temperature Instability Characteristics of Fully Depleted Silicon on Insulator Tunneling Field Effect Transistor with High-k Dielectric Gate Stacks.

The positive bias temperature instability (PBTI) characteristics of fully depleted silicon on insulator (FD-SOI) tunneling field effect transistor (TFET) are investigated in comparison with those of metal oxide semiconductor field effect transistor (MOSFET) fabricated with the same technology process. Unlike some of the previously reported studies, in which the PBTI lifetime of TFET is much longer than that of MOSFET, in this study, the PBTI lifetime of TFET is found to be shorter than that of MOSFET. This result is very interesting, because degradation of electrical parameters of TFET is mainly affected by local traps near the source junction rather than global traps in the channel region. Large degradation of the electrical parameters of TFET due to PBTI stress would result from large fluctuation of the vertical electric field caused by traps near the source junction. This electric field fluctuation near the local region in TFET has more impact on electrical parameter degradation than channel conductivity fluctuation in MOSFET. Therefore, to improve the reliability characteristics of TFET, evaluation of PBTI characteristics and improvement of the quality of gate oxide near the source junction are essential.

Investigation of PBTI Degradation in Nanosheet nFETs With HfO2 Gate Dielectric by 3D-KMC Method

Stacked nanosheet transistor (NST) has been regarded as a promising candidate to enable scaling beyond FinFET for the sub-5 nm technology node due to the superior performance. However, reliability optimization from the physical perspective, which is essential for the guideline of NST cell design, still remains unclear. In this paper, we investigate positive bias temperature instability (PBTI) degradation in the ultra-scaled n-type NST with HfO2 gate dielectric by three-dimensional-kinetic Monte Carlo method considering multiple microscopic mechanisms. Gate voltage bias and temperature dependent PBTI characteristics are presented. Furthermore, the impacts of width (Wsh) and height (Hsh), key design parameters for NST, on PBTI degradation and threshold voltage shift (ΔVth) variation are evaluated. The results show that with the larger Wsh/Hsh, PBTI becomes severer but suffers less variation and the high temperature enlarges ΔVth variation. In the case of same device perimeter, PBTI is more sensitive to the narrow Hsh side.

Comprehensive Investigation of Multitraps-Induced Degradation in HfO2-Based nmosfets With Interfacial Layer by Three-Dimensional KMC Method

This paper investigates trap-induced degradation in nmosfets with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric by three-dimensional Kinetic Monte Carlo method. Multiple microscopic mechanisms including trapping/detrapping, traps coupling, and trap generation/recombination are considered in simulation. The impacts of interfacial layer (IL) SiOx on positive bias temperature instability (PBTI) and trap-assisted tunneling (TAT) are comprehensively investigated. PBTI characteristics show the variations of power laws with time, and power laws are greatly affected by stress condition, trap density, and dielectric thickness. Therefore, impressionable power laws make much complexion in lifetime prediction. Meanwhile, it is found that IL markedly reduces PBTI effects. Significantly, TAT currents of fresh devices increase with IL thickening in the same effective oxide thickness (EOT), whereas TAT currents after stress decrease with IL thickening in a specific range. It can be concluded that the IL in the proper range of thickness can effectively suppress PBTI and TAT currents.

Contact-Resistance Reduction for Strained n-FinFETs With Silicon–Carbon Source/Drain and Platinum-Based Silicide Contacts Featuring Tellurium Implantation and Segregation

Tellurium (Te) implantation was introduced to tune the effective electron Schottky barrier height (SBH) ΦBn of platinum-based silicide (PtSi) contacts formed on n-type silicon-carbon (Si:C). Te introduced by ion implantation prior to Pt deposition segregated at the PtSi:C/Si:C interface during PtSi:C formation. The presence of Te at the PtSi:C/Si:C interface leads to a low ΦBn of 120 meV for PtSi:C contacts. The integration of Te-segregated PtSi:C contacts on strained n-channel fin field-effect transistors (FinFETs) with Si:C source/drain (S/D) stressors achieves the lowering of the parasitic series resistance RSD by ~62% and increases the saturation drive current by ~22%. The Te-segregated contact-resistance reduction technology does not degrade the short-channel effects and positive-bias temperature instability characteristics of n-FinFETs with Si:C S/D. As PtSi has a low SBH for holes and is a suitable contact for p-FinFETs, this new contact-resistance reduction technology has potential to be introduced as a single-metal-silicide dual-barrier-height solution for future complementary metal-oxide-semiconductor FinFET technology.

Investigation of the Origin of $V_{T}/V_{\rm FB}$ Modulation by $\hbox{La}_{2}\hbox{O}_{3}$ Capping Layer Approaches for NMOS Application: Role of La Diffusion, Effect of Host High- $k$ Layer, and Interface Properties

The role of La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> shift with various high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> and metal gate electrodes was systematically investigated. It was found that the La concentration at the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface is mainly responsible for the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> modulation in NMOS devices, whereas the effect of the host high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> and gate electrodes on <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> is minimal. A 400-mV shift in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> from the control HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> device with minimal degradation in mobility was obtained when a La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer was inserted between the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers. It was also found that the incorporation of La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> in the dielectric stack improves device reliability in terms of breakdown and positive-bias temperature instability characteristics. The main key for the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> shift is the ability of La diffusion through the host high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> material.

Identification of electron trap location degrading low-frequency noise and PBTI in poly-Si/HfO 2/interface-layer gate-stack MOSFETs

Identification of electron trap location in HfO 2/interface-layer (IFL) of poly-Si/TiN/HfO 2/SiO 2 gate-stacked MOSFETs is successfully demonstrated through analysis of low-frequency noise and PBTI characteristics with respect to nitrogen incorporation into the gate dielectrics in fabrication process. It is found that the electron trap existing in the bulk-IFL dominantly degrades low-frequency noise (LFN) and positive bias temperature instability (PBTI). The pre-existing electron trap is considered to be generated by N incorporation into the IFL in the fabrication process of gate-first process.

Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained $\hbox{HfO}_{2}$ nMOSFET

The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric are investigated for PBTI characteristics. A roughly 50% reduction of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> shift can be achieved for the 300-nm CESL HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nMOSFET after 1000-s PBTI stressing without obvious HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface degradation, as demonstrated by the negligible charge pumping current increase (< 4%). In addition, the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film of CESL devices has a deeper trapping level (0.83 eV), indicating that most of the shallow traps (0.75 eV) in as-deposited HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film can be eliminated for CESL devices.

Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO/sub 2/ gate stack with low preexisting traps

In this letter, the positive-bias temperature instability (PBTI) characteristics of a TaN/HfN/HfO/sub 2/ gate stack with an equivalent oxide thickness (EOT) of 0.95 nm and low preexisting traps are studied. The negligible PBTI at room temperature, the so-called turn-around phenomenon, and the negative shifts of the threshold voltage (V/sub t/) are observed. A modified reaction-diffusion (R-D) model, which is based on the electric stress induced defect generation (ESIDG) mechanism, is proposed to explain the above-mentioned PBTI characteristics. In this modified R-D model, PBTI is attributed to the electron-induced breaking of Si-O bonds at interfacial layer (IL) between HfO/sub 2/ and Si substrate and the diffusion/drift of oxygen ions (O/sup -/) from Si-O bonds into HfO/sub 2/ layer under positive-bias temperature stressing. The ESIDG mechanism is responsible for the breaking of Si-O bonds. The measured activation energy (E/sub a/) is consistent with the one predicted by the ESIDG mechanism.