Thin Polysilicon Layer Research Articles

3D CMOS devices in recrystallized silicon

A 2 μm scale three-dimensional CMOS process has been developed which allows the fabrication of MOS devices in two independent active device layers. NMOS transistors have been fabricated in the substrate and CMOS devices, including inverters and ring oscillators, in a thin laser-recrystallized polysilicon layer. The processing parameters were determined carefully in order to obtain a monocrystalline top layer and to avoid any damage to the underlying devices already existing.

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Local oxidation of polysilicon over silicon (LOPOS) isolation has been characterized for use in a 0.8 μm CMOS/BULK process with reduced field oxide edge encroachment (bird's beak). Compared to the standard local oxidation of silicon (LOCOS) LOPOS adds a thin polysilicon layer between the stress relief oxide and the overlying nitride without changing the active area patterning procedure. To optimize the LOPOS structure, the thickness of the oxide and nitride layers was varied in a fully‐factorial experiment, measuring the bird's beak and checking for the presence of silicon edge defects. It was found that for a 6000Å field oxide the bird's beak can be safely reduced to ≈0.3 μm per side with LOPOS, which is significantly less than ≈0.55 μm with LOCOS. The corresponding stack consisted of . LOPOS fabricated diodes exhibited low leakage of <0.5 nA/cm2 and <0.5 pA/cm for the area and edge components, respectively, while MOS capacitors were breakdown‐free up to 8 MV/cm during voltage‐stress tests, compared to 6 MV/cm for LOCOS.

A MOS Transistor with self-aligned polysilicon source—drain

A new MOS transistor with self-aligned polysilicon source-drain (SAPSD) is demonstrated. Using a thin implant-doped polysilicon layer above the active channel region, a shallow source-drain junction with negligible leakage is realized. A novel lightly doped-drain (LDD) structure is also incorporated by diffusing dopants from the n+ polysilicon source-drain layer into the silicon substrate, forming the n- region. During the gate oxidation, a sidewall spacer is simultaneously formed by the oxidation of polysilicon source-drain sidewalls. The transistor layout area is saved by bringing the source-drain contacts onto the field oxide region. Experimental results of the new structure are presented.

The role of reflectivity change in optically induced recrystallization of thin silicon films

In this paper we study a simplified model of the fundamental mechanisms governing the radiatively induced recrystallization of a thin polysilicon layer on a heat-sink structure. It has been observed that instabilities in laser induced crystal growth on thin polysilicon layers do occur. To study these solidification instabilities we use a linear stability analysis. The reflectivity difference between the liquid and the solid phases is shown to be a source of thermal instability.

Aluminum-silicon ohmic contact on “shallow” [formula omitted] junctions

In this work various technologies for contacts of Al on n +Si have been experimentally investigated, particularly in view of their suitability to very shallow n p junctions. Special test-patterns have been used to measure the contact resistivity, while diodes reverse current density has been checked to evaluate the junction leakage induced by the aluminum-silicon interaction during sintering. Best results are obtained by depositing a thin polysilicon layer on the front surface before the doping process and the Al evaporation. In this case both the requirements of low contact resistivity (< 10 −4 ohm · cm 2) and low junction leakage current are satisfied. Comparison with the conventional Al/Si and AgTi/Si ohmic contacts has been performed.