Polysilicon Emitter Bipolar Transistors Research Articles

New Insights Into Noise Characteristics of Hot Carrier Induced Defects in Polysilicon Emitter Bipolar Junction Transistors and SiGe HBTs

Low frequency (LF) noise is a powerful and nondestructive technique for evaluating the oxide-semiconductor interface and an effective evaluating tool in characterizing electronic device’s structure and reliability. In this study, we present a systematic analysis of the striking abnormal 1/f noise behavior of the hot carrier induced defects in highspeed polysilicon emitter bipolar transistors (PE-BJTs) and SiGe HBTs. Here, the comparative results before and after hot carrier degradation reveal that low frequency noise spectra are not correlated with the density and distribution of the interfacial defects, which related to Si dangling bonds reside at the SiO2/Si interface in PE-BJTs and SiGe HBTs.

Time-Dependent Hot Carrier Degradation in Polysilicon Emitter Bipolar Transistors Under High Current and Radiation Combined Stress

A comparative combined stress-induced reliability issues between Auger hot carrier and ionizing radiation in double polysilicon bipolar transistor is investigated. The observed differences in the low-frequency noise spectra of devices with different stressing conditions could be interpreted as the differences in the defects-related noise contributions. Low-frequency noise and electrical performance degradation results show that Auger hot carriers greatly induce the atomic hydrogen depassivating the dangling bonds in grain boundaries of emitter polysilicon. However, ionizing radiation damage occurs both at SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interfaces and in the oxide layer. 1/f noise characteristics indicate that these two damages have different time dependences.

Temperature Dependent Reliability of Polysilicon Emitter Bipolar Transistors Under High Current Stress

Temperature dependent high forward current stress induced drift of electrical parameters (current gain ( ${\beta }$ ) variations, emitter resistance ( R $_{E}$ ) decrease) in polysilicon emitter bipolar transistors has been revealed. It shows that the ambient temperature surrounding the test device, i.e., the lattice temperature, plays a key role in the reliability issues of the polysilicon emitter bipolar junction transistors under high forward current stress. However, both results from technology computer-aided design (TCAD) simulation and experimental test indicate that the junction temperature only rise up to a certain extent but not very high, i.e., the widely reported self-heating effect is not the essential reason for the device damage in the case of double-polysilicon self-aligned NPN bipolar junction transistor.

Investigation of the mechanism of transport across the poly/monocrystalline silicon interface in polysilicon-emitter bipolar transistors based on variations in the interface treatment process

Electrical transport across the poly/monocrystalline silicon (poly-Si/c-Si) interface has been investigated by introducing variations in the interface treatment process affecting the thickness of the native oxide layer formed on the silicon surface. The I-V relationship characterizing the resistance associated with this interface is extracted using an improved open-collector method, which eliminates the inherent nonlinearity arising from the reverse active characteristics of the bipolar transistor. The nonohmic behavior of the interface at low electric fields is demonstrated to be consistent with direct tunneling through a rectangular barrier presented by an ultrathin interfacial oxide layer. An approximate tunnel junction model is proposed that fits the tunneling current in the low bias regime, predicting the experimentally observed increase in the low-voltage leakage current associated with ultrathin oxides. The thickness of the interfacial oxide extracted by fitting the measured data to the proposed rectangular-barrier tunnel junction model is in good agreement with reported experimental values. Finally, a relation between experimentally introduced variations in the interface treatment process and the magnitude of the resistance associated with the interface is identified, which can be quantitatively explained based on the direct tunnel junction model in terms of differences in the native oxide thickness.

An Investigation of the Effects of Emitter Pre-Deposition Temperature in Double-Diffued Polysilicon Emitter Bipolar Transistors

An Investigation of the Effects of Emitter Pre-Deposition Temperature in Double-Diffued Polysilicon Emitter Bipolar Transistors

Analytical Model and Current Gain Enhancement of Polysilicon-Emitter Contact Bipolar Transistors

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents an analytical model that simulates the current gain improvement of polysilicon-emitter bipolar transistors based on the effective recombination velocity method. The theoretical framework developed in this paper incorporates the 2-D structure effect of the polysilicon layer with columnar grain boundary, tunneling processes of holes through polysilicon/silicon interface oxide layer, and nonuniform doping concentration and bulk recombination effects in the single-crystal emitter. The study goes on to derive an analytical expression for the base current density from which the analytical expression of the current gain was then derived. The effect of oxide breakup, at the polysilicon/silicon interface, on current gain was also considered. The dependence of the current gain on temperature was analyzed numerically; the results are in good agreement with experimental data. The approach outlined in this paper allows one to avoid many of the unnecessary simplifications inherent in previous works and to clearly assess the relevance of each physical mechanism. </para>

Properties and benefits of fluorine in silicon and silicon-germanium devices

This paper reviews the behaviour of fluorine in silicon and silicon-germanium devices. Fluorine is shown to have many beneficial effects in polysilicon emitter bipolar transistors, including higher values of gain, lower emitter resistance, lower 1/f noise and more ideal base characteristics. These results are explained by passivation of trapping states at the polysilicon/silicon interface and accelerated break-up of the interfacial oxide layer. Fluorine is also shown to be extremely effective at suppressing the diffusion of boron, completely suppressing boron transient enhanced diffusion and significantly reducing boron thermal diffusion. The boron thermal diffusion suppression correlates with the appearance of a fluorine peak on the SIMS profile at approximately half the projected range of the fluorine implant, which is attributed to vacancy- fluorine clusters. When applied to bipolar technology, fluorine implantation leads to a record fT of 110 GHz in a silicon bipolar transistor.

Review of low-frequency noise behaviour of polysilicon emitter bipolar junction transistors

For many analogue integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. The authors briefly review why bipolar transistors are still of great interest and in widespread use in analogue integrated circuits. The review includes a comparison between BJTs and MOSFETs using a simple small-signal equivalent circuit with important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low-frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. After a review of the effects of different processing technologies and conditions on the noise performance of PE-BJTs, a summary of some of the key technological steps and device parameters and their effects on noise is presented. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low-frequency noise in ultrasmall geometries is a serious issue since the rate of increase of the noise dispersion is faster than that of the noise itself as the emitter geometry is scaled to smaller values. The same effect, but to a greater extent, is also observed in MOSFETs. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe or SiGeC heterojunction bipolar transistors and MOSFETs, are presented after the conclusions.

Polysilicon-emitter sige-base bipolar transistors-what happens when ge gets into the emitter?

An analytical model is developed for evaluating the effect of emitter depth variation on base and collector currents in a polysilicon-emitter SiGe-base bipolar transistor. It is shown that the base current is relatively insensitive to the Ge distribution in the single-crystalline emitter region, consistent with reported experimental results. On the other hand, the collector current and Early voltage are functions of the Ge distribution, Ge-free cap thickness, and final emitter depth. In particular, the current gain and Early voltage could have a strong dependence on emitter depth when there is a residual Ge-free layer left in the final quasi-neutral base. However, if the emitter-base junction is located in a constant-Ge region, then large current gains can be achieved that are relatively insensitive to emitter-depth variation, consistent with reported results. The inverse relationship between current gain and Early voltage is noted and contrasted with that of a wide-gap-emitter HBT.

Hot-carrier induced degradation and recovery in polysilicon-emitter bipolar transistors

The hot-carrier induced degradation in submicron polysilicon-emitter NPN bipolar transistors with different emitter geometries and its post-stress reversibility have been investigated in detail. We show that the hot-carrier induced degradation during reverse emitter–base (EB) bias stressing can alter the EB junction, as well as the collector–base junction region. Oxide/silicon interface traps and positive charged defects are generated by the hot-carrier injection, both of which cause an increase in the low bias base current, and consequently degradation in the current gain. Our results confirm that the oxide/silicon interface traps generated by electrical stressing are located in the same region as those present in unstressed devices––around the emitter perimeter. The hot-carrier induced changes are not stable even at room temperature, and are partially reversed by annealing at 300 °C, indicating the existence of both a reversible component, with a broad distribution of annealing activation energies, and an irreversible component. We suggest that more than one microscopic process determines the hot-carrier induced degradation in devices. Which process plays a dominant role in a given device may be dependent on device technologies employed and stressing conditions.

A new model for the low-frequency noise and the noise level variation in polysilicon emitter BJTs

Presents a new, physically-based model for the low-frequency noise in high-speed polysilicon emitter bipolar junction transistors (BJTs). Evidence of the low-frequency noise originating mainly from a superposition of generation-recombination (g-r) centers is presented. Measurements of the equivalent input noise spectral density (SIB) showed that for BJTs with large emitter areas (AE) S(I/sub B/) is proportional to 1/f, as expected. In contrast, the noise spectrum for BJTs with submicron A/sub E/ showed a strong variation from a 1/f-dependence, due to the presence of several g-r centers. However, the average spectrum has a frequency dependence proportional to 1/f for BJTs with large as well as small A/sub E/. The proposed model, based only on superposition of g-r centers, can predict the frequency-, current-, area-, and variation-dependency of with excellent agreement to the measured results.

Low-frequency noise in polysilicon-emitter bipolar transistors

The authors present a review of low-frequency noise (LFN) in polysilicon-emitter (PE) bipolar junction transistors (BJTs). It includes noise results from unstressed as well as stressed devices. A discussion of the possible physical origins of low-frequency noise is presented. Details of noise measurement and a simple noise equivalent circuit, with related noise spectral-density expressions, are given. The first part of the paper deals with noise in virgin or unstressed devices. It starts with a detailed discussion of low-frequency noise results in virgin devices. This includes noise in ultra-small transistors and a discussion of the possible physical origin(s) of the noise. Low-frequency noise in npn and pnp transistors and a technique to estimate the collector 1/f noise are then presented. Since devices are scaled to achieve better high-frequency performance, a discussion of low-frequency noise as a function of emitter geometry for transistors from several different technologies is presented. The second part of the paper deals with degradation of the LFN performance due to electrical stress. It begins with a discussion of degradation mechanisms, followed by a phenomenological discussion of low-frequency noise after hot-carrier (HC) stress. A discussion of the modelling of low-frequency noise after hot-carrier degradation due to reverse current or reverse bias voltage stresses is presented. The effects of forward bias degradation on the low-frequency noise in BJTs are presented and discussed. Finally, it is demonstrated that the noise in PE-BJTs is more sensitive to degradation than the DC characteristics.

Modeling the variation of the low-frequency noise in polysilicon emitter bipolar junction transistors

The variation of the low-frequency noise in polysilicon emitter bipolar junction transistors (BJTs) was investigated as a function of emitter area (A/sub E/). For individual BJTs with submicron-sized A/sub E/, the low-frequency noise strongly deviated from a 1/f-dependence. The averaged noise varied as 1/f, with a magnitude proportional to A/sub E//sup -1/, while the variation in the noise level was found to vary as A/sub E//sup -1.5/. A new expression that takes into account this deviation is proposed for SPICE modeling of the low-frequency noise. The traps responsible for the noise were located at the thin SiO/sub 2/ interface between the polysilicon and monosilicon emitter. The traps' energy level, areal concentration and capture cross-section were estimated to 0.31 eV, 6/spl times/10/sup 8/ cm/sup -2/ and 2/spl times/10/sup -19/ cm/sup 2/, respectively.

Random telegraph signal noise mechanisms in reverse base current of hot carrier-degraded submicron bipolar transistors: Effect of carrier trapping during stress on noise characteristics

We investigate physical mechanisms of random telegraph signal (RTS) noise in reverse base current of hot carrier-degraded polysilicon emitter bipolar junction transistors. RTS noise, analyzed in the time domain, is studied as a function of reverse base-emitter bias, temperature, and additional reverse-bias stress. Two-level RTS with a relative amplitude as high as 100% is observed at room temperature. The RTS amplitude varies exponentially with the applied reverse base-emitter voltage and depends weakly on temperature. The additional hot carrier stress is observed to induce changes in RTS amplitude and mean pulse widths (independent or correlated), and a disappearance/reappearance of the RTS fluctuations. The results are interpreted by a model where the RTS noise is caused by fluctuations of generation-recombination (g-r) parameters (i.e., capture cross sections and energy position in the gap) of a stress-induced complex bistable defect (CBD) at the Si/SiO2 interface. The complex defect is assumed to be either a two-state fast interface state or an interacting pair of a fast interface state with a slow neighboring border trap. The RTS amplitude is well explained by fluctuations in a single-defect electric-field-enhanced g-r rate between a finite value and naught. The RTS amplitude-bias characteristics and their temperature dependence are satisfactorily accounted for by an expression for a phonon-assisted tunneling current via a single deep-level state. The model parameters are the g-r parameters of the defect and its spatial position in the base-emitter p–n junction. The stress-induced changes in the RTS noise are attributed to the influence of log-time trapping of hot carriers on border states laying in the vicinity of a CBD center. The charged border traps interact with a CBD, changing both its g-r parameters and the RTS switching behavior. The variations in RTS parameters are related to the microscopic nature of the interaction and are discussed for the two types of the CBDs.

Investigations of impact ionization phenomena in advanced transistors and speed-power improvement of BiMOS SRAM cells based on reverse base current effect

The experimental investigations of base reverse current of integrated Si polysilicon emitter bipolar transistor and its multiplication coefficients ( M−1) vs. U cb at different I E when the device is driven at constant emitter currents are represented. Current crowding effect induced by impact ionization in advanced Si transistors and intrinsic complex instabilities and limitations affecting multiplication coefficients under variable high electric fields at low and high emitter current densities are analysed. The speed-power potential and limitations of high-density memory cells based on reverse base current effect are discussed. Speed-power possibilities and limitations of scaled down BiMOS SRAM cells are examined using numerical simulation of their capabilities to work in a memory system at different conditions.

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/ f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/ f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/ f noise in the collector current is also estimated. The area dependence of 1/ f noise in both types of transistors as well as other npn bipolar transistors are presented.

Decreased low frequency noise by hydrogen passivation of polysilicon emitter bipolar transistors

The effect of hydrogen passivation by forming gas annealing (FGA) on the bipolar junction transistor low frequency noise was investigated. The results demonstrated a reduced 1/ f noise component by a factor of five after FGA, which resulted in a reduced corner frequency. An equivalent input noise spectral density ( S I B ) dependence on base current ( I B) of S I B ∼ I 2 B and on emitter area ( A E) of S I B ∼ A E −1 was observed, both before and after FGA. The interpretations of the results were (a) the 1/ f noise was due to carrier number fluctuation, (b) the noise sources were homogeneously distributed over the polysilicon/monosilicon emitter interfacial oxide, and (c) the noise sources were passivated by hydrogen.

Behavior and effects of fluorine in annealed n+ polycrystalline silicon layers on silicon wafers

A comprehensive study is made of the behavior and effects of fluorine in n+-polysilicon layers. The polysilicon is deposited in a conventional low pressure chemical vapor deposition furnace on (100) silicon wafers, implanted with 1×1016 cm−2 F+ and 1×1016 cm−2 As+ and annealed at 850, 950, 1015, and 1065 °C. Sheet resistance, transmission electron microscopy (TEM), and secondary ion mass spectroscopy are used to obtain quantitative data for the breakup of the interfacial oxide, the epitaxial regrowth of the polysilicon layer, and the fluorine and arsenic distributions. The fluorine significantly increases both the initial oxide breakup (∼8×) and the initial polysilicon regrowth. It also produces inclusions in the layer which can affect the subsequent polysilicon regrowth and the arsenic distributions. Three regrowth stages and two regrowth mechanisms are distinguished and interpreted, and a value of ∼6×10−11 cm2 s−1 is deduced for the effective diffusivity of fluorine in polysilicon at 950 °C. The amounts of regrowth determined by TEM are compared with the corresponding changes in sheet resistance. The thermal budgets required to produce polysilicon layer regrowths of 1% and 50%, important for the performance of polysilicon emitter bipolar transistors, are given. All the thermal budgets are lower when fluorine is present.

Evaluation of transport properties of ozonized poly/mono interfaces in polysilicon emitter bipolar transistors

Temperature-dependent electrical measurements have been performed to determine hole and electron transport properties across the poly/mono interface in polysilicon emitter bipolar transistors. A tunneling probability has been extracted, and the results are correlated with noise parameters.

Degradation mechanisms in polysilicon emitter bipolar junction transistors for digital applications

This paper is a thorough overview on polysilicon bipolar junction transistors’ (BJTs) reliability, with focus on transistors for digital applications, where the base–emitter junction switches from forward to reverse bias (low fields) and the base–collector junction is reverse biased at high fields. The effects of base–emitter reverse biasing are generation, charging and discharging of traps in silicon oxide or at the Si–SiO 2 interface near the base–emitter junction; their understanding is essential to model transistor current gain degradation and low frequency noise increase. Failure modes and mechanisms, degradation kinetics, lifetime models and physical phenomena related to device aging will be discussed. The base–emitter junction is also stressed by high currents, which lead, for example, to electromigration phenomena. The base–collector junction degradation is mainly due to high field and impact-ionization effects. Reliability constraints are now an important component of a correct design methodology in deep-sub-micron integrated circuits.