Polysilicon Deposition Research Articles

Rapid Thermal Chemical Vapor Deposition of Nitrogen-Doped Polysilicon for High-Performance and High-Reliability CMOS Technology

AbstractIn this paper, a detailed study is presented for the growth kinetics of rapid thermal chemical vapor deposition (RTCVD) of nitrogen-doped polysilicon using silane and ammonia chemistry. It is found that nitrogen doping has reduced the surface roughness and grain size of the RTCVD polysilicon film. Both the deposition rate and the incubation time of film growth depend strongly on the ammonia to silane flow ratio. We have proposed a novel structure of NICER (Nitrogen Incorporation into CMOS Gate Electrode by in-situ RTCVD). High performance and highly reliable dual gate CMOS can be formed by combining rapid thermal oxidation (RTO) with RTCVD.

Chemical Vapor Deposition of Hyperpure Polysilicon on Industrial Scale

The worldwide production of semiconductor grade polysilicon for electronic application has reached nowadays the amount of 10,000 T/y. The material is produced universally by CVD of extremely purified (chloro)silanes reacting with hydrogen. A modern plant will be described operating under conditions which are optimized for energy saving and ecological purposes (closed-loop operation). Other CVD applications in use for electronic materials are described, namely polysilicon deposition on wafer back, for gettering purposes, and epitaxial layer deposition on wafer front. Last one accounts for an annual production of more than 450 MSQI (million square inches).

Low-frequency noise sources in polysilicon emitter BJT's: influence of hot-electron-induced degradation and post-stress recovery

The noise properties of polysilicon emitter bipolar transistors are studied. The influences of the various chemical treatments and annealing temperatures, prior and after polysilicon deposition, on the noise magnitude are shown. The impact of hot-electron-induced degradation and post-stress recovery on the base and collector current fluctuations are also investigated in order to determine the main noise sources of these devices and to gain insight into the physical mechanisms involved in these processes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An analytical model for determining carrier transport mechanism of polysilicon emitter bipolar transistors

An analytical model is proposed by including carrier transport mechanisms which previous unified analytical models do not consider: minority carrier combination at both sides of polysilicon-silicon interfacial oxides and thermionic emission over segregation potential barriers for determining the precise carrier transport mechanisms which govern current gain and specific emitter interfacial resistivity. This approach allows us to gain an insight into carrier transport mechanisms and provides a distinct image for polysilicon emitter bipolar devices. With the consideration of the interfacial capture cross section as a function of temperature, the dependence of current gain for devices given an HF etch prior to polysilicon deposition on temperature is first explained successfully. For improving device performance, some directive suggestions are presented. >

Rapid thermal processing of piezoresistive polycrystalline silicon films: An innovative technology for low cost pressure sensor fabrication

Abstract Rapid thermal processing is evaluated as a low cost and flexible single wafer technology to develop SOI pressure sensors, allowing the fabrication of polycrystalline piezoresistors on thermally grown silicon dioxide with a turnaround time of a few minutes. The growth kinetics and the microstructure of polysilicon films obtained by rapid thermal chemical vapour deposition using an argon-silane gas mixture are investigated as a function of the process pressure and temperature. Polysilicon films deposited at 5 mbar and at temperatures lower than 750 °C exhibit high compressive stresses and grain sizes of about 30 nm due to a high level of oxygen contamination. At 1 mbar the lower oxygen contamination enables to deposit well crystallized films, with residual tensile stresses comparable to those of classical low pressure chemical vapour deposition polysilicon and with grain sizes reaching 55 nm. Longitudinal gauge factors of boron-implanted piezoresistors patterned on polysilicon films deposited at 5 mbar and 720 °C show a maximum of 20–22 in the 2×10 19 -4×10 19 cm −3 doping range. Longitudinal gauge factors of 25–32 are measured for piezoresistors made from boron-diffused polysilicon deposited at 5 mbar and 850 °C, thus illustrating the flexible capabilities of rapid thermal processing for the silicon microsystem technology.

Integrated system for deposition of polysilicon and WSi x films

Solutions to problems encountered with today's methods for creating polycide structures are addressed with a multi-chamber single-wafer processing cluster tool.

Integrated processing of stacked-gate heterostructures: plasma-assisted low temperature processing combined with rapid thermal high-temperature processing

We discuss a novel approach to the formation of deposited stacked-gate structures that combines several different processing steps into a single chamber with multi-function oxidation, passivation and deposition capabilities. To form a Si-based stacked gate structures the following in-situ steps can be performed i) a final cleaning/passivation of the Si surface, ii) formation of the SiO 2/Si interface, iii) deposition of a single, or multi-layer dielectric, e.g., SiO 2, or an oxide/nitride/oxide (ONO) structure, and iv) deposition of a polysilicon gate electrode. We discuss the fabrication and performance of test device structures that combine remote plasma and rapid thermal processing steps, but omit the polysilicon deposition, and use al Al gate electrode instead. These structures are use to demonstrate the effectiveness of different interface formation processes.

The effect of production conditions for in situ phosphorus-doped LPCVD polysilicon in monosilane/phosphine system on the deposition process kinetics

The effect of phosphine/monosilane flow ratio value γ in the range of 0–0.02 on the apparent activation energy E a for an in situ phosphorus-doped polysilicon deposition process has been investigated. A strong dependence of E a on the γ value has been found. The marginal value of γ has been determined whereby the apparent activation energy is “saturated” and becomes practically independent on the phosphine/monosilane flow ratio. An explanation of the obtained results on the basis of two reaction paths existing for the phosphorus-doped polysilicon deposition process in the phosphine/monosilane system has been proposed.

Formation of Si–SiO2 stacked-gate structures by plasma-assisted and rapid-thermal processing: Improved device performance through process integration

Formation of Si–SiO2 stacked-gate heterostructures requires (i) preparation of Si surfaces prior to interface formation and oxide deposition, (ii) oxide deposition, (iii) polysilicon gate electrode deposition, and generally (iv) post-deposition doping of the gate electrode. Mid- and/or end-process rapid thermal annealing performed in inert or oxidizing ambients may also be necessary to optimize device performance. Four phases in the development of an integrated processing protocol for stacked-gate structures are described in which these steps have been modified, and continuously improved. Process tools have evolved from (i) single-function chambers for (a) surface cleaning/passivation, and (b) thin film deposition, to (ii) dual-function/single process plasma chambers for (a) in-situ surface cleaning and interface formation and (b) oxide deposition, and finally to (iii) multi-function/dual process chambers in which all of the above process steps are done in situ, but by more than one processing technique. This last approach has culminated in chambers which can accommodate (i) low-temperature plasma-assisted interface formation at ∼300 °C, (ii) intermediate-temperature rapid thermal dielectric and polysilicon depositions at 600–800 °C, and (iii) higher-temperature rapid thermal annealing at 900–1000 °C.

A Predictive Model for the Chemical Vapor Deposition of Polysilicon in a Cold Wall, Rapid Thermal System

The chemical vapor deposition of polysilicon from thermally activated silane in a cold wall, single‐wafer rapid thermal system was studied by experimentation at a variety of low pressure conditions, including very high temperatures. The effect of diluent gas on polysilicon deposition rates was examined using hydrogen, helium, and krypton. A mass‐transfer model for the chemical vapor deposition of polysilicon in a cold wall, rapid thermal system was developed. This model was used to produce an empirical rate expression for silicon deposition from silane by regressing kinetic parameters to fit experimental data. The resulting model provided accurate predictions over widely varying conditions in the experimental data.

Rapid Thermal Annealing in Advanced Silicon Bipolar Technology

A rapid thermal anneal (RTA) process has been investigated in detail for the applications of emitter diffusion and anneals in an advanced double‐polysilicon bipolar process. The significance of thin oxide at the emitter‐polysilicon‐to‐silicon interface for a low thermal budget process using RTA is presented in this paper. A change in wafer loading temperature from 400 to 600°C at emitter polysilicon deposition increased the emitter resistance from 30 to 700 Ω for emitter diffusion using RTA at 1025°C for 30 s. In contrast, emitter resistance of wafers that went through diffusion in a furnace at 1000°C for 15 min was insensitive to the wafer loading temperature at emitter polysilicon deposition. Such a large increase in emitter resistance for the RTA process is attributed to oxidation of the silicon surface during wafer loading at elevated temperatures at the emitter polysilicon deposition step. The interaction of RTA and subsequent heat cycles on the heavily doped polysilicon sheet resistance is discussed in the second section. Sheet resistance of arsenic‐ and boron‐doped polysilicon increased by more than 50% when the wafers were annealed in a furnace at 800°C after the RTA emitter diffusion at 1050°C for 30 min. The reverse annealing was explained by the dopant deactivation from (i) segregation to grain boundaries and (ii) return to equilibrium concentration from supersaturation and dopant precipitation. The bipolar process employs an RTA heat cycle at 850°C for 10 s to transform the C49 phase of to the low resistivity C54 phase. The short RTA cycle resulted in superior silicide morphology and low contact resistance at the interface between and n+ polysilicon layers compared to a furnace anneal process.

Arsenic gas-phase doping of polysilicon

Polysilicon layers have been doped with high uniform concentrations of arsenic in short processing times using gas‐phase doping. The polysilicon layers were doped at total system pressures from 1 to 760 Torr with arsine or tertiarybutylarsine (TBA) as gas‐phase dopant sources. An arsenic concentration as high as ≳4×1020 atm/cm3 in 100 nm polysilicon layers was measured after a 60 s diffusion in 2.4% arsine in He at 1000 °C at 760 Torr. Using tertiarybutylarsine (TBA) at 3 Torr, a sheet resistance of 2.5 kΩ/⧠ was measured in a 100 nm polysilicon layer after 12 min at 900 °C. Doping at temperatures as low as 770 °C also gave high arsenic concentrations. Finally, a 6 μm deep DRAM trench capacitor was uniformly doped with arsenic to a concentration of 8×1019 atm/cm3 using gas‐phase doping and a two‐step polysilicon deposition process.

Robust design of a polysilicon deposition process using split‐plot analysis

AbstractThe technique used for the analysis of experimental data must be appropriate for the design and treatment structures of the experiment; failure to take this into account can produce misleading results. This paper illustrates how split‐plot designs can be used for the analysis of robust design experiments. In particular, the polysilicon deposition process data presented by Phadke1 is analysed, and comparisons are made between the split‐plot analysis of the raw data and the analysis conducted using signal‐to‐noise ratios. In addition, we demonstrate how the split‐plot analysis provides information about interactions between control and noise factors, and how interaction plots can be used to assess the performance of the control factors across the levels of the noise factors. This information is particularly important to select the settings of the control factors that minimize the variation in the response induced by the noise factors.

A Characterization of the Effect of Deposition Temperature on Polysilicon Properties: Morphology, Dopability, Etchability, and Polycide Properties

Low pressure chemically vapor deposited polysilicon deposition was studied from 525 to 650°C. The silicon appears to be amorphous with a smooth surface up to 550°C and completely crystalline above 600°C. The transition region is found to be from 560 to 590°C. This transition is marked by sharp crystallographic and resistivity changes. The smooth surface morphology of the amorphous silicon is found to be preserved after doping and a 1000°C oxidation. The preservation of this smooth morphology is demonstrated to be due to the presence of a native oxide on the surface of the silicon upon exposure to atmosphere. However, an in situ anneal of amorphous silicon at 610°C results in large coarse crystals with rough surface morphology and disparate orientation. The smooth morphology of the 550°C silicon is found to be transmitted through subsequent polycide structure layers. The impact on device reliability is discussed. The amorphous silicon is found to have a higher plasma etch rate than the polysilicon.

On the behavior of rapid thermal CVD reactors

Two mathematical models are developed and applied to RTCVD reactors. They involve the resolution of momentum, heat and mass transfer equations with homogeneous and heterogeneous chemical reactions. A detailed discussion about the effects of some physical parameters is undertaken so that a fundamental understanding of gas flow patterns and the contribution of each chemical species to the deposition of polysilicon is obtained

Optimizing Polysilicon Deposition for Film Uniformity and Particles

This paper describes a three-step approach to characterize a low-pressure chemical vapor deposition (LPCVD) flat polysilicon process. The first step was to design and construct a flat polysilicon deposition furnace for reduced defectivity and improved film uniformity. The second phase was to characterize a process in this newly constructed furnace for both film uniformity and particles by using an L18 Taguchi experimental design. The third phase was to verify the recommended setting from the experimental design by processing confirmation runs. Results from the confirmation runs in the optimally constructed polysilicon furnace showed that particles can be reduced by up to 66 percent, and film uniformity can be improved by 29 percent over the current production process.

Modeling of Gas‐Phase Chemistry in the Chemical Vapor Deposition of Polysilicon in a Cold Wall System

The relative contribution of gas‐phase chemistry to deposition processes is an important issue both from the standpoint of operation and modeling of these processes. In polysilicon deposition from thermally activated silane in a cold wall rapid thermal chemical vapor deposition (RTCVD) system, the relative contribution of gas‐phase chemistry to the overall deposition rate was examined by a mass‐balance model. Evaluating the process at conditions examined experimentally, the model indicated that gas‐phase reactions may be neglected to good accuracy in predicting polysilicon deposition rate. The model also provided estimates of the level of gas‐phase‐generated associated with deposition on the cold‐process chamber walls.

Application of Constant Absorptivity Ring (Car) to Improve Polysilicon Thickness Uniformity In A Rapid Thermal Chemical Vapor Deposition Reactor

ABSTRACTRapid Thermal Chemical Vapor Deposition (RTCVD) is a promising technology for thin film deposition in advanced cluster tool systems. It is well known that, if left uncompensated, excessive heat losses that occur around the wafer edge can lead to temperature and deposition non-uniformities. Using polysilicon deposition on SiO2 as an example we have shown that deposition non-uniformity can be aggravated by absorptivity variations across the wafer. In this paper, we propose a novel approach to alleviate this problem. In this technique, the edge cooling effect is compensated by increasing the absorptivity of the substrate around its perimeter. This is achieved by etching a thin (width≈200μm) ring from the isolation oxide around the wafer perimeter prior to polysilicon deposition. During polysilicon deposition, the absorptivity of the silicon-oxide-polysilicon structure continually changes resulting in positive and negative feedback mechanisms in certain polysilicon thickness ranges determined by both modeling and experiments. However, this absorptivity always remains less than the constant absorptivity of the silicon-polysilicon ring along the perimeter which is referred to here as the Constant Absorptivity Ring (CAR). The higher absorptivity of CAR shields edge cooling effects from the rest of the wafer. In this paper, we present the results of our experiments conducted to demonstrate the effectiveness of CAR in improving uniformity of polysilicon. We show that by using CAR uniform films can be obtained in a reactor which otherwise delivers a polysilicon non-uniformity of 30-40%.

Influence of polysilicon deposition on fabrication of power polysilicon emitter bipolar transistors

The aim was to fabricate a polysilicon emitter bipolar transistor for power applications. To this end, different polysilicon deposition steps compatible with the power bipolar technology and their influence on electrical characteristics were studied.

Thermally Driven In-Situ Removal of Native Oxide Using Anhydrous Hydrogen Fluoride

ABSTRACTIn-situ native-oxide removal is critical for epitaxial single-crystal silicon deposition, for polysilicon emitters and contacts and for ultrathin gate dielectric films in integrated circuit (IC) fabrication. We have developed an in-situ, thermally-driven, anhydrous hydrogen fluoride (AHF)-based native-oxide removal technique in which the wafer is treated by AHF at low temperatures (300-400°C) and a short (10 sec) 950°C ‘spike’ in AHF-H2 immediately prior to Si deposition. This process removes native oxides formed by standard wet cleans such as HC1:H202 and NH4OH:H202, as well as native oxides formed by the clean-room ambient. Further, the technique is an effective pre-clean for both polysilicon and epitaxial silicon deposition. This flexibility, combined with other salient features such as simplicity and a low thermal budget, make the process eminently suited for IC fabrication.