Polysilicon Deposition Research Articles

Simulation-Driven Fabrication and Performance Evaluation of n-MOSFET using Silvaco Athena and Atlas: From Process to Parameters

In this work, an n-channel MOSFET of Silvaco TCAD has been fabricated and analyzed using commercially available simulation software tools, namely Athena and Atlas. The fabrication of NMOS has been done through a series of fabrication steps, which include wafer selection with appropriate orientation and phosphorus doping, oxide diffusion, boron-implantation for p-well formation, polysilicon deposition, phosphorus-implantation for heavily doped n+-regions, aluminum-deposition for source/drain contact and extraction of unused materials- all of these steps has been performed through the Athena tool. Afterward, Atlas performs several simulations to deduce the transfer characteristics curves (the ID vs. VGS curves). The various performance parameters of the fabricated device, which include the on current (Ion), the off current (Ioff), the on/off ratio, the threshold voltage (Vth), the subthreshold swing, and the Drain-Induced Barrier Lowering (DIBL), are also determined using the Atlas tool. These simulation-based analyses provide a better understanding of an NMOS device's fabrication process and a clearer physical insight into its characteristic curves and performance parameters.

Optical Recrystallization of Nanocrystalline Silicon Ribbons

The Silicon on Dust Substrate (SDS) is a gas-to-wafer process that produces multicrystalline silicon ribbons directly from gaseous feedstock (silane), avoiding the standard industry steps of polysilicon deposition, crystal growth, and wafering. The SDS technique consists of three main steps: (i) micrometric-sized silicon powder production by grinding silicon chunks; (ii) chemical vapor deposition (CVD) of silicon over this silicon powder substrate; and (iii) zone-melting recrystallization (ZMR) of the nanocrystalline pre-ribbon obtained in the CVD step. Several samples were produced by this technique. During CVD, mechanically self-sustained nanocrystalline pre-ribbons were grown over silicon powder substrates, with growth rates in the order of 50 µm/min. The ZMR process performance is substantially impacted by the pre-ribbon physical characteristics. The best and largest recrystallizations were achieved on pre-ribbons grown over powder substrates with smaller particle sizes, which also have lower substrate powder incorporation ratios. Multicrystalline silicon ribbons with crystalline areas as large as 2 × 4 cm2 were successfully produced. These areas have visible columnar crystal growth with crystal lengths up to 1 cm. The SDS ribbons’ measured resistivity confirmed the high powder content of the resulting material. The ability to produce solar cells on SDS multicrystalline silicon ribbons was demonstrated.

A Novel Conformal Thick Oxide Technology for On-Chip High-Voltage Isolation

In this letter, a novel conformal thick oxide technology is proposed and demonstrated for on-chip high-voltage isolation. The proposed technology utilizes alternate deposition and oxidation of polysilicon to form thick high-quality conformal oxide with a reasonable process time. Experimental results show that breakdown voltages (BVs) as high as 4.19 kV can be achieved with double-side, 6-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>-thick planar oxide layers formed using this technology. Excellent conformity was also observed inside deep silicon trenches. The double-side, silicon-embedded transformer (DSSET) fabricated using this isolation layer technology achieved an isolation capability of 1.84 kV.

A novel SiC power MOSFET with integrated polySi/SiC heterojunction freewheeling diode

The adoption of intrinsic body diode of SiC MOSFETs as freewheeling diode (FWD) always induces high conduction loss and reverse recovery loss, therefore it is highly desirable to integrate a low loss FWD in SiC MOSFET. In this paper, we propose a new concept of monolithically integrating a polySi/SiC heterojunction diode (HJD) in SiC planar MOSFET (HJDMOS) without sacrificing MOSFET cell density or increasing much processing complexity. The HJD is formed between the gate polysilicon and the SiC JFET region using the same polysilicon deposition, thus the MOSFET and FWD can share the JFET and drift region in a time-multiplexing way. The SiC HJDMOS not only inactivates the body diode by offering lower turn-on voltage but also shows excellent reverse recovery characteristics because the HJD behaves like a Schottky barrier diode. Meanwhile, the gate-to-drain charge (Q gd) and gate-to-drain capacitance (C gd) of the SiC HJDMOS are significantly reduced by 8.0 times and 4.6 times in comparison with the conventional MOSFET due to the reduction of the overlapping area of gate and drain region. With optimal selection of design parameters, the integrated device maintains good MOSFET performances with forward blocking voltage of >1200 V and specific on-resistance (R on,sp) of 2.2 mΩ cm2. Therefore, the obtained figure-of-merits ( and ) of SiC HJDMOS are improved by around 7.5 times and 4.3 times, respectively. The enhanced performances suggest that SiC HJDMOS is an excellent choice for high efficiency and high frequency power electronic applications.

Influence of Water-Cooled Jacket on Polysilicon CVD, Fines Formation and Thermal Loss in Komatsu Reactor

A water-cooled jacket enclosing a silicon rod could reduce the fines formation during silane pyrolysis in Komatsu reactor. However, it would result in energy loss. Especially, as the diameter of the silicon rod increases, the free space between the jacket and the silicon rod will vary, and the jacket's effect would be complicated. This work presents a numerical study of the polysilicon chemical vapor deposition (CVD), fines formation, and thermal loss during silane pyrolysis in a Komatsu reactor. The CFD software FLUENT with detailed chemical reaction model of silane decomposition was applied to predict the silicon deposition rates, fines formation and thermal loss produced by a water-cooled jacket. The effects of water-cooled jacket temperature, rod wall temperature, and the distance between water-cooled jacket and rod surface on the polysilicon deposition rate and the fines formation have been investigated. The model was verified by comparing the model predictions with the experimental measurements in the literature. The results show that the jacket wall temperature and rod diameter have a complex influence on the fines formation, CVD growth rate, and thermal loss. The jacket wall temperature should be adjusted as the rod diameter enlarges.

Phosphorus diffused LPCVD polysilicon passivated contacts with in-situ low pressure oxidation

As silicon photovoltaic technology advances, charge carrier losses at the contacted interfaces of the silicon absorber are coming to dominate power conversion efficiency. The so-called passivated contact, which provides selective charge-carrier extraction while simultaneously reducing interface recombination, is thus of significant interest for next-generation silicon solar cells. However, achieving both low recombination and low resistance to charge carrier extraction has proven challenging. Here, we present a passivated contact technology based on polysilicon deposited using low pressure chemical vapour deposition (LPCVD) over an ultra-thin silicon dioxide layer, which achieves an excellent surface passivation with implied open-circuit voltage of 735 mV, a recombination prefactor below 1 fA cm−2 and contact resistivity below 1 mΩ cm2.Key to this technology is the deposition of an ultra-thin silicon dioxide interlayer under high temperature and low pressure condition, performed in-situ within a single process with the polysilicon deposition. Additionally, the passivating contact structure maintains its electronic properties at temperatures of up to 900 °C and is compatible with existing industrial processes. The presented work therefore represents a significant advancement in industrially-applicable passivated contact technology.

Numerical Simulations of a 96-rod Polysilicon CVD Reactor

With the rapid development of the photovoltaic industry, pressurized Siemens belljar-type polysilicon CVD reactors have been enlarged from 24 rods to 96 rods in less than 10 years aimed at much greater single-reactor productivity. A CFD model of an industry-scale 96-rod CVD reactor was established to study the internal temperature distribution and the flow field of the reactor. Numerical simulations were carried out and compared with actual growth results from a real CVD reactor. Factors affecting polysilicon depositions such as inlet gas injections, flow field, and temperature distribution in the CVD reactor are studied.

Numerical simulation of polysilicon deposition characteristics in chemical vapor deposition process

This paper addresses the complex component evolution and silicon dynamic deposition characteristics in the traditional Siemens reactor. A two-dimensional heat and mass transfer model coupled with a detailed chemical reaction mechanism was developed. The distributions of temperature, velocity, and concentration are presented in detail. The influencing factors (such as feeding mole ratio, inlet velocity, base temperature and reactor pressure) on the molar concentration evolutions of ten major components and silicon growth rate were obtained and analyzed. Results show that base temperature is main influence of HCl mole fraction. In order to get more growth rate of silicon and better silicon quality, the complex operating parameters need to be reasonably designed on collaborative optimization.

Decomposition of cumulative chi-squared statistics, with some new tools for their interpretation

It is well known that the Pearson statistic $$\chi ^{2}$$ can perform poorly in studying the association between ordinal categorical variables. Taguchi’s and Hirotsu’s statistics have been introduced in the literature as simple alternatives to Pearson’s chi-squared test for contingency tables with ordered categorical variables. The aim of this paper is to shed new light on these statistics, stressing their interpretations and characteristics, providing in this way new and different interpretations of these statistics. Moreover, a theoretical scheme is developed showing the links between the different proposals and classes of cumulative chi-squared statistical tests, starting from a unifying index of heterogeneity, unalikeability and variability measures. Users of statistics may find it attractive to understand well the different proposals. Some decompositions of both statistics are also highlighted. This paper presents a case study of optimizing the polysilicon deposition process in a very large-scale integrated circuit, to identify the optimal combination of factor levels. It is obtained by means of the information coming from a correspondence analysis based on Taguchi’s statistic and regression models for binary dependent variables. A new optimal combination of factor levels is obtained, different from many others proposed in the literature for this data.

Proton Inserted SiO2 Dielectrics for Nonvolatile Memory-Thin Film Transistor

We demonstrated the nonvolatile memory functionality of both nano-crystalline silicon (nc-Si) and amorphous indium gallium zinc oxide (a-IGZO) field effect transistors (FETs) using mobile protons that are generated by very short time (within 5 minutes) hydrogen neutral beam (H-NB) treatment at room temperature (25 °C). Some researches try to hydrogen insertion process via long time (40 minutes) high-pressure hydrogen annealing (HPHA) at high temperature (400 °C) that also need several steps such as poly silicon deposition, HPHA process, and poly silicon etching process. However our hydrogen insertion process does not need any other additional process but only H-NB process during normal thin film transistor fabrication. Also the whole memory fabrication process kept under 50 °C (except SiO2 deposition process; 300 °C). These NVM-TFT(nc-Si and a-IGZO) and devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We also investigated neutral beam energy effect on non-volatile memory functionality with IGZO NVM-TFTs. The hysteresis widths of the IGZO NVM-TFTs exhibited strong linear dependency on the H-NB treatment energy. We expected this result from the energy dependent hydrogen surface density profile. The sandwiched hydrogen between insulators becomes mobile proton without annealing process. This H-NB dependent mobile proton density variation is meaningful because until now the only way to increase proton density was increasing ambient temperature or annealing time. The hydrogen neutral beam process between insulators to generate mobile proton is easily controlled by reflector bias. Our study will further provide a useful route of creating memory functionality and incorporating proton-based storage elements onto a probability of next generation flexible memorable electronics such as low power consumption flexible display panel. Figure 1

Thermal Shields for Heat Loss Reduction in Siemens-Type CVD Reactors

The use of thermal shields to reduce radiation heat loss in Siemens-type CVD reactors is analyzed, both theoretically and experimentally. The potential savings from the use of the thermal shields is first explored using a radiation heat model that takes emissivity variations with wavelength into account, which is important for materials that do not behave as gray bodies. The theoretical calculations confirm that materials with lower surface emissivity lead to higher radiation savings. Assuming that radiation heat loss is responsible for around 50% of the total power consumption, a reduction of 32.9% and 15.5% is obtained if thermal shields with constant emissivities of 0.3 and 0.7 are considered, respectively. Experiments considering different thermal shields are conducted in a laboratory CVD reactor, confirming that the real materials do not behave as gray bodies, and proving that significant energy savings in the polysilicon deposition process are obtained. Using silicon as a thermal shield leads to energy savings of between 26.5–28.5%. For wavelength-dependent emissivities, the model shows that there are significant differences in radiation heat loss, of around 25%, when compared to that of constant emissivity. The results of the model highlight the importance of having reliable data on the emissivities within the relevant range of wavelengths, and at deposition temperatures, which remains a pending issue.

Fabrication of high aspect ratio self-aligned stepped polysilicon electrode for single-crystal silicon microstructure

This paper reports a self-aligned process for the fabrication of a high aspect ratio stepped polysilicon electrode with sub-micron capacitive gaps, which increases the coupling factor in capacitive driving and sensing. In contrast to the previous works, the polysilicon electrodes, which are formed by refilling the trenches and etching back, are anchored on the surfaces of steps in the trenches and etched by two-step deep reactive ion etching. The polysilicon electrodes are self-aligned and perfectly symmetric. Because of the `U'-shaped profile produced by the refilling process, the polysilicon electrode is less sensitive to a stress gradient in Low-pressure chemical vapor deposition (LPCVD) polysilicon layer. A thin layer of heavily doped polysilicon and a low-stress polysilicon layer, instead of uniform, heavily doped polysilicon, are used to form the polysilicon electrodes without sacrificing the electrical performance, which decreases the deposition time for LPCVD significantly due to the much faster deposition of normal low-stress polysilicon. To validate the study, a single-crystal silicon length extensional mode resonator with a 300-nm capacitive gap is fabricated based on this process. The frequency of the resonator is measured to be 25.5955 MHz, with a quality factor of 67,656 under 20 Pa.

Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects

Electrical through-wafer interconnect technologies such as vertical through-silicon vias (TSVs) are essential in order to maximize performance, optimize usage of wafer real estate, and enable three-dimensional packaging in leading edge electronic and microelectromechanical systems (MEMS) products. Although copper TSVs have the advantage of low resistance, highly doped polysilicon TSVs offer designers a much larger range of processing options due to the compatibility of polysilicon with high temperatures and also with the full range of traditional CMOS processes. Large stresses are associated with both Cu and polysilicon TSVs, and their accu- rate measurement is critical for determining the keep-out zone (KOZ) of transistors and for optimizing down- stream processes to maintain high yield. This report presents the fabrication and stress characterization of 400-μm deep, 20-Ω resistance, high aspect ratio (25:1) polysilicon TSVs fabricated by deep reactive ion etching (DRIE) followed by low-pressure chemical vapor deposition (LPCVD) of polysilicon with in-situ boron doping. Micro-Raman imaging of the wafer surface showed a maximum stress of 1.2 GPa occurring at the TSV edge and a KOZ of ∼9 to 11 μm. For polysilicon TSVs, the stress distribution in the TSVs far from the wafer surface(s) was not previously well-understood due to measurement limitations. Raman spectroscopy was able to overcome this limitation; a TSV cross section was examined and stresses as a function of both depth and width of the TSVs were collected and are analyzed herein. An 1100°C postanneal was found to reduce average stresses by 40%. © 2015 Society of Photo-Optical Instrumentation Engineers (SPIE) (DOI: 10.1117/1.JMM.14.2.024001)

Nonvolatile Memory Device Using Mobile Protons via Insertion Hydrogen Neutral Beam Treatment Process between SiO2 Deposition Processes at Room Temperature

We demonstrated the nonvolatile memory functionality of nano-crystalline silicon (nc-Si) field effect transistors (FETs) using mobile protons that are generated by very short time (within 2 minutes) hydrogen neutral beam (H-NB) treatment at room temperature (25 °C). Some researches try to hydrogen insertion process via long time (40 minutes) high-pressure hydrogen annealing (HPHA) at high temperature (400 °C) that also need several steps such as poly silicon deposition, HPHA process, and poly silicon etching process. However our hydrogen insertion process does not need any other additional process but only H-NB process during normal thin film transistor fabrication. Also the whole memory fabrication process kept under 50 °C (except SiO2deposition process; 300 °C). These nc-Si devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We think that the memory characteristics are attributed to the movement of protons between the Si(gate)/SiO2(gate insulator) interface and the SiO2/nc-Si thin film (active layer) interface by the applied gate electric field. Our study will further provide a useful route of creating memory functionality and incorporating proton-based storage elements onto a modified CMOS platform for FET memory devices using nanomaterials, and probability of next generation flexible memorable electronics.

Heat losses in a CVD reactor for polysilicon production: Comprehensive model and experimental validation

This work addresses heat losses in a CVD reactor for polysilicon production. Contributions to the energy consumption of the so-called Siemens process are evaluated, and a comprehensive model for heat loss is presented. A previously-developed model for radiative heat loss is combined with conductive heat loss theory and a new model for convective heat loss. Theoretical calculations are developed and theoretical energy consumption of the polysilicon deposition process is obtained. The model is validated by comparison with experimental results obtained using a laboratory-scale CVD reactor. Finally, the model is used to calculate heat consumption in a 36-rod industrial reactor; the energy consumption due to convective heat loss per kilogram of polysilicon produced is calculated to be 22–30kWh/kg along a deposition process.

Numerical Analysis of the Chemical Vapor Deposition of Polysilicon in a Trichlorosilane and Hydrogen System

The chemical vapor deposition (CVD) is an important approach to produce polycrystalline silicon for solar energy application. In this study, a model coupled with gas reactions and surface reactions has been built and simulated the characteristic of deposition process in a trichlorosilane and hydrogen system. The influence of the surface temperature, the reactor pressure and the deposition time on the growth rate has been analyzed in detail. The conclusions are helpful to guide the polycrystalline silicon production.

Radiation heat savings in polysilicon production: Validation of results through a CVD laboratory prototype

This work aims at a deeper understanding of the energy loss phenomenon in polysilicon production reactors by the so-called Siemens process. Contributions to the energy consumption of the polysilicon deposition step are studied in this paper, focusing on the radiation heat loss phenomenon. A theoretical model for radiation heat loss calculations is experimentally validated with the help of a laboratory CVD prototype. Following the results of the model, relevant parameters that directly affect the amount of radiation heat losses are put forward. Numerical results of the model applied to a state-of-the-art industrial reactor show the influence of these parameters on energy consumption due to radiation per kilogram of silicon produced; the radiation heat loss can be reduced by 3.8% when the reactor inner wall radius is reduced from 0.78 to 0.70m, by 25% when the wall emissivity is reduced from 0.5 to 0.3, and by 12% when the final rod diameter is increased from 12 to 15cm.

Film Thickness Prediction of Poly-Silicon LPCVD Process with a Simplified Two-Step Surface Reaction Model

Poly-silicon deposition rate profiles on silicon wafers were evaluated along the axial direction and radial direction in a mass-production scale low-pressure chemical vapor deposition (MPS-LPCVD) reactor using SiH4. Numerical analysis was made by computational fluid dynamics (CFD) considering coupled chemical reactions at several temperatures around 873 K. We have performed elementary reaction simulation, which includes 19 chemical species and 33 reactions. Despite the complexity of the chemical reaction process of poly-silicon film deposition, we could conclude that Si deposition rate was mainly controlled by the surface reaction of SiH4 under LPCVD condition. The contributions of chemical species formed in the gas-phase could be ignored. Thus, we successfully simulated the experimental results with a simplified 2-step surface reaction model of SiH4. Predicted film thickness along the axial direction of the reactor agreed well with experimental results, and the 2-step reaction model proved to be a good tool for the numerical simulation of the poly-silicon deposition process in an MPS reactor.

Gate 전하를 감소시키기 위해 Separate Gate Technique을 이용한 Trench Power MOSFET

이 논문에서 Trench Power MOSFET의 스위칭 성능을 향상시키기 위한 Separate Gate Technique(SGT)을 제안하였다. Trench Power MOSFET의 스위칭 성능을 개선시키기 위해서는 낮은 gate-to-drain 전하 (Miller 전하)가 요구된다. 이를 위하여 제안된 separate gate technique은 얇은(~500A)의 poly-si을 deposition하여 sidewall을 형성함으로서, 기존의 Trench MOSFET에 비해 얇은 gate를 형성하였다. 이 효과로 gate와 drain에 overlap 되는 면적을 줄일 수 있어 gate bottom에 쌓이는 Qgd를 감소시키는 효과를 얻었고, 이에 따른 전기적인 특성을 Silvaco T-CAD silmulation tool을 이용하여 일반적인 Trench MOSFET과 성능을 비교하였다. 그 결과 Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) 및 Crss(reverse recovery capacitance : Cgd) 모두 개선되었으며, 각각 14.3%, 23%, 30%의 capacitance 감소 효과를 확인하였다. 또한 inverter circuit을 구성하여, Qgd와 capacitance 감소로 인한 24%의 reverse recovery time의 성능향상을 확인하였다. 또한 제안된 소자는 기존 소자와 비교하여 어떠한 전기적 특성저하 없이 공정이 가능하다. In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.

Exploring polysilicon deposition conditions through a laboratory CVD prototype

AbstractCost and energy consumption related to obtaining polysilicon impact significantly on the total photovoltaic module cost and its energy payback time. Process simplifications can be performed, leading to cost reductions. Nowadays, among several approaches currently pursued to produce the so called Solar Grade Silicon, the chemical route, named Siemens process, is the dominant one. At the Instituto de Energía Solar research on this topic is focused on the chemical route, in particular on the polysilicon deposition step by chemical vapor deposition (CVD) from Trichlorosilane through a laboratory prototype. Valuable information about the phenomena involved in the polysilicon deposition process and the operating conditions is obtained from our experiments. A particular feature of our system is the inclusion of a mass spectrometer. The present work comprises spectra characterization of the polysilicon deposition chemical reaction, temperature and inlet gas mixture composition influence on the deposition rate and analysis of polysilicon deposition conditions for the ‘pop‐corn' phenomenon to appear, based on experimental experience (© 2012 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)