Polysilicon Thin Film Research Articles

In-line method for extracting the temperature coefficient of resistance of surface-micromachined polysilicon thin films

A method to in-line extract the temperature coefficient of resistance of polysilicon thin films is proposed. It is composed of two polysilicon microbeams with the same width and thickness but different lengths. The effects of all heat exchange by convection, radiation and heat transfer through the air gap and into substrates are considered in the electrothermal model of the polysilicon microbeams. In our measurements, by using parameter best fitting analysis of the theoretical curves with the experiment I– V curves of the two beams and its transient state cooling characteristics, the surface-micromachined polysilicon thin films with p + doped and a sheet resistance 116.25 Ω/sq., the linear temperature coefficient, −5.4354 × 10 −4 K −1, and the quadratic temperature coefficient, −4.7312 × 10 −6 K −2, can be obtained. The proposed method is suitable for the in-line extraction of the temperature coefficient of resistance for the surface-micromachined polysilicon thin films.

Sensitivity of Suspended-Gate Polysilicon TFTs to Charge Variation and Application to DNA Recognition

Suspended-Gate Polysilicon Thin Film Transistors, namely SGTFT, are fabricated using low temperature surface micro-machining process. When using sub-micronic gap, high field effect induces large shift of the transfer characteristics due to any charge variation inside the gap. The device was used in measurements of pH of different solutions with high sensitivity (~250 mV/pH), 4 times the theoretical Nernstian response and the usual value given by the known transducers. This high sensitivity, un-reached until now, is explained by the charge distribution induced by the high applied field. Application of the device is extended to DNA recognition with high and rapid answer. Whatever the application, SGTFT is sensitive to charge variation. Selectivity can be insured by the detection principle that is based on the couple DNA/complementary DNA in the case of DNA recognition

High-Performance Low Temperature Poly-Silicon Thin Film Transistors Fabricated by Excimer Laser Irradiation with Bottom-Gate Scheme

In this work, high-performance low-temperature poly-Silicon bottom-gate TFTs with single grain boundary perpendicular to the current flow in the channel regions have been demonstrated. A lateral grain growth of 0.75 μm in length could be artificially grown via the super lateral growth phenomenon using excimer laser irradiation with the plateau structure. Consequently, bottom-gate TFTs made by this method exhibit higher field-effect-mobility, lower leakage current, steeper subthreshold slope, larger on/off current ratios and improved device uniformity owing to this location-manipulated lateral grains. In addition, it shows better reliability because of the smooth interface between gate dielectric and poly-Si channel films.

Improved electrical stability in asymmetric fingered polysilicon thin film transistors

The authors studied the electrical stability of the asymmetric fingered polysilicon thin film transistors (AF-TFTs) at different bias-stress conditions by using a new test structure with an additional contact on the n+-floating region. This structure allows to measure the two subchannel TFT (sub-TFT) electrical characteristics before and after bias stressing. The AF-TFTs show a very stable saturation regime, even when bias stressing at very high Vds, where the electrical characteristics of both sub-TFTs are degraded. The authors concluded that stability of the AF-TFTs is related to the specific operation of the device rather than to immunity of this structure to hot carrier effects.

Determination of interface state distribution in polysilicon thin film transistors from low-frequency noise measurements: Application to analysis of electrical properties

Low-frequency noise is studied in n-channel furnace solid phase crystallized and in laser solid phase crystallized (LSPC) polysilicon TFTs biased from weak to strong inversion. Noise analysis is supported by theoretical results of the additivity of generation-recombination spectra to explain trapping/detrapping processes following the tunneling theory of carriers into the gate oxide. In the weak inversion region the normalized drain current spectral density is inversely proportional to the number of trapped carriers. The corresponding distribution of the trap states [density of states (DOS)] in the polysilicon band gap at the interface is determined. In the strong inversion region the normalized drain current spectral density is proportional to the effective oxide trap number/(freecarriernumber)2 ratio. For LSPC devices the DOS is one decade lower and the corresponding effective oxide trap number is one decade higher. The results are attributed to the effects of the laser annealing on the active layer crystal quality. Quantitative dependence of DOS with static conduction parameters in relation with interface quality is then analyzed.

DIRECT FORMATION OF NANOPORE ARRAY VIA FOCUSED ION BEAM FINE MILLING AND SURFACE COATING TECHNIQUES

A nanopore array with diameter of ~30 nm was fabricated by use of focused ion beam (FIB) scanning and thin film coating on Si (100). A thin film of SiO 2 with thickness of 200 nm (used as a sacrificial layer) was coated by physical evaporation deposition (PVD) first. Next, the thin films of poly-silicon with thickness of 50 nm were coated on double side of the substrate. A window with an area of 2 × 2 mm 2 was opened by reactive ion etching from bottom side and reached to the thin film of SiO 2. After that, a fine controlled FIB milling with bitmap function (milling according to a designed pattern in a defined area) was used to scan the area. Signal is obtained by a sensor inside the vacuum chamber collecting secondary electrons emitted from the sputtered material when the beam reach the layer of SiO 2. Stopping the milling process at this moment, the nanopore array was derived after removing the sacrificial layer by wet chemical etching. The nanopore arrays were characterized using transmission electron microscopy (TEM) after the FIB drilling.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

Large-grained poly-silicon thin films by aluminium-induced crystallisation of microcrystalline silicon

Al-induced crystallisation of microcrystalline Si (μc-Si:H) thin films prepared by electron cyclotron resonance plasma-enhanced chemical vapour deposition (ECR-PECVD) on SiO 2-coated Si wafers has been studied. The starting structure was substrate/μc-Si:H/Al. Annealing this structure at a temperature of 520 °C resulted in successful layer exchange and the formation of a substrate/Al+Si layer/poly-Si geometry. Grain sizes exceeding ∼60 μm have been achieved in films displaying a preferential (1 0 0) orientation. The length of time the samples are kept under ambient conditions before annealing plays a key role in controlling grain size and orientation. It is likely that this time delay influences the formation of the interface between the Si and Al layers and, hence, the crystallisation process. These poly-Si layers exhibit an average surface roughness ( R a) generally in the range ∼7–12 nm.

High-Performance Low Temperature Poly-Silicon Thin Film Transistors Fabricated by Excimer Laser Irradiation with Bottom-Gate Structure

not Available.

Poly-silicon thin films by aluminium induced crystallisation of microcrystalline silicon

Al-induced crystallisation of microcrystalline Si thin films prepared by electron cyclotron resonance plasma-enhanced chemical vapour deposition (ECR–PECVD) on glass and SiO 2 coated Si wafers has been studied. The starting structure was substrate/μc-Si/Al. Annealing this structure in the temperature range 370–520 °C, immediately following deposition of the Al layer, resulted in successful layer exchange and the formation of a substrate/Al+Si layer/poly-Si geometry. The top poly-Si layer exhibited grain sizes generally in the range ∼2–6 μm, although larger grains were also sparsely present. The films did not exhibit any appreciable degree of preferred orientation. The surface roughness was relatively high with a R a value of ∼20 nm.

Polysilicon TFT circuits on flexible stainless steel foils

This paper presents a study on several polysilicon TFT circuits that may be used for highly integrated electronic systems on flexible metal foils. The circuit performance presented here validates the polysilicon TFT metal foil technology as a suitable platform for the incorporation of control, processing and communication circuits onto a flexible system. This research addresses digital, analog and mixed signal polysilicon thin film transistor (TFT) circuits exploiting metal foil device assets, while complying with design and fabrication parameters of flexible substrates. This paper reports some of the highest electron mobilities recorded to date on TFTs fabricated on metal foils (over 300 cm 2/V s) and presents data on high performance circuits including: shift registers running at speeds over 10 MHz, ring oscillators with stage frequency response over 1 GHz and mixed signal circuits for row and column display driving. This is one of the most comprehensive reports to date on general purpose circuits on stainless steel foils.

Out of Plane Flexural Behaviour of Thin Polysilicon Films: Mechanical Characterization and Application of the Weibull Approach

Out of Plane Flexural Behaviour of Thin Polysilicon Films: Mechanical Characterization and Application of the Weibull Approach

Sensing sensibility of surface micromachined suspended gate polysilicon thin film transistors

Suspended gate thin film transistors (SGTFT) used as gas sensor are fabricated using surface micromachining process. The suspended gate is a polycrystalline silicon micro-bridge and the process is fully compatible with both IC technology and low-cost glass substrates. Detection of gas is linked to the concentration of electrical charges located in air-gap, region between the gate and the channel of the transistor. Field effect, due to the voltage applied to the suspended gate, is enough to influence the distribution of electrical charges present in ambience, and then, the transistor electrical characteristics. Results concerning the response of polysilicon SGTFT to NH 3 and NO 2 detection are presented. The high sensitivity is attributed to the influence of the very high field in the narrow (0.5 μm) gap on the charge distribution in the gap as well as the surface adsorption. Behaviour of the sensor is explained by a model based on electrical charges distribution in air-gap versus gate voltage.

A simple method for measuring the thermal diffusivity of surface-micromachined polysilicon thin films

A method to test the thermal diffusivity of surface-micromachined polysilicon thin films is proposed. It is composed of two polysilicon microbeams with the same width and thickness but different lengths. The thermal diffusivity is extracted from the thermal time dependence of the resistance for the two polysilicon microbeams cooling in free air. The effects of all heat exchange by convection, radiation and heat transfer through the air gap and into substrates are considered in the electrothermal model of the polysilicon microbeam. All measurements can be carried out in free air, and only the four-probe arrangement and digital oscilloscope are needed in experiments. The thermal diffusivity obtained using this method is 0.165 cm2 s−1. The proposed method is suitable for on-line measurement of the thermal diffusivity for surface-micromachined polysilicon thin films.

An online test microstructure for thermal conductivity of surface-micromachined polysilicon thin films

An online test structure for measuring the thermal conductivity of surface micromachined polysilicon thin films is presented. In the structure, a pair of microstructures, i.e., a reference structure and a test structure, are used. The surface micromachined structures are heated electrically. Heat dissipation by convection, radiation, and heat transfer through the air gap and into the substrate is considered in an electrothermal model. The model is confirmed by ANSYS Software. In experiments, current-voltage measurements are only required, and all measurements can be carried out in free air. The surface-micromachined and p-doped polysilicon thin films with a sheet resistance 116.25 /spl Omega//sq. are measured to have a thermal conductivity 28.7 W/mK at 300 K.

Annealing temperature effects on the electrical characteristics of p-channel polysilicon thin film transistors

In this work, we studied the effects of different thermal annealing on the electrical characteristics of non-self-aligned low-temperature p-channel polycrystalline silicon (polysilicon) thin film transistors. Different thermal treatments were performed after Al-gate formation at different temperature (200°C, 250°C, 350°C and 450°C) and annealing times. We found that optimal conditions were obtained at 350°C, with transfer characteristics showing a subthreshold slope of 0.5V/dec, field effect mobility >100cm2/Vs and threshold voltage around −3.5V. Hot carrier induced degradation was also analyzed performing bias-stress measurements on devices annealed at 350°C and at different bias stress conditions. The experimental data show that a maximum transconductance degradation is obtained for Vg(stress)−Vt=−4V while bias-stress at Vg=Vt and ∣Vg(stress)∣≫∣Vds(stress)∣ did not produce appreciable changes in both transfer and output characteristics.

Study of the hydrogenation mechanism by rapid thermal anneal of SiN:H in thin-film polycrystalline-silicon solar cells

A considerable cost reduction in photovoltaics could be achieved if efficient solar cells could be made from thin polycrystalline-silicon (pc-Si) films. Although hydrogen passivation of pc-Si films is crucial to obtain good solar cells, the exact mechanism of hydrogen diffusion through pc-Si layers is not yet understood. In this letter, the influence of the junction and the grain size are investigated. We find that the presence of a p-n junction acts as a barrier for hydrogen diffusion in thin-film polysilicon solar cells. Therefore, pc-Si solar cells should preferably be passivated before junction formation. Furthermore, pc-Si layers with large grains retain less hydrogen after passivation than layers with small grains. This indicates that hydrogen atoms get mainly trapped at the grain boundaries.

Formation of (111) nanotwin lamellae hillocks in polycrystalline silicon thin films caused by deposition of silicon dioxide layer

Plasma-enhanced chemical vapor deposition was used to deposit layers of tetraethylorthosilicate at different temperatures. In the case of low-temperature deposition (300°C), the deposited film surface was smooth and the major surface defects of the polycrystalline silicon (poly-silicon) film surface were grooves of grain boundaries. In contrast, in the case of high-temperature deposition (500°C), the deposited silicon oxide surface exhibited hillocks, and these hillocks were derived from the top end of inclined silicon (111) where protruding nanotwin lamellae penetrated the poly-silicon thin film. The observed hillocks stemming from nanotwin lamellae could have been formed by compressive stress during high-temperature silicon dioxide deposition.

オンチップ電気化学プロセスのための微小電極パターンのマイクロマシニング

In order to implement electrochemical processes (e.g., detection or synthesis) on a chip-based system, micromachining techniques for a glass microchip with fully integrated electrodes have been developed. Pt/Ti microelectrodes were successfully patterned on the curved surface of a glass microchannel, which was etched in a HF solution using polysilicon thin film as an etch mask, by means of a lift-off method using a positive thick photoresist. In this process, the photoresist must be exposed with a single wavelength (g line) selected from a high-pressure mercury lamp in order to obtain its microstructure with excellent edge quality and vertical sidewalls. In addition, although fusion bonding cannot be used for microchips with lead patterns in the interface between a pair of glass substrates, a glass cover plate can be bonded to a glass substrate with lead patterns embedded in the space formed on its surface by buffered HF (BHF) etching. The resulting bonded area ratio was estimated to be approximately the same as that for glass-to-glass bonding.

P-135: Fast Bend Transition of the Pi-Cell at Low Temperature

We have developed fast bend transition method of pi-cell in low temperature. This cell requires a transition of the liquid crystals (LC) from an initial splay state to bend transition before normal driving operation. This study analyzed the conditions under which this transition is generated in low temperature. Consequently, a method of fast bend transition by applying waveform that make the most of LC's dynamic response, using structure of top-gate electrode and surface alignment in Low Temperature Poly-Silicon (LTPS) Thin Film Transistor (TFT) cell was established.