Plastic Encapsulation Research Articles

Device Failures in Pressure Cooker Tests at 130°C

AbstractThe results obtained from Moisture-Temperature-Bias testing of Power- MOSFET at 130°C and 85%RH are examined. A variety of packaging techniques were tested varying from plastic encapsulation materials/methods to fully hermetic. Unprotected devices were tested as controls. The predominant failure mechanism observed was aluminum corrosion, which was manifested initially as a leakage current increase and eventually as visually observable dissolution of aluminum and eventual open circuits.This paper examines the critical part that surface contamination plays in the corrosion process, particularly where condensed water films can form at the metal surface. The effectiveness of various plastic coating methods are viewed in the light of this concept. Aluminum lead bonds were more susceptable to corrosion than expected. A number of materials were identified that showed resistance to pressure cooker conditions.

Stress-Induced Deformation of Aluminum Metallization in Plastic Molded Semiconductor Devices

Plastic encapsulation of large semiconductor chips has resulted in increased stress-related failures such as cracked passivation, metal deformation and delamination, cracked chips, cracked packages, and parameter shifts. The large mismatch in the coefficient of thermal expansion between the silicon chip and the plastic encapsulant is felt to be the major contributor to these failures. In an effort to minimize stress problems, many mold compound manufacturers have modified their formulations and epoxy resin chemistries. As a result, many "low-stress" mold compounds have been introduced in recent years. A procedure was developed for screening encapsulation plastics for mechanical stress on semiconductor chips. The method involves temperature cycling of molded packages containing unpassivated test chips. The degree of deformation of the metallization is used as a measure of stress on the chip. Several semiconductor grade epoxy mold compounds were evaluated with this procedure. Many of the newer low-stress epoxy formulations gave metal deformation equal to or greater than the standard formulations. One of the materials, however, yielded no observable metal deformation under the test conditions. Metal deformation is a result of shear stress acting at the chip surface, with the direction of the deformation being toward the center of the chip. Microscopic cross-sectional analysis of temperature cycled packages revealed microcracks in the plastic which appeared to have initiated at the chip edge. In most cases, the cracks were about 400/ <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\mu</tex> m long and thus did not reach the package surface. The microcracks appear to promote metal deformation, since they reduce the restrictions on plastic movement at the chip surface. SEM analysis was employed to determine the topography of the deformed aluminum stripes. The effects of chip size, aluminum line width, number of temperature cycles, and post-cure conditions were also determined.

EPIC, a Cost-Effective Plastic Chip Carrier for VLSI Packaging

With the continuing growth in complexity of very large-scale integrated (VLSI) chips, there are increasing demands for high-performance high-pin-count micropackages capable of providing high reliability protection of the chips without being unduly costly. Studies have confirmed that plastic encapsulants, particularly silicones, can provide very high reliability protection indeed. These observations led to the concept of a new plastic chip carrier, named the "EPIC," fabricated by printed circuit board technologies, which has been developed to be suitable for automated bonding and encapsulation of chips into the package, and for subsequent automated surface-mounted assembly of the EPIC onto circuit boards. Reliability evaluations of the EPIC, in comparison with established commercial small outline (SO) plastic micropackages, have demonstrated that high reliability is attainable with EPIC chip carriers and also SO packages from a few sources. Performance measurements have revealed the outstandingly better electrical performance of the EPIC over ceramic equivalents, and versions of EPIC can achieve equivalent or better thermal resistances. Cost analyses show that the EPIC starts with an intrinsically low cost and can achieve very high terminal counts (exceeding 200) while maintaining the cost advantage. Thus high performance and reliability of VLS1 packaging is achievable cost-effectively.

The Plastic Composite Package Provides an Economic Alternative To LSI‐VLSI Packaging for High Density Microcircuits

The increase in semiconductor integration level has led to complex Integrated Circuits (ICs) characterised by an increasing number of I/O, such that dies with 40 to 84 metallised pads are currently manufactured and frequently used in modern electronic systems. The advent from 1980 onwards of these LSI‐VLSI semiconductors requires new economical micropackages to be devised that can be adapted to surface mounting techniques on Hybrid Integrated Circuits (HICs) and Printed Circuits Boards (PCBs). Plastic encapsulation using a transfer moulded epoxy resin is a widely used method for packaging silicon devices because of the reduced manufacturing cost for large volumes. This economic criterion, which is considered with widespread interest in the electronics industry, has recently led the major semiconductor manufacturers to produce Plastic Leaded Chip Carriers (PLCCs) with up to 84 J bend connections on 1·27 mm pitch, and Mini Quad Packs with 40 to 84 Z bend pins on 0·75∼0·80mm centres. However, until now, a significant number of ICs, such as full custom circuits, are not yet available in any packaged form. Thus, in order to take advantage of the compactness offered by micropackages without being under component manufacturers' constraints for packaged LSI needs, it was decided at the Microelectronics Division of CIT‐Alcatel to develop a flexible semiconductor encapsulation technology which does not require any moulding equipment. The process involved has led to the development of a small economical package with 52 peripheral Z bend leads on 0·75 mm centres which has been evaluated. This original LSI carrier, named Plastic Composite Package (PCP) because of its special feature, is perfectly suited to the specific needs of multilayer HICs for all non‐military applications. In addition, another PCP format with 68 pins on 0·635 mm centres, designed for LSI Industrial applications, has been investigated. The purpose of this paper is to explain the specific needs in the hybrid industry and to give the authors' views on trends in LSI‐VLSI plastic encapsulation. Moreover, the PCP manufacturing process is described, the evaluation results being discussed as well as the economic aspect.

The Influence of Plastic Encapsulation, Overglaze, and Voltage on Anomalous Behavior of Thick-Film Resistors

Eariier detailed studies of the aging mechanisms of thickfilm resistors revealed anomalous behavior in which certain resistors appeared to be sensitive to the voltages applied to them, but only when they were plastic-encapsulated and not overglazed. These anomalies have been deliberately provoked in a further special study, reported here, of the influence of encapsulation and the effectiveness of overglazing in safeguarding the long-term stability of thick-film resistors. In this paper ruthenium-based thick-film resistors ranging in value from ohms to megohms were finished in a variety of different ways, such as with and without overglaze, with and without laser trim, and with and without plastic encapsulation, and subjected to damp heat and thermal overstress with and without electrical bias. The plastic encapsulaut employed was a particularly active one selected for its properties of nonneutral pH and high ionic content, which are usually regarded as undesirable for electronic component encapsulation but are useful in this instance to exaggerate the effects to be studied.

VLSI Packaging

The ever greater complexity of VLSI devices is resulting in increases in pin count, power dissipation, and chip area. Furthermore, the increase in speed because of the smaller feature sizes leads to more stringent electrical requirements on the packaging. For high reliability under adverse ambient conditions, hermetic sealing is mandatory. However, for less severe requirements, plastic encapsulation is proving a cost‐effective alternative. It is expected that improvements in plastic materials and in chip surface passivation will further enhance the reliability of plastic‐packaged VLSI devices. Packaging materials and processes, as well as packaged shapes, will have to be modified to cope with the demands of future VLSI devices.

The Manufacture and Reliability of the EPIC Chip Carrier

Following extensive studies that demonstrated that some types of plastic encapsulation can be used in high reliability environments, the EPIC chip carrier was conceived and developed as a cost‐effective micropackage for ICs. The EPIC chip carrier is manufactured by adaptations of PCB techniques with metallisation suitable for auto‐wire bonding. It is a low‐cost alternative to the ceramic chip carrier, but with a much better electrical performance, derived from lower parasitics of the materials employed. Reliability studies have confirmed the suitability of the EPIC for 20 year life operations to which an added benefit is the avoidance of TCE mismatch problems sometimes obtained with ceramic chip carriers on PCBs.

A new reliability evaluation method based on using the parasitic MOS formation phenomenon

AbstractOne of the instabilities in plastic‐encapsulated MOS LSI is due to leakage caused by parasitic MOS formation. This paper uses this parasitic MOS leakage phenomenon to evaluate the surface reliability of new MOS. In this investigation the center of the gate electrode is omitted, and an MOS transistor with a partial gate structure is fabricated; plastic encapsulations are used, and the source‐drain leakage current variation with time is investigated with a voltage applied between source and drain. The results are shown to be different with different plastic encapsulation. The maximum leakage current increase rate is denoted by α. The parameter α is temperature‐dependent and a linear relationship exists between the logarithm of α and the reciprocal of the absolute temperature T. The activation energy is found to be 1.1∼1.4 eV. The theoretical formula of the physical meaning of α shows that α is proportional to the diffusion constant of the parasitic MOS formation, and the correctness of the new evaluation method using α is confirmed. Our method has good repeatability. In addition, it permits an easier and, because of high sensitivity, a faster evaluation than the conventional method using variations of the threshold voltage VT.

Corrosion Test for Metallization for Plastic‐Encapsulated IC's

With the use of plastic encapsulation for semiconductor devices, the prevention of metallization corrosion has become one of the most important problems to be solved. A method for the evaluation of metallization materials has been devised so as to be able to predict the performance of the plastic‐encapsulated devices in temperature‐humidity‐bias test with the acceleration of the order of 103 times. This method has been used to find an Al‐Mn metallization which is more corrosion resistant than that using pure Al.

Water vaper penetration rate into enclosures with known air leak rates : Aaron DerMarderosian and Vincent Gionet. Proc. IEEE Reliab. Phys. Symp., San Diego (18–20 April 1978), p. 179

Plastic encapsulation is now a highly reliable method of packaging microelectronics and can be significantly more reliable than military specified “hermetic components” in field deployments of electronics in humid tropical climates. MIL883 hermeticity is an inadequate safeguard against penetration by high levels of moisture in the atmosphere. In this new work, tropical climates are analysed and shown to be significantly more severe than those safeguarded by current MIL883 standards. Field failure returns have revealed that MIL 883 hermetic CerDIP (ceramic dual-in-line) packaged ICs installed in digital switching systems failed catastrophically with a failure rate of 1755 FITs. The cause of failure was severe ingress of moisture, resulting in dewpoints up to 30°C. Alternative indigenous developments of modular digital switches for widespread rural use in India have incorporated plastic encapsulated components selected according to the criteria developed from earlier extensive and successful reliability work by British Telecommunications (BT). Such criteria include the use of HAST (highly accelerated stress technique, invented at BT Labs). The BT Labs pioneering work demonstrated that commercial transfer-moulded epoxy packaged devices from certain sources were more reliable than their hermetic counterparts.Evidence from other published pioneering work has confirmed that plastic packaging now endures as a high reliability method of packaging microelectronics. Such pioneering work is also reviewed in this paper. In the USA, the IEEE Gel Task Force followed the earlier BT Laboratories initiative and concluded that silicone gels are indeed suitable for high reliability applications. AT&T undertook comprehensive materials analyses to show that silicone gels possess remarkably useful properties to safeguard high reliability integrated circuits. CALCE, University of Maryland, conducted studies of simple logic circuits and showed that the achieved reliability in temperature climatic conditions is three times greater than that predicted for military parts. BT Labs continued its work and extended its applicability to optoelectronics. Analyses of MCM applications for satellites by the author also show that plastics are a preferred option. The evidence is that plastic encapsulation is now a very reliable and cost-effective option.

A comparison of the performance of plastic and ceramic encapsulations based on evaluation of CMOS integrated circuits

A comparison of the performance of plastic and ceramic encapsulations based on evaluation of CMOS integrated circuits

Factors contributing to the corrosion of the aluminum metal on semiconductor devices packaged in plastics

Using a test structure with an evaporated aluminum metallization pattern on the surface of a phosphorus “doped” oxide layer of a silicon semiconductor chip, the rate of corrosion of the aluminum metallization in a d.c. electric field at 85°C and 85% relative humidity was studied. The test structure was attached to a metal frame and molded in a variety of epoxy and silicone plastics. The relative contribution of the nature of the plastic encapsulant used, the presence of phosphorus in the silicon oxide layer and the strength of the electric field on the corrosion of the aluminum metallization was investigated. Under the above conditions it was established that in the presence of phosphoric acid extracted from the phosphorus-doped oxide layer corrosion occurs exclusively at the cathode. The rate is dependent upon the applied d.c. voltage. In the absence of phosphorus in the oxide layer and other ionic contaminants in the moisture on the surface of the device (pH 6–8) the rate of aluminum corrosion is low and occurs principally at the anode. The type of plastic encapsulant used influences the rate of moisture penetration to the device surface but once there the rate of corrosion under high temperature and bias is similar for all plastics if the acidity of the surface layer is high. It is shown that moisture penetration is diffusion-controlled and does not correlate with adhesion of the plastic to the external leads. On the basis of observations of the conditions favoring cathodic or anodic corrosion of the aluminum on semiconductor devices together with aluminum electrodes in various electrolytes, the electrochemical and chemical reactions occurring at the electrodes between the aluminum and the electrolytes are postulated.

Designing Reliablity into Solid-state Consumer Systems

The increased demand for semiconductors in the consumer market place has accelerated the need for improved product reliability. This need has been well recognized by the manufacturer and consumer. Often the consumer quality and reliability demands are tougher than required for military products --understandably so, when you consider the staggering cost of rework on line rejects, the repair of field failures (especially when warranties are involved), and the possibility of a bad reputation. Even though the price competition within the semiconductor industry has intensified, the manufacturer has to meet this challenge with good designed-in reliability and rigid process control. In addition, if a plastic encapsulant is used, it needs to exhibit a reliability approaching that of hermetic devices. Ultimately, the consumer can add to his system reliability by understanding the physical and electrical limitations of semiconductors, and recognizing the definite reliability improvements that can be achieved by integrating circuitry whenever possible.

Reliability problems related to plastic encapsulation of integrated circuits : G. Andre and J. Regnault. Onde Elec.52, No. 3, March (1972), p. 121. (In French.)

Reliability problems related to plastic encapsulation of integrated circuits : G. Andre and J. Regnault. Onde Elec.52, No. 3, March (1972), p. 121. (In French.)

The water vapour permeability of the plastic encapsulation of implantable cardiac pacemakers and its effects.

The plastic encapsulation of implantable cardiac pacemakers is permeable to water vapour, with a resultant degradation of reliability and longevity. The physics involved are discussed and the effects described. A solution is proposed.

Optimization of Electroluminescent Efficiencies for Vapor‐Grown GaAs1 − x P x Diodes

A series of diodes have been prepared by a vapor‐phase growth technique to investigate the effects of current‐spreading, absorption, impurity concentrations, and alloy composition on room‐temperature electro‐luminescent efficiencies. It is shown that for maximum efficiencies, a diode structure should be prepared with a p+ surface layer to enhance current spreading, and a “window” containing about 10% more than the p‐n junction region to reduce absorption losses. It is also shown that the most efficient radiative recombination originates on the p‐side of the junction; low acceptor concentrations and high donor concentrations which are required for strong electron injection into the p‐side of the junction are thus found to result in highest electroluminescent efficiencies. Slow compositional grading between the substrate and the p‐n junction also resulted in increased efficiencies. A drop‐off in efficiency near the direct‐indirect transition for values of increasing from 0.38 was found to be severe, however, a corresponding increase in the spectral sensitivity of the eye was found to provide a broad maximum in diode brightness at emission wave‐lengths near 6800Aå (). Planar uncoated diodes have provided brightness values in excess of 300 ft‐L at 10 amp/cm2 with external efficiencies of at 6400Aå. Plastic encapsulants ean be readily used as domes to increase external efficiencies by a factor of 3, or as directional lenses to provide beam‐widths as narrow as 7°.

Thermal Considerations for Plastic Encapsulation or Coating in Electronic Product Design

The effects ofusing plastic compounds for encapsulation or coating of electronic circuitry are discussed with respect to cooling. The basic thermal mechanisms are presented. It is concluded that encapsulation or coating can significantly improve the cooling of small compact circuitry not employing direct metallic conduction paths or direct forced convection.

Thermal Considerations for Plastic Encapsulation or Coating in Electronic Product Design

Thermal Considerations for Plastic Encapsulation or Coating in Electronic Product Design

Fabrication of Microminiaturized Core Memories by Plastic Encapsulation Techniques

Plastic encapsulation of nonlinear ferrites, and the effect of this encapsulation on the magnetic characteristics of the ferrites, is discussed in this paper. This technique provides greater immunity to shock and vibration damage than conventional core frames and provides bit densities in excess of one million per cubic foot. Chemical deposition and photographic techniques may be used to form a portion of the wiring matrix. Through-hole plating of ferrites having a 15-mil diameter hole is possible. Small-evaluation memories have been fabricated, using both toroids and transfluxors. Temperature tests on these memories show that encapsulation causes a slight increase in switching speed and a small decrease on output for a given drive current. These changes remain almost constant over the temperature range. No significant changes have been noted in the noise output. Techniques outlined are presently being used in the fabrication of microminiaturized, nondestructive memories for missile and satellite application.