Plasma Charging Damage Research Articles

Plasma-Charging Damage of Floating MIM Capacitors

In this paper, the mechanism of plasma-charging damage (PCD) of metal-insulator-metal (MIM) capacitors as well as possible protection schemes are discussed. A range of test structures with different antennas simulating interconnect layout variations have been used to investigate the mechanism of PCD of MIM capacitors. Based on the experimental results, two models are presented, describing the relation between the damage and the ratio of the area of the exposed antennas connected to the MIM capacitors plates. New design rules are proposed in order to predict and automatically flag possible PCD sites. Furthermore, layout solutions to reduce PCD are suggested.

Failure Analysis for High via Resistance by HDP CVD System for IMD Layer

As the application of semiconductor chips into electronics increases, it requires more complete integration, which results in higher performance. And it needs minimization in device design for cost saving of manufacture. Therefore oxide gap fill has become one of the major issues in sub-micron devices. Currently HDP (High-Density Plasma) CVD system is widely used in IMD (Inter Metal Dielectric) to fill narrower space between metal lines. However, HDP-CVD system has some potential problems such as plasma charging damage, metal damage and etc. Therefore, we will introduce about one of via resistance failure by metal damage and a preventive method in this paper.

Plasma charging defect characterization, inspection, and monitors in poly-buffered STI

In this paper, the mechanism, inspection, and inline monitor of plasma charging defects found in an active area (AA) corner and edge using a poly-buffer (PB) STI process is reported. These defects are formed by the arcing (or discharging) through weak spots of pad-oxide between the poly-buffer layer and substrate as resulting from the charging of poly buffer layer during reverse-AA oxide etching. Such defect formation is found to be strongly enhanced by the magnetic field used in oxide etchers but not related to etch rate and plasma density. The defect inspection on patterned wafers is found to be strongly correlated to the flat-band voltage (V/sub fb/) and to a lesser extent to oxide charge (Q/sub tot/) degradation on in-line unpatterned oxide wafers. Therefore, the shift of V/sub tb/ and Q/sub tot/ on unpatterned wafers can be effective inline monitors for plasma charging damage during reverse-AA etching in PB-STI process.

Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si/sub 3/N/sub 4/ and Ta/sub 2/O/sub 5/ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si/sub 3/N/sub 4/ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta/sub 2/O/sub 5/ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta/sub 2/O/sub 5/ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta/sub 2/O/sub 5/ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation.

The impact of plasma-charging damage on the RF performance of deep-submicron MOSFET

Integration of RF analog functions with CMOS digital circuits offers great advantages in terms of cost and performance. Plasma-charging damage is known to degrade MOSFET characteristics and can be expected to impact the RF performance as well. In this work, we present for the first time a thorough investigation of the impact of plasma-charging damage on the RF characteristics of deep-submicron MOSFET. Our result shows that, with ultra-thin gate oxide, a 400/spl deg/C forming gas annealing can completely recover the RF performance degradation due to plasma-charging damage.

Effect of reverse biased voltage at source and drain on plasma damage

We have examined the possible effects of reverse-biased floating potential at the source and drain during plasma processing on the performance of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Threshold voltage degradation was evaluated by subjecting the gate oxide to high-field injection. Device degradation is found to be enhanced with the floating potential at source and drain for the devices subjected to substrate injection. An increase in electron trapping was observed with an increase in floating potential. Estimation shows that the effective antenna ratio of MOSFET increases with the reverse-biased floating voltage at source and drain. Our results indicate that plasma-charging damage can be significant even under uniform plasma if a potential is developed at the antenna-connected source and drain terminals. Damage in devices subjected to gate injection on the other hand, could have minimal dependence on source and drain potential.

Enhanced Negative-Bias-Temperature Instability of P-Channel Metal-Oxide-Semiconductor Transistors due to Plasma Charging Damage

The effects of plasma charging on the negative-bias-temperature instability (NBTI) of p-channel metal-oxide-semiconductor (PMOS) transistors were explored in this work. It is clearly shown that the threshold voltage shift during bias-temperature stressing (BTS) could be enhanced by plasma charging damage. More importantly, we also found that electron trappings are aggravated by plasma charging, even on new devices with large antenna area ratios prior to BTS. Our charge pumping current measurements confirm that the interface-state density is increased for devices with large antennas, both before and after the BTS. This indicates, without ambiguity, that electron trapping is solely responsible for the observed low (in absolute value) threshold voltage in new devices with large antennas. Finally, it is proposed that the NBTI characterization can be used as a sensitive method for characterizing the antenna effects in devices with ultrathin gate oxide, which is particularly attractive in light of the fact that conventional indicators are becoming inadequate as oxide is scaled down.

Plasma charging damage on MOS devices with gate insulator of high-dielectric constant material

Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si/sub 3/N/sub 4/ film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta/sub 2/O/sub 5/ samples. For devices with Ta/sub 2/O/sub 5/ film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application.

Plasma charging damage mechanisms and impact on new technologies

Plasma charging damage is a serious concern in fab today. In this topic will be discussed mechanisms through which charging damage arises, how to characterize them, and how to minimize them at the different phases of circuit fabrication. The relation between oxide thickness and damage will be discussed highlighting the importance of characterization methods and reliability physics. Importance of charging damage on new technologies as copper and SOI will be discussed.

Gate-induced drain leakage current enhanced by plasma charging damage

Correlation between gate-induced drain leakage (GIDL) current I/sub GIDL/ and plasma charging damage is investigated for p-MOSFETs. I/sub GIDL/ and maximum charge pumping current show the same trend as a function of antenna area ratio (AAR) and cell location. Enhancement of I/sub GIDL/ is mainly attributed to the increase of Si/SiO/sub 2/ interface traps generated in the plasma processes and is not related to the small amount of trapped charge in the oxide.

Plasma-charging damage in ultra-thin gate oxide

The impact of plasma-charging damage on ultra-thin gate oxide is discussed. The argument for plasma-charging damage becoming less important is examined. Without considering the area and failure rate scaling effect, one mode of charging damage does become less important while other modes continue to be a serious problem. After scaling is properly accounted for, all charging damage remains a serious problem. The problem is more serious for thinner gate oxides because its life time becomes a limiting factor in device scaling. No one has yet made proper measurement for charging damage in the ultra-thin gate oxide regime. Stress-induced leakage current with properly designed tester may be used for ultra-thin gate-oxide damage measurement if one has the required sensitivity in the measurement. However, one must take care to use stress to reveal the latent defects that are hidden by annealing.

Plasma charging damage during contact hole etch in high-density plasma etcher

Plasma process induced damage from high-density plasma dielectric etcher was studied comprehensively. It was observed that PMOS devices were damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect the permanent damages. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler–Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at the conductor etch, although no electron shading effect was observed. Thus, plasma damage during contact or via hole etch in high-density plasma system must be considered carefully.

Plasma charging damage and ESD, help each other?

ESD and plasma charging damage are different modes of electrical stress that degrade integrated circuits. They are quite different and yet share many similarities. As integrated circuit technology continue to progress, both face the challenge of how to protect the ultra-thin gate-oxide. This paper discusses the common problem shared by both communities.

Plasma-induced charging damage in ultrathin (3-nm) gate oxides

Plasma-induced damage in various 3-nm-thick gate oxides (i.e., pure oxides and N/sub 2/O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Both charge-to-breakdown and gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as the wafer edge for pMOS devices, while only at the wafer center for nMOS devices. These interesting observations could be explained by the strong polarity dependence of ultra thin oxides in charge-to-breakdown measurements of nMOS devices. In addition, pMOS devices were found to be more susceptible to charging damage, which can be attributed to the intrinsic polarity dependence in tunneling current between nand p-MOSFETs. More importantly, our experimental results demonstrated that stress-induced leakage current (SILC) caused by plasma damage can be significantly suppressed in N/sub 2/O-nitrided oxides, compared to pure oxides, especially for pMOS devices. Finally, nitrided oxides were also found to be more robust when subjected to high temperature stressing. Therefore, nitrided oxides appear to be very promising for reducing plasma charging damage in future ULSI technologies employing ultrathin gate oxides.

Influence of Gate Oxide Quality on Plasma Process-Induced Charging Damage in Ultra Thin Gate Oxide

The correlation between the gate oxide quality and the plasma process-induced charging damage is studied for metal-oxide-semiconductor (MOS) devices with gate oxide thickness of 1.9–3 nm. It is found that plasma charging damage of ultra thin oxide strongly depends on its initial oxide quality. The ultra thin oxide of around 2 nm thick is not always free from plasma charging damage, if the fabrication process other than the plasma process is not optimized. A mechanism of the enhanced plasma charging damage due to gate electrode formation process is proposed. If defects exist in the oxide, these defects become weak paths for the injected current during the plasma process. Thus, current density at the defects becomes high and oxide breakdown occurs even when the oxide is as thin as 2 nm, in which current conduction by direct tunneling dominates.

Dependence of the performance and reliability of n-metal-oxide-silicon field effect transistors on interlayer dielectric processing

This article reports on the impact of interlayer dielectric (ILD) deposition and processing on the characteristics and reliability of n-channel metal-oxide-silicon field-effect transistors (n-MOSFETs). The ILD materials used were silicon dioxide prepared from tetra-ethyl-ortho-silane, fluorinated silicon oxides (FSOs), and low-k polymers. The ILDs were deposited by means of plasma enhanced chemical vapor deposition (PECVD), PECVD and high density plasma (HDP), and spin coating, respectively. The devices with 90 Å gate oxide and 0.35 μm channel lengths were sensitive to poly-Si gate definition etching steps with antenna ratio 5 and 70 K. To assess the degree of degradation, charge pumping (CP), gate-oxide integrity as well as transistor’s parameters were measured after Fowler–Norheim (FN) stressing. It is found out that PECVD deposition of FSO resulted in the highest degradation to the MOSFETs, whereas spinning-on and processing polymer ILD yielded the best performing and the most reliable MOSFETs. It is also found that device degradation in wafers with FSO as ILD depends on the deposition method of FSO, and that this degradation bears a reverse charging-antenna correlation. It is argued that this correlation is caused by the interaction between fluorine and plasma-charging damage.

Nondestructive DCIV method to evaluate plasma charging damage in ultrathin gate oxides

Understanding and minimizing plasma charging damage to ultrathin gate oxides became a growing concern during the fabrication of deep submicron MOS devices. Reliable detecting techniques are essential to understand its impact on device reliability. As the gate oxide thickness of MOSTs rapidly scales down, the conventional nondestructive methods such as capacitor C-V and threshold voltage and subthreshold swing of MOSTs are no longer effective for evaluating this damage in gate oxide. In this paper, the newly developed direct-current current-voltage (DCIV) technique is reported as an effective monitor for plasma charging damage in ultrathin oxide. The DCIV measurements for p-MOSTs with both 50- and 37-/spl Aring/ gate oxides clearly show the plasma charging damage region on the wafers and are consistent with the results of charge-to-breakdown measurements. In comparing with charge-to-breakdown measurement and other conventional methods, the DCIV technique hits the advantages of nondestructiveness, high sensitivity and rapid evaluation.

The prospect of process-induced charging damage in future thin gate oxides

Abstract Gate oxide scaling effect on plasma charging damage is discussed for various IC fabrication processes such as metal etching, contact oxide etching, high current ion implantation, and via contact sputtering. Capacitance distortion, stress-induced leakage current, MOSFET characteristics, and circuit performance are used for evaluating the charging damage. We observed that very thin gate oxides are less susceptible to the charging damage because of their lower rate of interface damage, larger charge-to-breakdown, and less device determined stress voltage in the plasma system. We also discuss the diode protection scheme and design techniques for minimizing the charging damage. Latent damage exists after thermal annealing and can be revealed during the subsequent device operation causing circuit performance degradation. High density plasma etching is a trend of the etching technology as it provides better anisotropy, selectivity, and uniformity. Its effects on oxide charging damage is compared with low-density plasma etching. The resistance to process-induced charging damage of future devices appears to be high. This is counter-intuitive and is a good tiding for the future of IC manufacturing. The emergence of alternative gate dielectric raises questions about charging damage that requires further studies.

Oxide thickness dependence of plasma charging damage

Abstract Charging damage induced in oxides with thickness ranging from 8.7 to 2.5 nm is investigated. Results of charge-to-breakdown ( Q bd ) measurements performed on control devices indicate that the polarity dependence increases with decreasing oxide thickness at both room and elevated temperature (180°C) conditions. As the oxide thickness is thinned down below 3 nm, the Q bd becomes very sensitive to the stressing current density and temperature. Experimental results show that severe antenna effect would occur during plasma ashing treatment in devices with gate oxides as thin as 2.6 nm. It is concluded that high stressing current level, negative plasma charging, and high process temperature are key factors responsible for the damage.

Correlation Between Gate Induced Drain Leakage and Plasma Induced Interface Traps

ABSTRACTIn this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain leakage current caused by plasma charging damage is a function of metal 1 antenna area/length ratio and cell location. Combined with the charge pumping measurements, it is found that gate induced drain leakage current enhancement is mainly due to the plasma induced interface traps. A linear relationship between the gate induced drain leakage and the plasma induced interface trap density is observed within the experimental error. On the other hand, the threshold voltage measurements show that oxide trapped charge has no major contribution to, and no correlation with, the gate induced drain leakage current for thin gate oxide MOSFET devices.