Plasma Charging Damage Research Articles

The improvement of MOSFET performance by the optimization of STI HDP-CVD integration process

The integration process of shallow trench isolation (STI) deposition was systematically investigated by using high-density plasma chemical vapor deposition (HDP-CVD). Two sputtering agents, Ar and H2, were utilized with various plasma RF power conditions. The STI HDP-CVD process consisted of two steps, including liner oxide and main gap-fill depositions. For the liner oxide deposition, the usage of Ar plasma was more favorable than H2 plasma because the drift of hydrogen-ions was detrimental for the electrical property of gate oxide. In the gap-fill process, H2 plasma with high bias RF power efficiently reduced plasma charging damage (PCD) on gate oxide due to its low sputtering rate and densely filled STI. The gap-fill capability and PCD were improved by the optimized condition of STI HDP-CVD process.

Analytic Model of Threshold Voltage Variation Induced by Plasma Charging Damage in High-k Metal–Oxide–Semiconductor Field-Effect Transistor

We discuss plasma charging damage (PCD) to high-k gate dielectrics and the resultant threshold voltage shift (ΔVth) in n-channel metal–oxide–semiconductor field-effect transistors (n-ch MOSFETs). The PCD induced by the antenna effect is focused on, and ΔVth and its variation are estimated for MOSFETs treated by various plasma processes. We propose a ΔVth variation model based on both the power-law dependence of ΔVth on the antenna ratio r (= exposed metal interconnect area/gate area) and the r distribution deduced from an interconnect-length distribution function (ILDF) in a large-scale integrated (LSI) circuit. Then, we simulate the variations in ΔVth [σ(ΔVth)] and the subthreshold leakage current Ioff [σ(Ioff)], in accordance with the employed r distribution. The model prediction quantitatively shows the effects of PCD on σ(ΔVth) and σ(Ioff): The antenna effect is found to increase σ(ΔVth) and σ(Ioff).

Comparative Study of Plasma-Charging Damage in High-k Dielectric and p–n Junction and Their Effects on Off-State Leakage Current of Metal–Oxide–Semiconductor Field-Effect Transistors

Plasma-induced charging damage (PCD) to a metal–oxide–semiconductor field-effect transistor (MOSFET) with a high-k dielectric was studied in detail using a capacitively coupled plasma reactor for various exposure times. From the drain current versus gate voltage characteristics, we observed the threshold voltage shift (ΔVth) and the increase in reverse-leakage current (Ij) at the n+/p junction in plasma-exposed n-channel MOSFETs. The observed ΔVth in the negative direction was due to positive trap-site creation in the high-k dielectric. The combined effect by PCD increased off-state leakage current (Ioff) in n-channel MOSFETs, however, the Ij increase was found to be dominant in the Ioff increase. By employing a capacitance-measurement technique, we clarified that the Ij considerably was increased at the junction by PCD, whereas the maximum capacitance at the junction in accumulation decreased. We also identified that the generated defect site density (nd) at the junction induces the observed Ij increase as a trap-assist tunneling site.

Comparative Study of Plasma-Charging Damage in High-kDielectric and p–n Junction and Their Effects on Off-State Leakage Current of Metal–Oxide–Semiconductor Field-Effect Transistors

Comparative Study of Plasma-Charging Damage in High-<i>k</i>Dielectric and p–n Junction and Their Effects on Off-State Leakage Current of Metal–Oxide–Semiconductor Field-Effect Transistors

A comprehensive study of various etch processes for the removal of silicide-block-film in submicron CMOS technologies

The removal of silicide-block-film is crucial for device stability, reliability and subsequent silicide formation. In this paper, various silicide block etch processes, i.e. dry and wet etch, were studied and compared. Possible plasma charging damage during dry etch might caused unstable PMOS threshold voltage ( V th) during H 2 annealing. The impacts of the plasma-process-induced-damage (PPID), including V th shift, its channel length dependency, and its thermal stability were investigated. The PPID can be eliminated by reducing bias power and magnetic field, while sacrificing etch rate (ER) and equipment throughput. The main advantages of wet etch are immunity from PPID, and little surface damage resulting in uniform silicide formation. However, it also has disadvantages: buffered oxide etchant (BOE) leads to the appearance of poly pinholes, and diluted hydrofluoric acid (DHF) peels the photoresist (PR) off. Therefore, wet etch can only be used in the situation of short etching time such as the combined dry and wet etch.

Light Switched Plasma Charging Protection Device for High-Field Characterization and Flash Memory Protection

Plasma charging damage (PCD) is usually measured by comparing the measurement results of an undamaged reference structure to the results of structures, which intentionally received PCD. If wafer level reliability structures are required, these test structures, including the damage amplifying antenna, have to be small enough to fit into the scribeline. However, when these test structures, usually transistors, become smaller, it is harder to realize damage-free reference structures, since the ratio from pad antenna to gate area will increase. To avoid this effect, protection devices are commonly placed parallel to the gate of the reference transistors. However, most protection devices do not allow high-field measurement or the use of both polarities, which is important for in-depth PCD analysis. A device, which at the same time protects the test structure from PCD and also permits bipolar high-field stress to be applied to the test structure, is shown in this paper. Its usefulness is demonstrated on a realistic test structure and as a protection device for Flash memory cells.

Mechanism Analysis of Plasma Charging Damage on Gate Oxide for HDP FSG Process

For its stability and relatively lower K value, FSG (fluorine silica glass) is widely used in 0.18μm and below VLSI process. In this paper, the plasma charging damage on 30Aå gate oxide from the high-density-plasma deposition (HDP) of FSG is investigated. Positive and negative nondestructive JTDDB stress is applied to fresh transistors to simulate the plasma charging current. According to the results comparison, positive plasma stress at the end of the HDP-CVD FSG deposition is found to be the major cause of damage. The damage is located near the Gate/SiO2 interface. By increasing the FSG thickness, the damage is effectively suppressed.

Bias frequency dependence of pn junction charging damage induced by plasma processing

Plasma-induced charging damage to pn junction in metal-oxide-semiconductor field-effect transistors (MOSFETs) was studied by using an inductively coupled plasma (ICP) reactor with Ar gas. The junction leakage current ( I leak) was measured for various source/drain to well in MOSFETs and simple diode structures. Two different rf bias frequencies, 13.56 MHz and 400 kHz, were utilized to investigate the effect of frequency on an increase in I leak. The I leak of n +/p and p +/n junctions was found to increase by a plasma treatment. In particular, more severe damage was observed for n +/p junction in both n-channel MOSFETs and the diodes. These observed results imply that plasma plays a role primarily as a positive current source. With regard to the rf bias frequency effects, samples exposed to the 400-kHz plasma were found to suffer from larger I leak than those to the 13.56 MHz. From capacitance–voltage ( C– V) measurement of junction capacitance changes, we also clarified that the observed increase in I leak was attributed to the defect density at pn junction created by the plasma charging damage.

Mechanism and CHARM2 Evaluation of P-Channel Metal Oxide Semiconductor Threshold Voltage Drop during High Density Plasma Heat-up Process

Plasma damage during the plasma deposition process is one of the most critical device characteristic issues facing complementary metal oxide semiconductor field effect transistor (CMOSFET) technology. In this paper, the CHARM2 monitoring system is used to evaluate UV damage and plasma charging damage during a high density plasma chemical vapor deposition (HDP-CVD) heat-up process. As a result, the amount of UV damage and negative charging damage is increased as the HDP-CVD heat-up process source power is increased. The main cause of P-channel metal oxide semiconductor field effect transistor (PMOSFET) threshold voltage drop is UV photon facilitated gate oxide electron trapping at the gate oxide and substrate P-channel interface during the HDP-CVD heat-up process. In N-channel metal oxide semiconductor field effect transistor (NMOSFET), when negative gate voltage stress is increased, gate oxide energy bend is flattened. Electrons cannot be trapped at the gate oxide and substrate N-channel interface. Therefore, the NMOSFET threshold voltage is constant during the HDP-CVD heat-up plasma process.

Statistical Characterization of Process-Induced Plasma Damage

During plasma processes, charging damage produces various defects in silicon oxide, thereby deteriorating device performance. Optimizing process-induced charging damage requires a computer model, as well as a quantitative analysis of process parameter effects. In this study, plasma charge damage on threshold voltage of metal-semiconductor field-effect transistors is statistically investigated. This includes the analysis of main and interaction effects of process parameters, as well as the construction of response surface models. Charging damage is characterized by means of a statistical experiment. Four types of statistical regression models are constructed. A model with the largest R-Square (R2) fit of 90.6 is chosen for the response surface analysis. Analysis of the main effects revealed that radio frequency power and gas ratio are the most significant and least significant factors, respectively. Among various interaction terms, only the interaction between radio frequency power and bias is found to be influential. Meanwhile, several conflicting effects are noted as the bias power or gas ratio are varied. An optimized regression model is used to understand parameter effects on plasma charging damage.

Neural Network Model of Plasma Charging Damage on MOSFET Device

Plasma-induced charging damage can degrade device reliability considerably. Constructing charging damage model is important since it can be used for qualitative parameter effect analysis as well as for process optimization. In this study, a backpropagation neural network was used to capture causal relationships between process parameters and plasma charging-damaged metal-oxide semiconductor (MOS) device. For a systematic modeling, plasma charging damage process was characterized by means of a face-centered Box Wilson experiment. As a charge collector, aluminum antennae were connected to MOS device. The prediction performance of BPNN was optimized as a function of training factors. Electrical device characteristics modeled include threshold voltage (V), subthreshold swing (S), and transconductance (G). The normalized prediction errors are 1.84, 2.99, and 1.87{%} for V, S, and G, respectively. The optimized models were compared to statistical regression and fuzzy logic models. The comparison revealed that neural network models yielded more improved predictions over either of them. The improvement was even more than 40{%} for V and S.

Plasma Charging Damage Affecting Flash Memory Device Encountered at Pad Etch

This paper is to present plasma charging damage affecting 0.18 micron flash memory product. The affected product encountered high voltage N-MOS transistor current leakage. Correlation analysis pointed towards the passivation / pad etch step. Engineering splits were performed to isolate and understand the root cause. Several factors were suspected contributing to the current leakage. These factors are categorized by recipe, consumable kit and product technology (process flow). Further splits were performed with the consumable kits divided into three groups; quartz group, anodized aluminum group and the gas distribution plate group. The focus of this paper is to highlight the combined impact of high power radio frequency (RF) from process recipe with equipment consumable parts intrinsic defect affecting flash memory device causing plasma charging damage. This paper also investigates the effectiveness of electrical test rework procedure utilizing ultraviolet (UV) erase.

Use of adaptive network fuzzy inference system to predict plasma charging damage on electrical MOSFET properties

A prediction model of plasma-induced charging damage is presented. The model was constructed using adaptive network fuzzy inference system (ANFIS). The prediction performance of ANFIS model was optimized as a function of training factors, including a step-size, a normalization factor, and type of membership function. Charging damage data were obtained from antenna-structured MOSFET with the variations in process parameters. For a systematic modeling, the experiment was characterized by means of a face-centered Box Wilson experiment. Electrical properties modeled include a threshold voltage ( V), a subthreshold swing ( S), and a transconductance ( G). Both S and G were found to be considerably affected by the normalization factor. For the variations in the type of membership function, either V or S was the most significantly influenced. The optimized root mean square errors are about 0.041 (V), 5.040 (mV/decade), and 12.311 (×10 −6/Ω), respectively. Better predictions were demonstrated against statistical regression models and the improvements were even more than 15% for V and S models.

Comparative Study of Plasma Source-Dependent Charging Polarity in Metal–Oxide–Semiconductor Field Effect Transistors with High-k and SiO2 Gate Dielectrics

The polarities of charging damage in n- and p-channel metal–oxide–semiconductor field effect transistors (MOSFETs) with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar- and Cl-based gas mixtures) and found to depend on plasma conditions, in contrast to those with conventional SiO2. It was also found that high-k devices were more susceptible to plasma charging damage than SiO2 devices. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-channel MOSFETs with high-k gate stacks suffer from negative charge trapping, whereas for Cl-plasma confirmed to induce less damage, both n- and p-channel MOSFETs with high-k gate stacks suffer from positive charge trapping. The above-mentioned plasma-source-dependent charging damage was also compared on the basis of the results obtained by the plasma diagnostics. From the results of constant-current stress tests, the unique charging polarity observed for the high-k gate stack was attributed to the characteristic hole and electron trapping phenomena, in accordance with the injected stress current and stress time, implying the necessity of taking the intrinsic charge trapping process into consideration for accurate evaluations of charging damage on high-k gate dielectrics.

Fabrication process development for superconducting VLSI circuits: minimizing plasma charging damage

In order to realize the potential of superconducting digital integrated circuits and make them competitive with semiconductor ICs, their integration scale must be increased from a current level of ~ 104 Josephson junctions (JJs) per chip to a VLSI level, and the maximum clock frequency, currently ~ 30 GHz, must also be increased above 50 GHz. It is shown that the main factor preventing successful fabrication of VLSI superconducting digital circuits is variations of the Josephson critical currents in logic cells caused by plasma-induced charging damage (electric stress) to the ultra thin oxide tunnel barrier of JJs. The results are presented for Nb/Al/AlOx/Nb tunnel junctions fabricated on 150-mm wafers by an 11-level process for superconducting integrated circuits. It is shown that, as a result of charging in processing plasmas, the critical current Ic of JJs becomes dependent on the way the junctions are connected to the circuit ground plane and interconnected with other circuit elements. For instance, the Ic of the grounded junctions may abnormally increase with respect to the Ic of the floating junctions. Depending on the processing plasma parameters, plasma charging can damage all junctions in a circuit or only some specific junctions, e.g., the smallest in size. In addition to the Ic enhancement, the damage also reveals itself as increased subgap conduction in tunnel junctions and as an enhanced spread of the critical currents of the same-size junctions, a result of the statistical nature of the oxide barrier breakdown under electric stress. The plasma damage model is proposed and the most damaging plasma processing fabrication steps are discussed as well as the ways of minimizing the plasma-induced charging damage to superconducting integrated circuits.

Advanced Plasma and Advanced Gate Dielectric—A Charging Damage Prospective

Current status of plasma charging damage is assessed. The impact of wide adaptation of high density plasma in IC processing to charging damage is examined for advanced CMOS technology where ultrathin gate oxide is used. The issue of measurement is high-lighted. The resulting misconception of plasma charging damage is no longer a problem when gate oxide is ultrathin is explained as a result of measurement difficulty as well as previously unexpected longer oxide lifetime.

Improved reliability of HfO/sub 2//SiON gate stack by fluorine incorporation

Effects of fluorine (F) incorporation on the reliabilities of pMOSFETs with HfO/sub 2//SiON gate stacks have been studied. In this letter, fluorine was incorporated during the source/drain implant step and was diffused into the gate stacks during subsequent dopant activation. The authors found that F introduction only negligibly affects the fundamental electrical properties of the transistors, such as threshold voltage V/sub th/, subthreshold swing, gate leakage current, and equivalent oxide thickness. In contrast, reduced generation rates in interface states and charge trapping under constant voltage stress and bias temperature stress were observed for the fluorine-incorporated split. Moreover, the authors demonstrated for the first time that F incorporation could strengthen the immunity against plasma charging damage.

Ultrathin Gate-Oxide Breakdown—Reversibility at Low Voltage

Solid-insulator breakdown always leads to a permanent conduction path that is irreversible. This is a built-in assumption in all gate-oxide breakdown reliability measurement and lifetime projection. This assumption is not valid when the gate-oxide thickness is less than 2 nm and the operation voltage is 1 V or less. The authors examine the impact of reversible breakdown using breakdown data from 12 000 devices stressed by plasma charging damage. The data support the notion that when the surge current is limited at breakdown, the breakdown event may not leave any mark such as a permanent conduction path. The implication is that the commonly used accelerated-stress test, such as time dependent dielectric breakdown (TDDB), may be underestimating the actual gate-oxide lifetime by as much as a million folds.

Composition, structure, and electrical characteristics of HfO2 gate dielectrics grown using the remote- and direct-plasma atomic layer deposition methods

Hafnium oxide thin films were deposited using both the remote-plasma atomic layer deposition (RPALD) and direct-plasma atomic layer deposition (DPALD) methods. Metal-oxide semiconductor (MOS) capacitors and transistors were fabricated with HfO2 gate dielectric to examine their electrical characteristics. The as-deposited RPALD HfO2 layer exhibited an amorphous structure, while the DPALD HfO2 layer exhibited a polycrystalline structure. Medium-energy ion scattering measurement data indicate that the interfacial layer consisted of interfacial SiO2−x and silicate layers. This suggests that the change in stoichiometry with depth could be related to the energetic plasma beam used in the plasma ALD process, resulting in damage to the Si surface and an interaction between Hf and SiO2−x. The as-deposited RPALD HfO2 films had better interfacial layer characteristics, such as an effective fixed oxide charge density (Qf,eff) and interfacial roughness than the DPALD HfO2 films did. A MOS capacitor fabricated using the RPALD method exhibited an equivalent oxide thickness (EOT) of 1.8nm with a Qf,eff=−4.2×1011q∕cm2 (where q is the elementary charge, 1.6022×10−19C), whereas a MOS capacitor fabricated using the DPALD method had an EOT=2.0nm and a Qf,eff=−1.2×1013q∕cm2. At a power=0.6MV∕cm, the RPALD n-type metal-oxide semiconductor field-effect transistor (nMOSFET) showed μeff=168cm2∕Vs, which was 50% greater than the value of the DPALD nMOSFET (μeff=111cm2∕Vs). In the region where Vg-Vt=2.0V, the RPALD MOSFET drain current was about 30% higher than the DPALD MOSFET drain current. These improvements are believed to be due to the lower effective fixed charge density, and they minimize problems arising from plasma charging damage.

Screening of Si–H bonds during plasma processing

This work investigates the screening of Si–H bonds at the Si–SiO 2 interface in an n-channel MOSFET due to plasma charging damage. Since CMOS devices are subjected to high field electron injection during plasma processing, this condition was emulated by subjecting the devices to current stress (both gate injection and substrate injection). With the source and drain terminals reverse biased by a screening potential during stress, representing the impact from source and drain antenna, a decrease in stress-induced interface state density formation was noticed. Observed interface state density D it before and after the high field injection, therefore, demonstrates an effective screening of the source and the drain edges. During gate injection the Si–H bond concentration, estimated using a model based on a simple first order kinetic equation, is inversely proportional to measured D it at effective screening potentials. In substrate injection, however, the Si–H concentration does not relate to D it creation. Similar trends were observed for transistors with different antenna ratios. Subsequent hot carrier stress confirms that the screening is mainly due to protected drain edges. These results suggest that effective screening of Si–H bonds is possible during plasma processing.