Silicon Plane Research Articles

Digital holographic interferometry method for tracking detector modules displacement

In high energy particle physics scattering experiments, the precision of the reconstructed particle tracks can be fundamental. For this reason, a method for detecting the displacement of tracking detector modules is developed. The modules are silicon planes mounted on a frame and used in the MUonE project, which aims at a precision measurement of the scattering angle of elastic muon-electron scattering. From the scattering angle, the hadronic contribution to the anomalous magnetic moment of the muon is extracted. To achieve the desired accuracy, the position of the tracking detector planes must be monitored. The allowable relative displacements must be less than 10 μ m. To meet the specifications and to monitor as large an area of the detector as possible, a digital holographic interferometer was developed. It is based on a novel lens-less design in off-axis holographic geometry. Light from a fiber-coupled laser source is split by a fiber beam splitter, with one output used to illuminate the detector plane and the other for the reference beam. The two beams produce an interference pattern on a CMOS image sensor. To obtain relative displacement information, successive images are superimposed on an initial reference image and reconstructed by solving the Rayleigh-Sommerfeld diffraction integral taking into account the spherical wavefronts of the beams. The interference fringes that appear in the reconstructed holographic image provide a measure of the relative displacement of the detector plane compared to the initial position. The performance of the reconstruction method used was verified with the proposed setup at a real tracking station.

Peridynamic modeling of nonlinear surface acoustic waves propagating in orthotropic materials

Due to the elastic nonlinearity of the material, high-amplitude surface acoustic waves undergo nonlinear evolution during propagation and may lead to material failure. To enable the acoustical quantification of material nonlinearity and strength, a comprehensive understanding of this nonlinear evolution is necessary. This paper presents a novel ordinary state-based nonlinear peridynamic model for the analysis of the nonlinear propagation of surface acoustic waves and brittle fracture in anisotropic elastic media. The relationship between seven peridynamic constants and second- and third-order elastic constants is established. The capability of the developed peridynamic model has been demonstrated by predicting surface strain profiles of surface acoustic waves after propagating in the silicon (111) plane and the 〈112¯〉 direction. On this basis, the nonlinear wave-induced spatially localized dynamic fracture is also studied. The numerical results reproduce the main features of nonlinear surface acoustic waves and fracture observed in experiments.

Epitaxial growth of V2O3 thin films on Si(1 1 1) by molecular beam epitaxy

Vanadium sesquioxide (V2O3) is a strongly correlated electron material exhibiting two distinct metal–insulator transitions that can be tuned via strain, doping, or pressure, making it an interesting material for new-generation sensors or smart devices. For this purpose, it is required to achieve well-ordered epitaxial thin film growth with high-quality electrical and optical properties on technologically relevant substrates. We report the successful growth of epitaxial thin films of V2O3 via molecular beam epitaxy, in the paramagnetic insulating (PI) phase on the (111) plane of silicon, by tailoring the growth conditions. Extensive electrical, structural, and morphological characterization both in situ and ex situ has been performed on all samples. The structural analysis reveals that temperature plays a more impactful role in affecting the thin film microstructures than the oxygen partial pressure. When the epitaxy of V2O3 occurs on the unoxidized (111) plane of silicon, four equivalent epitaxial domains begin to form, leading to twin boundaries in the bulk of the film. The considerable lattice mismatch between silicon and V2O3 induces the growth of the corundum PI phase. Lastly, small deviations from stoichiometry due to different oxygen inflow during growth alter significantly the resistivity change upon cooling.

Multiple scattering of channeled and non-channeled positively charged particles in bent monocrystalline silicon

We present the results of an experimental study of multiple scattering of positively charged high-energy particles in bent samples of monocrystalline silicon. This work confirms the recently discovered effect of a strong reduction in the rms multiple scattering angle of particles channeled in the silicon (111) plane. The effect is observed in the plane orthogonal to the bending plane. We show in detail the influence of angular constraints on the magnitude of the effect. Comparison of the multiple scattering process at different energies indicates a violation of the law of inverse proportionality of the rms angle of channeled particles with energy. By increasing the statistics, we have improved the results of multiple scattering measurements for particles moving, but not channeled, in silicon crystals.

Self-adaptive near-filed thermal stabilizer

Analogous to an electrical circuit, a thermal circuit/calculator relying on the heat current to transfer information has been recently proposed as a substitute for applications in extreme environments, where electronic devices may not work. However, different from the electric circuit which could easily get electrically insulated, the thermal one has to face the challenge of temperature fluctuations from the external environment. Taking advantage of the negative thermal expansion (NTE) characteristics of ZrW2O8 and the high sensitivity of the near-filed thermal radiation (NFTR) between two doped silicon (D-Si) planes to the vacuum distance, a self-adaptive near-field stabilizer is designed with the D-Si plane as the emitter/receiver and ZrW2O8 as the substrate for the emitter in present study. The radiation terminal is driven by the NTE substrate to adjust the vacuum distance to neutralize the temperature change, which stabilizes the near-field thermal radiation. The numerical results, obtained by the fluctuational dissipation theorem, show that the heat flow fluctuation is within 5% with the emitter temperature change in the range of 365-435 K and a total heat flux around 4 kW m−2. As a comparison, the heat fluctuation could be more than 50% for the case without the NTE substrate. This study also systematically explores the factors affecting the steadiness of the heat flow. The proposed thermal stabilizer could self-regulate the heat flow to keep it stable regardless of external temperature fluctuation, which is essential as one of the basic elements in a thermal circuit and could lay the foundation for thermal calculation.

Investigation of the oxidation of plasma sprayed silicon coating

The quality of plasma sprayed silicon coating determined by density and spreading condition of lamella greatly influences its performance. The oxidation of silicon coating deteriorates its performance. However, the investigators mostly focus on the oxidation and mechanism of amorphous silicon, porous silicon and specific crystal planes on single crystal. The factors which influence the quality and oxidation of silicon coating has never be studied.The helium secondary gas flow has more influence on the quality of silicon coating than other spraying parameters. So, we prepare the silicon coating by plasma spraying technology with different secondary gas flow. The relationship between silicon coating's quality and secondary gas flow is investigated. Furthermore, the oxidation of plasma sprayed silicon coating is discussed. We find that the secondary gas has an adverse effect on quality and oxidation degree of silicon coating. With the decrease of secondary gas flow, both quality and oxygen content of coatings increase. Besides, the oxygen atoms heterogeneously concentrate at the outermost layer of silicon lamellas. Components of oxygen enrichment area (OEA) from outside to inside are Si + SiOx + SiO2→Si + Si2O + SiO2→Si + SiOx→Si (1<x < 1.5). The width of OEA in lamellas at top layer of silicon coating is about 180 nm, obviously thicker than that in inner lamellas. The results obtained from research can provide support to better understand the behavior of silicon coating in the service process.

Coherent control of a donor-molecule electron spin qubit in silicon

Donor spins in silicon provide a promising material platform for large scale quantum computing. Excellent electron spin coherence times of {T}_{2}^{* }=268 μs with fidelities of 99.9% have been demonstrated for isolated phosphorus donors in isotopically pure 28Si, where donors are local-area-implanted in a nanoscale MOS device. Despite robust single qubit gates, realising two-qubit exchange gates using this technique is challenging due to the statistical nature of the dopant implant and placement process. In parallel a precision scanning probe lithography route has been developed to place single donors and donor molecules on one atomic plane of silicon with high accuracy aligned to heavily phosphorus doped silicon in-plane gates. Recent results using this technique have demonstrated a fast (0.8 ns) two-qubit gate with two P donor molecules placed 13 nm apart in natSi. In this paper we demonstrate a single qubit gate with coherent oscillations of the electron spin on a P donor molecule in natSi patterned by scanning tunneling microscope (STM) lithography. The electron spin exhibits excellent coherence properties, with a {T}_{2} decoherence time of 298 ± 30 μs, and {T}_{2}^{* } dephasing time of 295 ± 23 ns.

Development of MEMS-based piezoresistive 3D stress/strain sensor using strain technology and smart temperature compensation

This paper presents the microfabrication and testing of a membrane-free eight-element single-polarity (n-type) sensing rosette integrated with strained silicon technology over (111) silicon plane to measure the full 3D stress/strain tensor with full temperature compensation. Such n-type piezoresistive (PR) sensor has low sensitivity to the out-of-plane components compared to the in-plane components. To improve the sensitivity of such sensors to the out-of-plane components, a strained silicon technique was integrated into the sensing rosette during the microfabrication process using a highly compressive film produced by plasma enhanced chemical vapor deposition silicon nitride. For experimental verification, a prototype device featuring the proposed sensing rosette was microfabricated using semiconductors fabrication processes. The experimental analysis applied both, in-plane and out-of-plane stresses at different temperatures over a range from −20 °С to 60 °С. In this work, a smart sensing calibration algorithm, utilizing machine learning, is employed to reduce the temperature impact on both sensitivity and resistance of PR coefficients during stress measurement. The developed sensor is capable of accurately extracting the applied stress/strain components with temperature compensation.

Theoretical and experimental revision of surface acoustic waves on the (100) plane of silicon

The phase velocity dispersion of the surface acoustic waves on a basal plane of Si(100) has been calculated in the whole range of the azimuthal angle of propagation. We present a detailed description of the calculations. These calculations are compared with the experimental data obtained by a laser acoustic method. Our data convincingly demonstrate the existence of a gap in the spectrum of the phase velocities. The gap means that in a definite range of the phase velocities the SAWs are absent in the whole interval of the azimuthal angles. There is an excellent coincidence between the numerical and experimental data.

Hybrid Smart Temperature Compensation System for Piezoresistive 3D Stress Sensors

This paper proposes a new hybrid temperature compensation system for doped silicon-based piezoresistive 3D stress sensors. The developed compensation system integrates a temperature sensor, placed in close proximity to the stress sensing rosettes, with the artificial neural networks (ANNs). In this work, the n-type circular piezoresistor featured over (111) silicon plane was employed to capture the local temperature variations, within the sensing chip. The extracted temperature changes, along with the resistance changes, are fed, as inputs, to the ANNs to compensate the temperature effect on the acquired signals for more accurate stress measurement. The proposed compensation system was experimentally evaluated while extracting stress applied up to 60 MPa at different temperatures within a range from 0 °C to 50 °C. The developed system was successfully able reduce the maximum full scale error, obtained from using only a temperature sensor for compensation, by ~55%. The new system has merit since it has the capability to compensate for both resistance and sensitivity, for 3D stress sensor, with no need for additional circuitry. Moreover the employed temperature sensor shares the same thermal environment with the stress sensing rosette.

Study of reduction of multiple scattering of positively charged particles during channeling in (1 1 1) crystallographic silicon planes

The article proposes an analytical model to describe a recently discovered phenomenon of reduction of multiple scattering of positively charged particles during channeling in (111) crystallographic silicon planes. The phenomenon represents a strong suppression of the mean square angle of multiple scattering of such particles in a plane perpendicular to the channeling plane (in comparing with the non channeling particles). The proposed model is based on the development of our previously considered approximate description of the diffusion process in short crystals. Using successive reductions, we extended this description to fairly long crystals. Our analytical model explains the phenomenon observed in the experiments and allows us to calculate the behavior of the root-mean-square angle of channeling particles as a function of the crystal thickness.

Investigating boron and phosphorus removal from silicon by Si-Ti and Si-Ti-Fe alloying systems

B and P content of purified Si through alloying refining by Ti was investigated. 65–75% P removal and 39–80% B removal were obtained by the addition of 5–20 wt% Ti to silicon. The reduction of impurities was recognized to be attributable to the formation of Ti5P3.16 and TiB2. The iron addition (up to 20 wt%) to the Si-Ti system increased B removal from 63 to 83% and 74 to 92% in the presence of 10 wt% and 15 wt% Ti, respectively. Nevertheless, iron addition did not make any noticeable improvement in P removal. Phosphorus removal in the Fe containing samples may be ascribed by the formation of the TiFeP phase. Overall, the best impurity removal was obtained for the sample containing 15 wt% Ti + 20 wt% Fe that showed 75% P and 92% B reduction in the purified Si. The directional solidification of a sample containing 20 wt% Ti slightly improved the removal rates compared to its corresponding furnace cooled sample. Also, it resulted in the enhancement of (220) plane of silicon in the solidified alloy. At last, boron removal as a result of TiB2 formation was studied from the thermodynamic point of view.

A New Designs of Microstrip Wi-Fi-shape Nanoantenna & Microstrip Wi-Fi-shape Slot Nanoantenna at THz region

The Evolution of Terahertz technology led to focus of Scientists and Researchers on this technology field. Terahertz region lies between optics frequency range and electronics, so THz frequencies are lowest frequencies make the free space conventional optics enable still be utilized before microwave components adopt. In this paper, CST studio suite 2018 simulator is utilized to simulate and design a new Microstrip Wi-Fi-shape Nanoantenna (MWNA) & Microstrip Wi-Fi-shape Slot Nanoantenna (MWSNA). Reflection coefficient (S11), Directivity, Gain and Bandwidth are computed. The results that achieved working at Terahertz frequencies in Nano size. The Bandwidth of MWNA design and the MWSNA design working in the range of (103.3-110.3 THz) and (124.5 -127.8 THz) respectively. The Microstrip nanoantenna that utilized consist of three layers, Patch made from Gold, Substrate layer that utilized Silicon and Ground plane layer made from Gold. So the applications of these bands of THz frequencies work at visible region and near infrared (IR).

Development of Doped Silicon Multi-Element Stress Sensor Rosette With Temperature Compensation

In this paper, a developed n-type piezoresistive three dimensional (3D) stress sensor with full temperature compensation is presented. The proposed sensing rosette benefits from the stress insensitivity of the full-circular n-type piezoresistor, oriented over (111) silicon plane, to detect only temperature changes for compensation. Moreover, the unique behavior of shear piezoresistive coefficient (π44) of n-Si is utilized to construct a piezorestive stress sensing rosette over (111) silicon plane that is capable of extracting 3D stress components. A prototype stress sensing chip was microfabricatedto test the capabilityof the developedsensing rosette to accurately extract stress applied on structures at different thermal environments. The fabricated sensing chip was subjected to different mechanical loads using a loading rig with four-point bending fixture. The testing was carried out over a temperature range of 0-50 °C. The results showed that the proposed sensing chip has the capability of capturing the stress applied at different temperatures. Also, the developed sensing rosette showed less sensitivity to the uncertainty in piezoresistive coefficients' values compared to the other developed 3D piezoresistive stress sensors.

Scanning Probe Microscopy Applications in Failure Analysis of Semiconductor Devices

Abstract Scanning probe microscopy (SPM) is widely used for fault isolation as well as diagnosing leakage current, detecting open circuits, and characterizing doping related defects. In this article, the author presents two SPM applications that are fairly uncommon but no less important in the scope of failure analysis. The first case involves the discovery of nano-steps on the surface of high-voltage NFETs, a phenomenon associated with stress-induced crystalline shift along the (111) silicon plane. In the second case, the author uses an AFM probe in the conductive mode to correlate tunneling current distribution with hot spots in high-k gate oxide films, which is shown to be a better indicator of oxide quality than rms surface roughness.

Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration

The manufacturers of high-performance logic have been ardent champions of Moore's Law, which has resulted in exponential increase in aerial transistor density to 100 million transistors per square millimeter of silicon real estate. However, it is the memory chip makers who have taken the first step toward escaping the confines of scaling within the horizontal plane and have embraced the vertical or the third dimension. The dynamic random access memory manufacturers have adopted stacked capacitors that tower above the silicon plane that hosts the access and peripheral transistors, whereas the nand flash memory technologists can stack 128 layers of charge trap flash cells on top of each other in a monolithic fashion. To enable monolithic three-dimensional (M3D) integration of high-performance logic, one needs to solve the fundamental challenge of low temperature (<400 °C) in situ synthesis of high mobility n-type and p-type semiconductor thin films that can be utilized for fabrication of back-end-of-line (BEOL) compatible complementary MOS transistors under the constraint of limited thermal budget. This article discusses recent progress in the selection and optimization of semiconductor materials for BEOL compatible transistors to enable sequential M3D integration for a range of applications.

Investigation on residual scratch depth and material removal rate of scratching machining single crystal silicon with Berkovich indenter

Single crystal silicon is the basic material for the fabrication of micro-devices and micro-structures. It exhibits plastic behavior in micro/nano-machining. The key to obtain high-quality machined surfaces in ultra-precision machining of brittle materials is the material removal in ductile region. This paper focuses on single crystal silicon scratching machining in ductile region. The contact area and contact force of Berkovich indenter along two typical scratching machining directions (Φ=0° and Φ=60°) are analyzed. The residual scratch depth of typical scratching direction of Berkovich indenter is calculated theoretically. The experiments of scratching machining on (001) crystal plane of single crystal silicon using nanoindenter and Berkovich indenter are conducted. Based on experiments of nanoindenter scratching machining, the effects of normal load and scratching direction on the residual scratch depth and material removal rate in ductile region machining are investigated. Between the theoretical calculation results and the experimental results, the maximum deviation of residual scratch depth and material removal rate of Berkovich indenter scratching machining single crystal silicon is less than 3.5%. The residual scratch depth and material removal rate of Berkovich indenter scratching machining single crystal silicon along directions Φ=0° and Φ=60° are quite different. When the normal load is 10 mN and 20 mN, the material removal rate of single crystal silicon scratching machining along direction Φ=60° is more than 2 times that of along direction Φ=0°. The residual scratch depth of scratching machining single crystal silicon with Berkovich indenter varies nonlinearly with normal load, and the material removal rate is obviously affected by the direction of the scratching machining. The results in this paper are useful for the determination of process parameters for ultra-precision machining of single crystal silicon.

A New Temperature Transducer for Local Temperature Compensation for Piezoresistive 3-D Stress Sensors

In this paper, a new temperature transducer using full-circular n-type piezoresistor over (111) silicon plane is proposed as an accurate solution for local temperature compensation for piezoresistive three-dimensional (3-D) stress sensors. Analytical study, in this paper, showed that the proposed n-type full-circular piezoresisor over (111) has near-zero response under 3-D state of stress. As an experimental verification, a test device with n-type piezoresistive stress sensing elements oriented over (111) plane at 0° and 90° to crystallographic direction $[ {\bar{1}10} ]$ was microfabricated to test the capability of the proposed temperature compensator. The test device was subjected to a uniaxial load up to 50 MPa using a loading rig with four-point bending fixture. The testing was performed over a temperature range of 0–50 °С. The results showed that the proposed temperature transducer has a linear response to temperature excitation. The fabricated transducer is capable of accurately capturing the local temperature changes with maximum absolute error of ±0.8 °С. This compensation system is advantageous for piezoresistive stress/strain sensors, since the temperature transducer has the same thermal environment with the stress/strain-sensing rosette. Moreover, this technique does not require additional circuitry on the sensing device itself.

Effect of Seed Layer and Thermal Annealing on Structural and Optical Properties of Silicon Layers Deposited by PECVD

Hydrogenated silicon (Si:H) layers have been deposited on crystalline silicon substrate by radiofrequency plasma-enhanced chemical vapor deposition technique (rf-PECVD) from SiH4/H2 gas mixture using different deposition times and after a seed layer with thickness of 70 nm (to improve the nucleation of nanocrystallites). The effect of the deposition time on the as-deposited and annealed layers was investigated. Ultraviolet–visible–infrared (UV–Vis–IR) spectroscopy was used to determine the thickness of the layers. Before annealing, the layer thickness showed a linear variation with deposition time in the range from 450 s to 1500 s. On the other hand, for deposition times of 450 s, 600 s, and 1500 s, the layers showed an x-ray diffraction (XRD) peak corresponding to the (111) crystal plane of Si. Raman spectroscopy confirmed the appearance of the crystalline phase in these layers. Raman scattering studies showed that, when using the short deposition time for the top layer, the crystalline peak dominated. We deduce that insertion of a seed layer improves the crystallinity of the top layer. In addition, the crystallinity increased slightly with the deposition time. The structural properties of the layers annealed at 900°C were studied by Raman spectroscopy and XRD analysis. We noted an increase in the crystalline volume fraction and the appearance of (111) crystal plane of silicon, confirming the transition from amorphous to nanocrystalline phase for all the annealed films.

Side-Supported Radial-Mode Thin-Film Piezoelectric-on-Silicon Disk Resonators.

In this paper, anisotropy of single-crystalline silicon (SCS) is exploited to enable side-supported radial-mode thin-film piezoelectric-on-substrate (TPoS) disk resonators. In contrast to the case for isotropic material, it is demonstrated that the displacement of the disk periphery is not uniform for the radial-mode resonance in SCS disks. Specifically, for high-order harmonics, nodal points are formed on the edges, creating an opportunity for placing suspension tethers and enabling side-supported silicon disk resonators at the very high-frequency band with negligible anchor loss. In order to thoroughly study the effect of material properties and the tether location, anchor loss is simulated using a 3-D perfectly matched layer in COMSOL. Through modeling, it is shown that eighth-harmonic side-supported SCS disk resonators could potentially have orders of magnitude lower anchor loss in comparison to their nanocrystalline diamond (NCD) disk resonator counterparts given the tethers are aligned to the [100] crystalline plane of silicon. It is then experimentally demonstrated that in TPoS disk, resonators fabricated on an 8- [Formula: see text] silicon-on-insulator (SOI) wafer, unloaded quality factor improves from ~450 for the second-harmonic mode at 43 MHz to ~11500 for the eighth-harmonic mode at 196 MHz if tethers are aligned to [100] plane. The same trend is not observed for NCD disk resonators and SCS disk resonators with tethers aligned to [110] plane. Finally, the temperature coefficient of frequency is simulated and measured for the radial-mode disk resonators fabricated on the 8- [Formula: see text]-thick degenerately n-type doped SCS, and the TFC data are utilized to guarantee proper identification of the harmonic radial-mode resonance peaks among others.