Pipelined Coordinate Rotation Digital Computer Research Articles

An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks

Practical implementation of deep neural networks (DNNs) demands significant hardware resources, necessitating high computational power and memory bandwidth. While existing field-programmable gate array (FPGA)–based DNN accelerators are primarily optimized for fast single-task performance, cost, energy efficiency, and overall throughput are crucial considerations for their practical use in various applications. This article proposes a performance-centric pipeline Coordinate Rotation Digital Computer (CORDIC)–based MAC unit and implements a scalable CORDIC-based DNN architecture that is area- and power-efficient and has high throughput. The CORDIC-based neuron engine uses bit-rounding to maintain input-output precision and minimal hardware resource overhead. The results demonstrate the versatility of the proposed pipelined MAC, which operates at 460 MHz and allows for higher network throughput. A software-based implementation platform evaluates the proposed MAC operation’s accuracy for more extensive neural networks and complex datasets. The DNN accelerator with parameterized and modular layer-multiplexed architecture is designed. Empirical evaluation through Pareto analysis is used to improve the efficiency of DNN implementations by fixing the arithmetic precision and optimal pipeline stages. The proposed architecture utilizes layer-multiplexing, a technique that effectively reuses a single DNN layer to enhance efficiency while maintaining modularity and adaptability for integrating various network configurations. The proposed CORDIC MAC-based DNN architecture is scalable for any bit-precision network size, and the DNN accelerator is prototyped using the Xilinx Virtex-7 VC707 FPGA board, operating at 66 MHz. The proposed design does not use any Xilinx macros, making it easily adaptable for ASIC implementation. Compared with state-of-the-art designs, the proposed design reduces resource use by 45% and power consumption by 4× without sacrificing performance. The accelerator is validated using the MNIST dataset, achieving 95.06% accuracy, only 0.35% less than other cutting-edge implementations.

Research and Implementation of a Numerical Control Oscillator with Improved Pipelined CORDIC Algorithm

As the recognized core of electronic systems, frequency synthesizers have been applied in many communication fields. NC oscillator (NCO) is the main component of the frequency synthesizer. It helps to generate high-precision and high-frequency signals, so it has been widely used. NCO implementation methods include table lookup method, polynomial expansion method, coordinate rotation digital computer (CORDIC) algorithm, etc. CORDIC algorithm is one of many commonly used methods in trigonometric function calculation and digital signal processing, and is often used as the core of DDS (direct digital synthesis) to generate signals. Compared with table lookup and polynomial expansion, CORDIC algorithm has higher efficiency in signal generation and hardware utilization. In view of the disadvantages of traditional CORDIC algorithm, which takes up large resources and has relatively slow calculation speed, in order to improve the output efficiency, this paper uses an efficient 12-stage pipelined CORDIC architecture and a very small lookup table (LUT) to implement a sine wave generator. The system is coded and simulated in Quartus and ModelSim. The results show that the proposed structure can increase the operating speed of the system from 217.77 MHz to 291.04 MHz, and improve the output efficiency of the system.

CORDIC Hardware Acceleration Using DMA-Based ISA Extension

The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware acceleration and Instruction Set Architecture (ISA) extension. Recent publications of AI have demonstrated the use of Coordinate Rotation Digital Computer (CORDIC) as a dedicated low-power solution for solving nonlinear equations applied to Neural Networks (NN). This paper proposes ISA extension to support floating-point CORDIC, providing efficient hardware acceleration for mathematical functions. A new DMA-based ISA extension approach integrated with a pipeline CORDIC accelerator is proposed. The CORDIC ISA extension is directly interfaced with a standard processor data path, allowing efficient implementation of new trigonometric ALU-based custom instructions. The proposed DMA-based CORDIC accelerator can also be used to perform repeated array calculations, offering a significant speedup over software implementations. The proposed accelerator is evaluated on Intel Cyclone-IV FPGA as an extension to Nios processor. Experimental results show a significant speedup of over three orders of magnitude compared with software implementation, while applied to trigonometric arrays, and outperforms the existing commercial CORDIC hardware accelerator.

Low latency pipelined CORDIC-like rotator architecture

ABSTRACTThis work presents a Field Programmable Gate Array (FPGA) prototyping of a new low latency pipelined COordinate Rotation DIgital Computer (CORDIC)-like rotator. The proposed rotator predicts the directions for all rotations in parallel and determines the final coordinates using the architecture with logarithmic relation between the number stages and precision of the target angle. The functionality of the pipelined CORDIC-like rotator is verified by implementing on the Xilinx Virtex-4 pro device (XC4vlx40, 90 nm technology). Based on detailed comparisons with the available pipelined rotators for the resolution of 8–12 bits, it is observed that the proposed rotator requires less hardware and improves latency by 45–85%.

A Modified CORDIC FPGA Implementation for Wave Generation

This paper presents a modified coordinate rotation digital computer (CORDIC) algorithm implemented in parallel architecture to generate sine and cosine waveform. Since CORDIC is a combination of only additions and shifts, it can be efficiently implemented in hardware. The proposed algorithm further approximates the way of computing rotation angle based on Taylor series in order to reduce the usage of Read-Only-Memory (ROM) table. Thus area and power is reduced due to partial usage of ROM storage. The precision remains the same as the original algorithm. The modified 32-bits pipeline CORDIC are implemented in Spartan XC3S500E device using Xilinx ISE 12.3 design suite. The result is compared with original CORDIC and Xilinx coregen in device utilization. It is shown that the logic usage is 31 FFs and 285 FFs less than the original design and Xilinx core, respectively. When compared with the original design, the signal power and total power reduction at 40 MHz clocks are 7.69 % and 1.35 %, respectively. The bit error remains at 10−8 dB level. The SNR of modified CORDIC is about 2 dB lower, which is acceptable in wave generation.

CORDIC‐based window implementation to minimise area and pipeline depth

Filtering is one of the most important modules in signal processing paradigm. This study presents a field-programmable gate array implementation of various window functions using coordinate rotation digital computer (CORDIC) algorithm to minimise area-delay product. First, the authors modify the Taylor series approximation order used in the scaling-free CORDIC, to completely eliminate the scale-factor and, yet, preserve the range of convergence spanning across the entire coordinate space. Secondly, the authors propose a new generalised technique for micro-rotation sequence identification to reduce the number of iterations required by the pipelined CORDIC processor. Then, this circular CORDIC processor is used to realise window functions. The existing window architecture uses a linear CORDIC processor in series with circular CORDIC processor, resulting in long pipeline. The authors replace the linear CORDIC with multiple optimised shift-add networks to reduce area and pipeline depth. As a result, the proposed window architecture, on an average requires approximately 64.34% less pipeline stages and saves up to 48% area. The authors have designed the processor to implement Hanning, Hamming and Blackman window families. The implementation of the proposed architecture is detailed in this study.

Reconfigurable Design of Pipelined CORDIC Processor for Digital Sine-Cosine

Digital sine and cosine waves have been used in countless applications in the field of vector rotated Digital Signal Processing (DSP). The COordinate Rotation DIgital Computer (CORDIC) algorithm has become very popular due to its simplicity in catering to almost perfect digital sine and cosine waveforms during modulation and demodulation processes in DSP modules. In this paper, we have presented the design of pipelined architecture for the computation of flexible and scalable digital Sine and Cosine values using the CORDIC algorithm. The design of an application-specific CORDIC processor in circular rotation mode gives high system throughput due to pipelined architecture by reducing latency in each individual pipelined stage. Saving area on FPGA is essential to the design of pipelined CORDIC and can be achieved through optimizing the number of micro rotations. The computed quantization error is also minimized using a required number of iterations. The design has been synthesized and implemented on a Xilinx Spartan 3 device using 10.1 ISE design tool suite and results are shown and discussed.

Novel architecture for QAM modulator–demodulator and its generalization to multicarrier modulation

This paper presents an architecture for quadrature amplitude modulation (QAM) modulator and demodulator with hardware economic structure. While the modulator part requires simple logic circuits for its implementation, the more complex demodulator utilizes Running Fourier transform based on CORDIC (Co-Ordinate Rotation DIgital Computer) processor, for demodulation as well as synchronization. The basic design philosophy has been extended to multicarrier modulation and demodulation technique by using pipelined CORDIC structure for computing Running Fourier transform. The architectures have been implemented with 16 bit wordlength in Xilinx Spartan series field programmable gate arrays (FPGA).

Virtually scaling-free adaptive CORDIC rotator

The authors propose a coordinate rotation digital computer (CORDIC) rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In the proposed scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/√2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects the appropriate iteration steps and converges to the final result by executing on average only 50% of the number of iterations required by the classical CORDIC. Unlike for the classical CORDIC, the value of the scale factor is completely independent of the number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator was implemented. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 000 inverter gates in the used 0.25 μm BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW at a 2.5 V supply voltage and a 20 Ms/s throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with the IEEE 802.11a standard.

Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations

In this correspondence, an efficient implementation of pipelined coordinate rotation digital computer (CORDIC)-based IIR digital filters based on fast orthonormal /spl mu/-rotations is proposed. Using this method, the Givens rotations are approximated by angles corresponding to orthonormal /spl mu/ rotations, which are based on the idea of CORDIC and can perform rotation with minimal number of shift-add operations. We present various methods of construction for such orthonormal /spl mu/ rotations. A significant reduction (over 70%) of the number of required shift-add operations is achieved. All types of fast rotations can be implemented as a cascade of only four basic types of shift-add stages. These stages can be executed on a modified floating-point CORDIC architecture, making the pipelined filter highly suitable for VLSI implementations.

An efficient CORDIC array structure for the implementation of discrete cosine transform

We propose a novel implementation of the discrete cosine transform (DCT) and the inverse DCT (IDCT) algorithms using a CORDIC (coordinate rotation digital computer)-based systolic processor array structure. First, we reformulate an N-point DCT or IDCT algorithm into a rotation formulation which makes it suitable for CORDIC processor implementation. We then propose to use a pipelined CORDIC processor as the basic building block to construct l-D and 2-D systolic-type processor arrays to speed up the DCT and IDCT computation. Due to the proposed novel rotation formulation, we achieve 100% processor utilization in both 1-D and 2-D configurations. Furthermore, we show that for the 2-D configurations, the same data processing throughput rate ran be maintained as long as the processor array dimensions are increased linearly with N. Neither the algorithm formulation or the array configuration need to be modified. Hence, the proposed parallel architecture is scalable to the problem size. These desirable features make this novel implementation compare favorably to previously proposed DCT implementations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>