Pinned Photodiode Pixel Research Articles

Influence of Pixel Design on Charge Transfer in Pinned Photodiode CMOS Image Sensors

The influence of pixel design on charge transfer, mainly on potential barrier and potential pocket, is investigated in this paper. By simplifying the interface region between the pinned photodiode (PPD) and the transfer gate (TG), an intuitive and simple method for analyzing the potential barrier and pocket is presented. Through TCAD simulations, the validity of the analysis method is verified, and the influence of some key dimension and process parameters in PPD pixel design on the potential barrier and pocket is clarified. The whole study help improve the understanding of the charge transfer limitation mechanism, and can achieve high charge transfer efficiency and low image lag noise in the PPD pixel design of CMOS image sensors (CISs).

Novel CMOS image sensor pixel to improve charge transfer speed and efficiency by overlapping gate and temporary storage diffusing node* *Project supported by the National Natural Science Foundation of China (Grant No. 61574112).

A novel CMOS image sensor (CIS) pinned photodiode (PPD) pixel, named as O-T pixel, is proposed and investigated by TCAD simulations. Compared with the conventional PPD pixel, the proposed pixel features the overlapping gate (OG) and the temporary storage diffusing (TSD) region, based on which the several-nanosecond-level charge transfer could be achieved and the complete charge transfer from the PPD to the floating node (FD) could be realized. And systematic analyses of the influence of the doping conditions of the proposed processes, the OG length, and the photodiode length on the transfer performances of the proposed pixel are conducted. Optimized simulation results show that the total charge transfer time could reach about 5.862 ns from the photodiode to the sensed node and the corresponding charge transfer efficiency could reach as high as 99.995% in the proposed pixel with 10 μm long photodiode and 2.22 μm long OG. These results demonstrate a great potential of the proposed pixel in high-speed applications.

3D device‐level simulation of charge separation from sidewall in vertical transfer gate pinned photodiode pixels for noise mitigation

This study proposes vertical sidewall implantation for noise reduction of CMOS image sensor pixel employing a vertical transfer gate (VTG). The pixel performance is evaluated by 3D device-level simulation. It is concluded that the proposed pixel's output is less sensitive to interface traps compared to similar previous work. In previous back-side-illuminated shared VTG pixel, which lacks the sidewall implantation for noise mitigation, photogenerated carriers were transferred to the floating diffusion (FD) region along with the interface. In the proposed pixel, the channel is separated from the interface, and photogenerated carriers are transferred with 10 nm distance from VTG. The proposed pixel has a complete charge transfer from the buried pinned photodiode to FD with 1274 e − /µm 2 equilibrium full-well capacity. The conversion gain is 200 μV/e − and the signal-to-noise ratio is 37 dB.

Analyses of Pinned Photodiodes With High Resistivity Epitaxial Layer for Indirect Time-of-Flight Applications

This article analyzes the performance of pinned photodiode (PPD) for Time-of-Flight(ToF) applications on high resistivity epitaxial wafers. Due to its wide depletion region, high epitaxial resistivity PPDs feature some key advantages in collecting photogenerated charges. This article compares the demodulation contrast of the same pixel design on epitaxial wafers with different resistivity at near-infrared wavelength to analyze their performance. By comparing the simulated profile of pixels with different epitaxial resistivity, the characteristics of the PPD pixel on high resistivity epitaxial wafer when collecting photogenerated charges are concluded. This article also discusses the effects of using high resistivity epitaxial wafer with various design parameters. It is found that the use of high resistivity epitaxial wafer can greatly improve crosstalk performance, allow pixels to work at higher modulation frequencies, and enable large-sized pixels to have good demodulation capabilities.

Exploration of Pinned Photodiode Radiation Hardening Solutions Through TCAD Simulations

The use of pinned photodiode (PPD)-based CMOS image sensors (CIS) in harsh radiation environment (such as space) is limited by their tolerance to ionizing radiation. Technology computer-aided design (TCAD) simulations are performed to reproduce the radiation-induced defect and therefore the dark current increase in PPD pixels up to 1 kGy (i.e., 100 krad) of total ionizing dose (TID). To do so, the TCAD models are calibrated with measurements performed on irradiated pixels. Then, the influence on the PPD radiation hardness of various manufacturing process and pixel design modifications are explored. This work shows that the proposed modification can improve the radiation hardness of PPD CIS against ionizing.

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias.

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

Optimization of Pinned Photodiode Pixels for High-Speed Time of Flight Applications

We discuss optimizations of pinned photodiode (PPD) pixels for indirect time of flight sensors. We focus on the transfer-gate and dumping gate regions optimization, on the PPD dimension and shape to assure fast lateral charge transfer and on the epitaxial layer thickness for a good tradeoff between fast vertical charge transfer and high quantum efficiency at near infrared region. The overall performance of the pixel is quantified by the demodulation contrast of the pixel at specific frequencies. The operation frequency of the device is determined by the required ambiguity range of the application and the required distance noise. In order to reach a reasonable distance noise, the pixel needs to allow modulation frequencies up to 100 MHz. In this paper, we present TCAD simulation and experimental data on demodulation contrast, impulse response time, and quantum efficiency of $10 \times 10\,\,\mu \text{m}$ pixels. We introduce a setup for impulse response measurement and we compare this to the demodulation contrast. We also discuss the optimization of the dump gate and dump diffusion. With the best pixel we measured a quantum efficiency of about 45% at 850 nm, a demodulation contrast of 47% at 80 MHz, and an impulse response time < 5 ns.

Fully Depleted Pinned Photodiode CMOS Image Sensor With Reverse Substrate Bias

A new pixel design using fully depleted pinned photodiode (PPD) in a 180-nm CMOS image sensor (CIS) process has been developed and the first experimental results from a test chip are presented. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the in-pixel p-wells have been added to the manufacturing process in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The new design shows the same electro-optical performance as the PPD pixel it is based on, and can be fully depleted without significant leakage currents. This development has the potential to greatly increase the quantum efficiency of scientific PPD CIS at near-infrared and soft X-ray wavelengths.

Dynamic Multispectral Imaging Using the Vertical Overflow Drain Structure

Multispectral imaging enables discrimination of spectra beyond the 3-D spectral space of human vision. Most multispectral systems are complex and bulky, and simpler monolithic designs usually require several pixels in order to generate one multispectral data point. Here, we use the vertical overflow drain (VOD) structure to enable monolithic multispectral imaging in a single pixel. We show that by controlling the substrate bias voltage it is possible to change the effective depth of the photodiode, thus enabling dynamic tuning of the pixel's spectral response. A small voltage change (<;5 V) is shown experimentally to reduce the red light quantum efficiency by ~ 40 %, while the blue light quantum efficiency is reduced by <;10%. Using this effect, we demonstrate an ability to discriminate between different monochromatic illumination sources with 20-nm spectral resolution in a single pixel. In addition, we present an RGB image taken using an off-the-shelf charge coupled devices with no color filters by relying solely on the VOD mechanism. Finally, we present process and device simulations suggesting that this mechanism can be implemented in any pinned photodiode pixel with a VOD barrier, including in CMOS image sensors fabricated on n-type starting material.

A quantum efficiency analytical model for complementary metal—oxide—semiconductor image pixels with a pinned photodiode structure

A quantum efficiency analytical model for complementary metal—oxide—semiconductor (CMOS) image pixels with a pinned photodiode structure is developed. The proposed model takes account of the non-uniform doping distribution in the N-type region due to the impurity compensation formed by the actual fabricating process. The characteristics of two boundary PN junctions located in the N-type region for the particular spectral response of a pinned photodiode, are quantitatively analyzed. By solving the minority carrier steady-state diffusion equations and the barrier region photocurrent density equations successively, the analytical relationship between the quantum efficiency and the corresponding parameters such as incident wavelength, N-type width, peak doping concentration, and impurity density gradient of the N-type region is established. The validity of the model is verified by the measurement results with a test chip of 160 × 160 pixels array, which provides the accurate process with a theoretical guidance for quantum efficiency design in pinned photodiode pixels.

Single Event Effects in 4T Pinned Photodiode Image Sensors

This paper describes how Single Event Effects (SEEs) produced by heavy ions disturb the operation of Pinned Photodiode (PPD) CMOS Image Sensors (CISs) in the frame of space and nuclear applications. Several CISs with 4T and 5T pinned photodiode pixels were exposed to ions with a broad Linear Energy Transfer range (3.3 to 67.7 MeV·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg). One sensor exhibited Single Event Latchups (SELs). Physical failure mechanism and latchup properties were investigated. SELs are caused by the level shifters of the addressing circuits, which create frame perturbations - following which, in some cases, parts of the addressing circuits need to be hardened. In the second part of the paper, the effects of anti-blooming capabilities on the Single Event Transient effects (SETs) are analyzed. SETs in pixels can be partially mitigated by anti-blooming through the transfer gate and/or a dedicated transistor. This work also shows that the number of pixels disturbed by SETs can be reduced by using appropriate anti-blooming techniques.

Performance Evaluation of Pinning Potential Adjustment in Two-Dimensional/Three-Dimensional Image Sensor

Standard pinned photodiode pixels with various pinning potentials are fully evaluated in two different operation modes: color image capture and depth map extraction. The diode pinning potential affects the quality of both color and depth images. On the one hand, it has an impact on the full well capacity and maximum signal-to-noise ratio (SNR) which determine the color pixel performance. On the other hand, it influences the charge transfer speed. Higher speed enables the use of higher modulation frequency which is beneficial to improve the depth accuracy in time-of-flight (TOF) measurement. Prototype pixel arrays with three types of pinning potentials have been fabricated in a 0.11-μm CMOS imaging technology by controlling the energy level of a buried implant layer. The pixels with low and high pinning potentials provide color images with 22- and 36-dB SNRs and 28 and 16 MHz of modulation frequencies in TOF operation with 40% demodulation contrast, respectively.