Pin Assignment Algorithm Research Articles

Design of Pin-Constrained General-Purpose Digital Microfluidic Biochips

Digital microfluidic biochips are being increasingly used for biotechnology applications. The number of control pins used to drive electrodes is a major contributor to the fabrication cost for disposable biochips in a highly cost-sensitive market. Most prior work on pin-constrained biochip design determines the mapping of a small number of control pins to a larger number of electrodes according to the specific schedule of fluid-handling operations and routing paths of droplets. Such designs are, therefore, specific to the bioassay application, hence sacrificing some of the flexibility associated with digital microfluidics. We propose a design method to generate an application-independent pin-assignment configuration with a minimum number of control pins. Layouts of commercial biochips and laboratory prototypes are used as case studies to evaluate the proposed design method for determining a suitable pin-assignment configuration. Compared with previous pin-assignment algorithms, the proposed method can reduce the number of control pins and facilitate the general-purpose use of digital microfluidic biochips for a wider range of applications.

Multilayer pin assignment for macro cell circuits

We present a multilayer pin (crossing point) assignment algorithm for macro cell circuits. The pin-assignment algorithm takes advantage of a multilayer chip-level global router that we recently developed. Previously reported methods also sought to combine global routing and pin assignment, but their models forced them to use inferior global routing methods. No previous pin-assignment program can handle multilayer layout in which multiple crossing points should be assigned to cell boundaries to fully minimize total routing length and area. In fact, we will show that multiple crossing-point layouts had 27% less total wire length and 9% less area, on average, than single-pin-assignment solutions.

Pin assignment with global routing for VLSI building block layout

In this paper, we will consider global routing and pin assignment in VLSI building block layout, and present an efficient algorithm which integrates global routing, pin assignment, block reshaping and positioning. The general flow of the proposed algorithm is the same as the one proposed in by Cong in 1991 [1] and consists of two main phases. The first phase is to determine not only global routes and coarse pin assignment in the same way as [1], but also shapes and positions of blocks. The second phase is to compute the final pin assignment for channels. We generalize the channel pin assignment (CPA) problem in [1], in which the CPA problem is formulated for only channels formed by two blocks, to the CPA problem for channels formed by multiple blocks. We will propose a linear time optimal channel pin assignment algorithm, which is an extension of the algorithm in [1]. Experimental results show the effectiveness of the proposed algorithm.

Performance-driven channel pin assignment algorithms

In this paper we consider two channel pin assignment problems which take circuit performance into account. The first one is the module implementation selection problem. We are given a net span bound for each critical net and each module has several possible placements of its pins. Our objective is to minimize channel density while satisfying net span constraints. We proved that this problem is NP-complete. For the case when each module has at most 2 pin placements, the problem can be transformed to the 2-SAT problem and hence is polynomial time solvable. We present a heuristic based on this algorithm to solve the general case. The second problem we consider is the module shifting problem. We are given a set of modules whose relative ordering is fixed on each side of the channel but their exact positions are not fixed. We present a polynomial time algorithm to test the feasibility of satisfying the net span constraints by shifting the modules. The algorithm is based on formulating the problem as a special integer linear programming problem which is solvable in polynomial time. We also extend our algorithms to handle multiple channels.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Three-step pin assignment algorithm for building block layout

A new pin assignment algorithm is proposed which can be use in floorplanning and building block layout to minimise the total wiring length and channel area while satisfying the minimum distance constraint among pin positions on the block boundary. This algorithm can be used in floorplanning in which block shapes are iteratively modified by the channel density obtained as a result of global routing. The proposed pin assignment algorithm occurs in three steps: approximate pin assignment, global routing and detailed pin assignment. Experimental results were obtained using MCNC placement and floorplanning benchamark examples