Physical Qubits Research Articles

Early Fault-Tolerant Quantum Computing

In recent years, research in quantum computing has largely focused on two approaches: near-term intermediate-scale quantum (NISQ) computing and future fault-tolerant quantum computing (FTQC). A growing body of research into early fault-tolerant quantum computing (EFTQC) is exploring how to utilize quantum computers during the transition between these two eras. However, without agreed-upon characterizations of this transition, it is unclear how best to utilize EFTQC architectures. We argue for the perspective that this transition period will be characterized by a law of diminishing returns in quantum error correction (QEC), where the ability of the architecture to maintain quality operations at scale determines the point of diminishing returns. Two challenges emerge from this picture: how to model this phenomenon of diminishing return of QEC as the performance of devices is continually improving and how to design algorithms to make the most use of these devices. To address these challenges, we present models for the performance of EFTQC architectures, capturing the diminishing returns of QEC. We then use these models to elucidate the regimes in which algorithms suited to such architectures are advantageous. As a concrete example, we show that for the canonical task of phase estimation, in a regime of moderate scalability and using just over one million physical qubits, the “reach” of the quantum computer can be extended (compared to the standard approach) from 90-qubit instances to over 130-qubit instances using a simple early fault-tolerant quantum algorithm, which reduces the number of operations per circuit by a factor of 100 and increases the number of circuit repetitions by a factor of 10 000. This clarifies the role that such algorithms might play in the era of limited-scalability quantum computing. Published by the American Physical Society 2024

QM-DLA: an efficient qubit mapping method based on dynamic look-ahead strategy

Quantum computing has already demonstrated great computational potential across multiple domains and has received more and more attention. However, due to the connectivity limitations of Noisy Intermediate-Scale Quantum (NISQ) devices, most of the quantum algorithms cannot be directly executed without the help of inserting SWAP gates. Nevertheless, more SWAP gates lead to a longer execution time and, inevitably, lower fidelity of the algorithm. To this end, this paper proposes an optimized qubit mapping algorithm based on a dynamic look-ahead strategy to minimize the number of SWAP gates inserted. Firstly, a heuristic algorithm is proposed based on maximizing physical qubit connectivity to generate the optimal initial qubit mapping, which reduces the need for logical qubit shifts during subsequent SWAP gate insertion. Secondly, in the form of directed acyclic graphs, we identify quantum gates that violate the constraints of physical coupling and insert SWAP gates to remap qubits, thereby overcoming the limitations of qubit interactions. Finally, the optimal SWAP gate insertion strategy is built by comparing the cost of different SWAP gate insertion strategies through a multi-window look-ahead strategy to reduce the number of SWAP gates inserted. The experimental results show that the strategy in this paper decreases the number of SWAP gate insertions and significantly reduces the depth of quantum circuits when performing qubit mapping compared with state-of-the-art methods.

Flying-cat parity checks for quantum error correction

Long range, multiqubit parity checks have applications in both quantum error correction and measurement-based entanglement generation. Such parity checks could be performed using qubit-state-dependent phase shifts on propagating pulses of light described by coherent states |α〉 of the electromagnetic field. We consider “flying-cat” parity checks based on an entangling operation that is quantum nondemolition for Schrödinger's cat states |α〉±|−α〉. This operation encodes parity information in the phase of maximally distinguishable coherent states |±α〉, which can be read out using a phase-sensitive measurement of the electromagnetic field. In contrast to many implementations, where single-qubit errors and measurement errors can be treated as independent, photon loss during flying-cat parity checks introduces errors on physical qubits at a rate that is anticorrelated with the probability for measurement errors. We analyze this trade-off for three-qubit parity checks, which are a requirement for universal fault-tolerant quantum computing with the subsystem surface code. We further show how a six-qubit entangled “tetrahedron” state can be prepared using these three-qubit parity checks. The tetrahedron state can be used as a resource for controlled quantum teleportation of a two-qubit state or as a source of shared randomness with potential applications in three-party quantum key distribution. Finally, we provide conditions for performing high-quality flying-cat parity checks in a state-of-the-art circuit QED architecture, accounting for qubit decoherence, internal cavity losses, and finite-duration pulses, in addition to transmission losses. Published by the American Physical Society 2024

Heterogeneous integration of spin-photon interfaces with a CMOS platform.

Colour centres in diamond have emerged as a leading solid-state platform for advancing quantum technologies, satisfying the DiVincenzo criteria1 and recently achieving quantum advantage in secret key distribution2. Blueprint studies3-5 indicate that general-purpose quantum computing using local quantum communication networks will require millions of physical qubits to encode thousands of logical qubits, presenting an open scalability challenge. Here we introduce a modular quantum system-on-chip (QSoC) architecture that integrates thousands of individually addressable tin-vacancy spin qubits in two-dimensional arrays of quantum microchiplets into an application-specific integrated circuit designed for cryogenic control. We demonstrate crucial fabrication steps and architectural subcomponents, including QSoC transfer by means of a 'lock-and-release' method for large-scale heterogeneous integration, high-throughput spin-qubit calibration and spectral tuning, and efficient spin state preparation and measurement. This QSoC architecture supports full connectivity for quantum memory arrays by spectral tuning across spin-photon frequency channels. Design studies building on these measurements indicate further scaling potential by means of increased qubit density, larger QSoC active regions and optical networking across QSoC modules.

Single-step parity check gate set for quantum error correction

A key requirement for an effective quantum error correction (QEC) scheme is that the physical qubits have error rates below a certain threshold. The value of this threshold depends on the details of the specific QEC scheme, and its hardware-level implementation. This is especially important with parity-check circuits, which are the fundamental building blocks of QEC codes. The standard way of constructing the parity check circuit is using a universal set of gates, namely sequential CNOT gates, single-qubit rotations and measurements. We exploit the insight that a QEC code does not require universal logic gates, but can be simplified to perform the sole task of error detection and correction. By building gates that are fundamental to QEC, we can boost the threshold and ease the experimental demands on the physical hardware. We present a rigorous formalism for constructing and verifying the error behavior of these gates, linking the physical measurement of a process matrix to the abstract error models commonly used in QEC analysis. This allows experimentalists to directly map the gates used in their systems to thresholds derived for a broad-class of QEC codes. We give an example of these new constructions using the model system of two nuclear spins, coupled to an electron spin, showing the potential benefits of redesigning fundamental gate sets using QEC primitives, rather than traditional gate sets reliant on simple single and two-qubit gates.

Fault-tolerant quantum computation using low-cost joint measurements

We introduce a new method to implement joint measurements using a 4-qubit twist defect on a rotated surface code. The proposed method enables us to perform logical S (Phase gate), T (π/8\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\pi /8$$\\end{document} gate), and H (Hadamard) with low overhead. Combined with other universal quantum gates, we can implement fault-tolerant quantum computation at the lattice surgery level beyond the gate level while saving considerable resources. We compare our method with previous methods using benchmark circuits by calculating the space and time costs. The proposed method requires additional lines of physical qubits for each encoded patch. Although it slightly increases the space cost for logical H compared to the previous work, it reduces the time cost. In addition, the proposed method decreases the space cost and time cost by introducing a 4-qubit twist defect for logical S and T. Therefore, the overall space-time cost is reduced.

Modeling the performance of early fault-tolerant quantum algorithms

Progress in fault-tolerant quantum computation (FTQC) has driven the pursuit of practical applications with (EFTQC). These devices, limited in their qubit counts and fault-tolerance capabilities, require algorithms that can accommodate some degrees of error, which are known as EFTQC algorithms. To predict the onset of early quantum advantage, a comprehensive methodology is needed to develop and analyze EFTQC algorithms, drawing insights from both the methodologies of noisy intermediate-scale quantum and traditional FTQC. To address this need, we propose such a methodology for modeling algorithm performance on EFTQC devices under varying degrees of error. As a case study, we apply our methodology to analyze the performance of randomized Fourier estimation (RFE) [Kshirsagar, Katabarwa, and Johnson, ], an EFTQC algorithm for phase estimation. We investigate the runtime performance and the fault-tolerant overhead of RFE in comparison to the traditional quantum phase estimation algorithm. Our analysis reveals that RFE achieves significant savings in physical qubit counts while having a much higher runtime upper bound. We anticipate even greater physical qubit savings when considering more realistic assumptions about the performance of EFTQC devices. By providing insights into the performance trade-offs and resource requirements of EFTQC algorithms, our work contributes to the development of practical and efficient quantum computing solutions on the path to quantum advantage. Published by the American Physical Society 2024

Probing single electrons across 300-mm spin qubit wafers

Building a fault-tolerant quantum computer will require vast numbers of physical qubits. For qubit technologies based on solid-state electronic devices1–3, integrating millions of qubits in a single processor will require device fabrication to reach a scale comparable to that of the modern complementary metal–oxide–semiconductor (CMOS) industry. Equally important, the scale of cryogenic device testing must keep pace to enable efficient device screening and to improve statistical metrics such as qubit yield and voltage variation. Spin qubits1,4,5 based on electrons in Si have shown impressive control fidelities6–9 but have historically been challenged by yield and process variation10–12. Here we present a testing process using a cryogenic 300-mm wafer prober13 to collect high-volume data on the performance of hundreds of industry-manufactured spin qubit devices at 1.6 K. This testing method provides fast feedback to enable optimization of the CMOS-compatible fabrication process, leading to high yield and low process variation. Using this system, we automate measurements of the operating point of spin qubits and investigate the transitions of single electrons across full wafers. We analyse the random variation in single-electron operating voltages and find that the optimized fabrication process leads to low levels of disorder at the 300-mm scale. Together, these results demonstrate the advances that can be achieved through the application of CMOS-industry techniques to the fabrication and measurement of spin qubit devices.

Hunting for quantum-classical crossover in condensed matter problems

The intensive pursuit for quantum advantage in terms of computational complexity has further led to a modernized crucial question of when and how will quantum computers outperform classical computers. The next milestone is undoubtedly the realization of quantum acceleration in practical problems. Here we provide a clear evidence and arguments that the primary target is likely to be condensed matter physics. Our primary contributions are summarized as follows: 1) Proposal of systematic error/runtime analysis on state-of-the-art classical algorithm based on tensor networks; 2) Dedicated and high-resolution analysis on quantum resource performed at the level of executable logical instructions; 3) Clarification of quantum-classical crosspoint for ground-state simulation to be within runtime of hours using only a few hundreds of thousand physical qubits for 2d Heisenberg and 2d Fermi-Hubbard models, assuming that logical qubits are encoded via the surface code with the physical error rate of p = 10−3. To our knowledge, we argue that condensed matter problems offer the earliest platform for demonstration of practical quantum advantage that is order-of-magnitude more feasible than ever known candidates, in terms of both qubit counts and total runtime.

High-threshold and low-overhead fault-tolerant quantum memory

The accumulation of physical errors1–3 prevents the execution of large-scale algorithms in current quantum computers. Quantum error correction4 promises a solution by encoding k logical qubits onto a larger number n of physical qubits, such that the physical errors are suppressed enough to allow running a desired computation with tolerable fidelity. Quantum error correction becomes practically realizable once the physical error rate is below a threshold value that depends on the choice of quantum code, syndrome measurement circuit and decoding algorithm5. We present an end-to-end quantum error correction protocol that implements fault-tolerant memory on the basis of a family of low-density parity-check codes6. Our approach achieves an error threshold of 0.7% for the standard circuit-based noise model, on par with the surface code7–10 that for 20 years was the leading code in terms of error threshold. The syndrome measurement cycle for a length-n code in our family requires n ancillary qubits and a depth-8 circuit with CNOT gates, qubit initializations and measurements. The required qubit connectivity is a degree-6 graph composed of two edge-disjoint planar subgraphs. In particular, we show that 12 logical qubits can be preserved for nearly 1 million syndrome cycles using 288 physical qubits in total, assuming the physical error rate of 0.1%, whereas the surface code would require nearly 3,000 physical qubits to achieve said performance. Our findings bring demonstrations of a low-overhead fault-tolerant quantum memory within the reach of near-term quantum processors.

Deep Quantum Error Correction

Quantum error correction codes (QECC) are a key component for realizing the potential of quantum computing. QECC, as its classical counterpart (ECC), enables the reduction of error rates, by distributing quantum logical information across redundant physical qubits, such that errors can be detected and corrected. In this work, we efficiently train novel end-to-end deep quantum error decoders. We resolve the quantum measurement collapse by augmenting syndrome decoding to predict an initial estimate of the system noise, which is then refined iteratively through a deep neural network. The logical error rates calculated over finite fields are directly optimized via a differentiable objective, enabling efficient decoding under the constraints imposed by the code. Finally, our architecture is extended to support faulty syndrome measurement, by efficient decoding of repeated syndrome sampling. The proposed method demonstrates the power of neural decoders for QECC by achieving state-of-the-art accuracy, outperforming for small distance topological codes, the existing end-to-end neural and classical decoders, which are often computationally prohibitive.

An elementary review on basic principles and developments of qubits for quantum computing.

An elementary review on principles of qubits and their prospects for quantum computing is provided. Due to its rapid development, quantum computing has attracted considerable attention as a core technology for the next generation and has demonstrated its potential in simulations of exotic materials, molecular structures, and theoretical computer science. To achieve fully error-corrected quantum computers, building a logical qubit from multiple physical qubits is crucial. The number of physical qubits needed depends on their error rates, making error reduction in physical qubits vital. Numerous efforts to reduce errors are ongoing in both existing and emerging quantum systems. Here, the principle and development of qubits, as well as the current status of the field, are reviewed to provide information to researchers from various fields and give insights into this promising technology.

Optimizing quantum gates towards the scale of logical qubits

A foundational assumption of quantum error correction theory is that quantum gates can be scaled to large processors without exceeding the error-threshold for fault tolerance. Two major challenges that could become fundamental roadblocks are manufacturing high-performance quantum hardware and engineering a control system that can reach its performance limits. The control challenge of scaling quantum gates from small to large processors without degrading performance often maps to non-convex, high-constraint, and time-dynamic control optimization over an exponentially expanding configuration space. Here we report on a control optimization strategy that can scalably overcome the complexity of such problems. We demonstrate it by choreographing the frequency trajectories of 68 frequency-tunable superconducting qubits to execute single- and two-qubit gates while mitigating computational errors. When combined with a comprehensive model of physical errors across our processor, the strategy suppresses physical error rates by ~3.7× compared with the case of no optimization. Furthermore, it is projected to achieve a similar performance advantage on a distance-23 surface code logical qubit with 1057 physical qubits. Our control optimization strategy solves a generic scaling challenge in a way that can be adapted to a variety of quantum operations, algorithms, and computing architectures.

Partially Fault-Tolerant Quantum Computing Architecture with Error-Corrected Clifford Gates and Space-Time Efficient Analog Rotations

Quantum computers are expected to drastically accelerate certain computing tasks versus classical computers. Noisy intermediate-scale quantum (NISQ) devices, which have tens to hundreds of noisy physical qubits, are gradually becoming available, but it is still challenging to achieve useful quantum advantages in meaningful tasks. On the other hand, full fault-tolerant quantum computing (FTQC) based on quantum error correction code remains far beyond realization due to its extremely large requirement of high-precision physical qubits. In this study, we propose a quantum computing architecture to close the gap between NISQ and FTQC architectures. Our architecture is based on erroneous arbitrary rotation gates and error-corrected Clifford gates implemented by lattice surgery. We omit the typical distillation protocol to achieve direct analog rotations and small qubit requirements, and minimize the remnant errors of the rotations by a carefully designed state injection protocol. Our estimation based on numerical simulations shows that for early-FTQC devices that consist of 104 physical qubits with physical error probability p=10−4, we can perform roughly 1.72×107 Clifford operations and 3.75×104 arbitrary rotations on 64 logical qubits. Such computations cannot be realized by the existing NISQ and FTQC architectures on the same device, as well as classical computers. We hope that our proposal and the corresponding development of quantum algorithms based on it will bring new insights into the realization of practical quantum computers in the future. Published by the American Physical Society 2024

Resource analysis and modifications of quantum computing with noisy qubits for elliptic curve discrete logarithms

We estimate the number of physical qubits and execution time by decomposing an implementation of Shor’s algorithm for elliptic curve discrete logarithms into universal gate units at the logical level when surface codes are used. We herein also present modified quantum circuits for elliptic curve discrete logarithms and compare our results with those of the original quantum circuit implementations at the physical level. Through the analysis, we show that the use of more logical qubits in quantum algorithms does not always lead to the use of more physical qubits. We assumed using rotated surface code and logical qubits with all-to-all connectivity. The number of physical qubits and execution time are expressed in terms of bit length, physical gate error rate, and probability of algorithm failure. In addition, we compare our results with the number of physical qubits and execution time of Shor’s factoring algorithm to assess the risk of attack by quantum computers in RSA and elliptic curve cryptography.

Union-find quantum decoding without union-find

The union-find decoder is a leading algorithmic approach to the correction of quantum errors on the surface code, achieving code thresholds comparable to minimum-weight perfect matching (MWPM) with amortized computational time scaling near-linearly in the number of physical qubits. This complexity is achieved via optimizations provided by the disjoint-set data structure. We demonstrate, however, that the behavior of the decoder at scale underutilizes this data structure for twofold analytic and algorithmic reasons, and that improvements and simplifications can be made to architectural designs to reduce resource overhead in practice. To reinforce this, we model the behavior of erasure clusters formed by the decoder and show that there does not exist a percolation threshold within the data structure for any mode of operation. This yields a linear-time worst-case complexity for the decoder at scale, even with a naive implementation omitting popular optimizations. Published by the American Physical Society 2024

The effects of quantum hardware properties on the performances of variational quantum learning algorithms

In-depth theoretical and practical research is nowadays being performed on variational quantum algorithms (VQAs), which have the potential to surpass traditional, classical, algorithms on a variety of problems, in physics, chemistry, biology, and optimization. Because they are hybrid quantum-classical algorithms, it takes a certain set of optimal conditions for their full potential to be exploited. For VQAs, the construction of an appropriate ansatz in particular is crucial, since it lays the ground for efficiently solving the particular problem being addressed. To prevent severe negative effects that hamper quantum computation, the substantial noise, together with the structural limitations, characteristic of currently available devices must be also taken into consideration while building the ansatz. In this work the effect of the quantum hardware structure, namely the topological properties emerging from the couplings between the physical qubits and the basis gates of the device itself, on the performances of VQAs is addressed. Specifically, it is here experimentally shown that a complex connectivity in the ansatz, albeit being beneficial for exploring wider sets of solutions, introduces an overhead of gates during the transpilation on a quantum computer that increases the overall error rate, thus undermining the quality of the training. It is hence necessary, when implementing a variation quantum learning algorithm, to find the right balance between a sufficiently parametrized ansatz and a minimal cost in terms of resources during transpilation. Moreover, the experimental finding allows to construct a heuristic metric function, which aids the decision-making process on the best possible ansatz structure to be deployed on a given quantum hardware, thus fostering a more efficient application of VQAs in realistic situations. The experiments are performed on two widely used variational algorithms, the VQE (variational quantum eigensolver) and the VQC (variational quantum classifier), both tested on two different problems, the first on the Markowitz portfolio optimization using real-world financial data, and the latter on a classification task performed on the Iris dataset.

Error-correcting codes for fermionic quantum simulation

Utilizing the framework of \mathbb{Z}_2ℤ2 lattice gauge theories in the context of Pauli stabilizer codes, we present methodologies for simulating fermions via qubit systems on a two-dimensional square lattice. We investigate the symplectic automorphisms of the Pauli module over the Laurent polynomial ring. This enables us to systematically increase the code distances of stabilizer codes while fixing the rate between encoded logical fermions and physical qubits. We identify a family of stabilizer codes suitable for fermion simulation, achieving code distances of d=2,3,4,5,6,7, allowing correction of any \lfloor \frac{d-1}{2} \rfloor⌊d−12⌋-qubit error. In contrast to the traditional code concatenation approach, our method can increase the code distances without decreasing the (fermionic) code rate. In particular, we explicitly show all stabilizers and logical operators for codes with code distances of d=3,4,5. We provide syndromes for all Pauli errors and invent a syndrome-matching algorithm to compute code distances numerically.

Qubits without qubits.

Light-based platforms for quantum computing do not require physical qubits.

QuCloud+: A Holistic Qubit Mapping Scheme for Single/Multi-programming on 2D/3D NISQ Quantum Computers

Qubit mapping for NISQ superconducting quantum computers is essential to fidelity and resource utilization. The existing qubit mapping schemes meet challenges, e.g., crosstalk, SWAP overheads, diverse device topologies, etc., leading to qubit resource underutilization and low fidelity in computing results. This article introduces QuCloud+, a new qubit mapping scheme that tackles these challenges. QuCloud+ has several new designs. (1) QuCloud+ supports single/multi-programming quantum computing on quantum chips with 2D/3D topology. (2) QuCloud+ partitions physical qubits for concurrent quantum programs with the crosstalk-aware community detection technique and further allocates qubits according to qubit degree, improving fidelity, and resource utilization. (3) QuCloud+ includes an X-SWAP mechanism that avoids SWAPs with high crosstalk errors and enables inter-program SWAPs to reduce the SWAP overheads. (4) QuCloud+ schedules concurrent quantum programs to be mapped and executed based on estimated fidelity for the best practice. Experimental results show that, compared with the existing typical multi-programming study [ 12 ], QuCloud+ achieves up to 9.03% higher fidelity and saves on the required SWAPs during mapping, reducing the number of CNOT gates inserted by 40.92%. Compared with a recent study [ 30 ] that enables post-mapping gate optimizations to further reduce gates, QuCloud+ reduces the post-mapping circuit depth by 21.91% while using a similar number of gates.