Phase Opposition Disposition Pulse Width Modulation Research Articles

Design and Performance Analysis of New Multilevel Inverter for PV System

Multilevel inverters (MLIs) have recently attracted more attention in medium-voltage and high-power applications as they can provide an effective interface with photovoltaic (PV) systems. Conventional MLIs are used to generate higher voltage levels, which improve power quality and reduce the requirement for passive filters. However, recent research has focused on designing new MLI topologies using reduced switch counts and less voltage stress. This study, as such, proposes a new nine-level symmetric MLI for PV systems with a minimum number of switches. This decrease in the number of switches reduces the voltage stress across the switches and the number of driving circuits, which lowers the complexity of the control circuit and, as a result, lowers the cost and size of the system. This article compares the proposed MLI with other topologies based on the DC sources, switches count, gate driver circuits (Ngd), total standing voltage per unit (TSVPU), cost function (CF), and components count per level (CC/L). The proposed topology is integrated with the PV system. MATLAB software is used to evaluate the performance of MLI at step change in irradiance and under variable load conditions. The total harmonic distortion (THD) of the proposed topology is reduced with the implementation of phase disposition pulse width modulation (PD-PWM). In addition, PD-PWM is compared with phase opposition disposition pulse width modulation (POD-PWM) and alternative phase opposition disposition pulse width (APOD-PWM) modulation techniques. The simulation results reveal the improved performance of the proposed topology at variable irradiance and under varying load conditions. The comparison results reveal minimum (TSVPU), CC/L, CF, and switch count compared to existing topologies. Hence, the proposed topology of MLI is cost-effective and superior in all aspects compared to other topologies. In summary, it offers overall improved performance, and thus, it is feasible for the PV system.

Performance Comparison of Five-Level Active Neutral Point Converter Based on Phase Disposition-PWM and Alternate Phase Opposition Disposition-PWM

The work in this paper presents the performance analysis of the reduced component count converter which is the 5-Level Active Neutral Point Converter (5LANPC). This 5-level converter has been configured by stacking the traditional 3-Level Neutral Point Converter with the Flying Capacitor converter. Two types of control algorithms were considered and compared to explore the performance of the 5LANPC. The first algorithm was based on the Phase-Disposition-Pulse Width Modulation (PD-PWM), while the second one was based on the Alternate Phase Opposition Disposition-Pulse Width Modulation (APOD-PWM). These algorithms are used to determine the required voltage level and according to the required level the state of the switches is selected through a simplified voltage balance algorithm. This voltage balance algorithm deals with the redundant switching states to maintain the voltages of the 5LANPC capacitors at a specified level. The comparison between these two modulation strategies was performed by simulation based on MATLAB/Simulink package. Simulation results showed compelling outcomes involving the two techniques concerning the voltage and current characteristics, as well as the equilibrium in the capacitor voltages. By comparing the simulation results, it was found that the performance of the system is relatively better using the PD-PWM strategy.

Capacitor-Voltage Self-Balance Seven-Level Inverter With Unequal Amplitude Carrier-Based APODPWM

In this article, a seven-level inverter based on bridge modular switched-capacitor circuits is presented. The inverter cannot only obtain dc-dc boosting conversion ability but also own capacitor voltage self-balance capability. Meanwhile, some of the switches can be operated under line voltage frequency, which makes the control strategy simpler and reduces the switching loss. More importantly, a new unequal amplitude carrier-based alternative phase opposition disposition pulsewidth modulation method is proposed to control the inverter, where the amplitude of the carrier wave will change based on the output voltage level. Under the proposed strategy, the inverter can output seven different voltage levels and the capacitor voltage self-balance can be realized during the switching period, the quality of the output waveforms can be improved remarkably. Last, a loss analysis within the two time-scale of switching period and 1/4 line voltage period is presented to give the loss insight. The simulation and experimental results verify the correctness and practicability of these analyses.

Switched capacitor based multi-level boost inverter for smart grid applications

To link DC power sources to an AC grid, converters are needed. Inverters are the power electronic devices, which are used for this purpose. Conventional inverters employ harmonic filters and transformers that are lossy and expensive. Multilevel inverters (MLIs) are an alternative to conventional ones, proposing reduced total harmonic distortion (THD), increased range of control, and inductor-less design. They generate a stepped waveform, with close similarity to a sine wave. Many distributed sources may be employed in a smart grid. If those sources have minimal THD, the filtering process could be reduced at the point of common coupling. This paper presents two switched capacitor based MLIs, proposing boost capability and low THD. Inverters have inherent charge balancing capability, which eliminates the need for auxiliary circuits and voltage sensors. Inverters switches are modulated using phase opposition disposition pulse-width modulation (PODPWM) method that ease the balancing of the voltage and decrease the losses of switching. Designs were verified by simulation and the output waveforms were introduced.

Carrier based PD and POD PWM Technique for MLI

This paper presents the design of gate drive circuit for controlling of multilevel inverter (MLI) with Phase Disposition (PD), Phase Opposition Disposition (POD) pulse width modulation (PWM) switching control technique.

A Voltage Balancing Scheme for Modular Multilevel Converter Based on Charge Variation in Each Cycle

This article presents a voltage balancing scheme for a modular multilevel converter (MMC) based on capacitor charge variation in each fundamental cycle. An in-depth theoretical analysis of stored charge variation for the concept is described. A new hybrid pulsewidth modulation (PWM) sequence is proposed based on a rotation strategy to achieve capacitor voltage balancing without sensing the capacitor voltages or arm currents. The rotation strategy provides the freedom of finding the best possible sequence to achieve capacitor voltage balancing. This reduces hardware, software burden and overall cost of the design implementation. The functionality and performance of the balancing strategy with new hybrid PWM sequence are carried out over wide range of modulation index (M) for three-phase five-level MMC in MATLAB/Simulink. A hardware prototype of single-phase five-level MMC is designed for experimental validation. The proposed hybrid PWM sequence is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field-programmable gate array using alternate phase opposition disposition PWM method. Simulation and experimental results are presented.

Effect of Modulation Index on THD of Reduced Switch MLI

In recent days ac drives play an important role in many industries. Most of the AC drives employ PWM technology for switching. For medium voltage high power machines two level inverter alone cannot provide required output to run machines. In this paper a novel method is proposed of Phase Opposition Disposition Pulse Width Modulation (PODPWM) signal generation for a reduced switch multilevel inverter. The experiment is carried out in MATLAB SIMULINK environment. This paper also shows the effect of modulation index (MI) on multilevel inverter.

DC Decoupling-Based Three-Phase Three-Level Transformerless PV Inverter Topology for Minimization of Leakage Current

This letter presents a three-phase three-level cascaded photovoltaic (PV) inverter configuration based on the dc decoupling strategy. The given configuration requires two additional decoupling switches for the minimization of the leakage current. The leakage current is minimized by avoiding or restricting the change in terminal voltages, during the common zero state. Further, a common zero state in all the three phases is obtained using a phase opposition disposition pulsewidth modulation technique. Once the common zero state is realized, the dc decoupling switches are used to isolate the PV source and output load. Apart from the terminal voltage, the proposed configuration also reduces the transitions in the common-mode voltage. Further, this letter also presents an analysis of the terminal voltage using the switching function concept. From the given switching function analysis, an analytical expression of the terminal voltage is derived and is used to obtain the analytical waveform, which matches with the simulation results. In addition to the terminal voltage, the leakage current waveform is also given. Fast Fourier transform spectrums of both are shown. These results are further supported by the experimental waveforms which match both simulation and analytical waveforms. Further, the proposed cascaded multilevel inverter (CMLI) is also compared with the conventional CMLI.

Performance Evaluation of Multi-carrier PWM Techniques: PD, POD and APOD

In industrial applications, modulation strategies play a significant role to provide the effective voltage generation at the outputs of inverter structures. Also, the modulation strategies are important to generate output voltages with lower harmonic distortions. For this purpose, there are several modulation techniques to produce stepped voltage waveforms by reducing harmonics for high voltage levels. Therefore, this work introduces the comparative study of multi-carrier based pulse width modulation (PWM) methods used in high power rated inverters. In this regard, phase disposition (PD), phase opposition disposition (POD) and alternative phase opposition disposition (APOD) PWM strategies are tested in five-level cascaded H-bridge inverter. The performance consequences are received for different carrier frequencies, and total harmonic distortions are evaluated for tested methods. The results show that total harmonic distortion in APOD-PWM controlled inverter is less than other methods. In addition, total harmonic distortion values are performed for frequency values, which are from 0.5 kHz to 4 kHz.

Carrier Phase-Shift PWM to Reduce Common-Mode Voltage for Three-Level T-Type NPC Inverters

Common-mode voltage (CMV) causes overvoltage stress to winding insulation and damages AC motors. CMV with high dv/dt causes leakage currents, which create noise problems for equipment installed near the converter. This study proposes a new pulse-width modulation (PWM) strategy for three-level T-type NPC inverters. This strategy substantially eliminates CMV. The principle for selecting suitable triangle carrier signals for the three-level T-type NPC is described. The proposed method can mitigate the peak value of CMV by 50% compared with the phase disposition pulse-width modulation method. Furthermore, the proposed method exhibits better harmonic spectrum and lower root mean square value for the CMV than those of the reduced-CMV method on the basis of the phase opposition disposition PWM scheme with modulation index higher than 0.5. The proposed modulation can easily be implemented using software without any additional hardware modifications. Both simulation and experimental results demonstrate that the proposed carrier phase-shift PWM method has good output waveform performance and reduces CMV.

Contour-Based Dead-Time Harmonic Analysis in a Three-Level Neutral-Point-Clamped Inverter

The term dead time refers to a prime safety factor for most power electronic converter topologies, and it is included either in the control software or in the gate/base driver hardware, depending on the application as well as the control requirements. In this paper, the authors present a comprehensive numerical analysis of dead-time effects on the output voltage of a three-level neutral-point-clamped (NPC) inverter. To incorporate the dead-time effect in the output voltage, 3-D models of three-level carrier pulse width modulation (PWM) methods are modified for two dead-time implementations. Closed-form expressions of inverter phase voltage harmonics for phase opposition disposition (POD) PWM are derived based on the double Fourier series approach and modified contour plots. The harmonic spectra from numerical evaluations, simulations, and experiments for natural sampling (NS), symmetrical regular sampling (SRS), and asymmetrical regular sampling (ARS) are compared to validate the mathematical models. In addition, the fundamental voltage with respect to the dead time and the load phase angle is presented based on analytical results and simulation.

Controlled Strategies Using DC Voltage for Asymmetric Twin Converter for a High Power STATCOM

The proposed controller can balance individual dc capacitor voltages when H-bridges run with different switching patterns and have parameter variations. It has two advantages: 1) the controller can work well in all operation modes (the capacitive mode, the inductive mode, and the standby mode) and 2) the impact of the individual dc voltage controller on the voltage quality is small. This topology suggests further improvement Here we have to using fuzzy logic controllers in the control scheme to reduce total harmonic distortion. A three phase cascaded H-bridge inverter this control method uses a discrete-time model of the system to predict the future value of the current for all voltage vectors, and selects the vector which minimizes a cost function. Analytical solutions of pulse width-modulation (PWM) strategies for multilevel inverters are used to identify that alternative phase opposition disposition PWM for diode clamped inverters produces the same harmonic performance as phase-shifted carrier PWM for cascaded inverters, and hybrid PWM for hybrid inverters, when the carrier frequencies are set to achieve the same number of inverter switch transitions over each fundamental cycle. In order to improve the performance, a phase-shifted carrier based pulse width modulation technique is used. A mathematical model of the system is derived, based on which a controller for the scheme is designed. The effectiveness of the scheme is verified through detailed simulation study. Index Terms: DC voltage regulation, fuzzy logic controllers, voltage source converter (VSC), Pulse width modulation (PWM), static compensator (STATCOM) I. Introduction The static synchronous compensator (STATCOM) is a flexible ac transmission system device, which is connected as a shunt to the power system, for generating or absorbing reactive power (5). A STATCOM works in the capacitive mode if it injects reactive power to the power system and in the inductive mode it absorbs reactive power from the power system. A multi pulse converter uses more than one voltage source converter (VSC), with common dc link, operating with nearly fundamental switching frequency, and the output of each module is connected in series through the multi pulse transformer. By adjusting the triggering pulses of different VSCs, specified total harmonic distortion (THD) of the injected current is achieved with reduced switching losses as compared to that of single-VSC-based solution. The major drawback of this scheme is the high cost and complex structure of the bulky multi pulse transformer. Multilevel converter technology is a very efficient alternative for medium voltage and high-power applications and also for other applications where high-quality voltages and currents are required (1), (2). The other commonly used multilevel topology, i.e., cascaded converter topology comprises several single-phase H-bridge/full-bridge converters, with separate dc links. The following are the two associated problems of this topology: 1) The size of the dc-link capacitor required is high because the instantaneous power involved with each module varies at twice the fundamental frequency. 2) Regulating voltage across a large number of self supported dc-link capacitors makes the controller design complex.

Phase-Shifted Carrier PWM Technique for General Cascaded Inverters

Phase-shifted carrier (PSC) pulsewidth modulation (PWM) in its conventional form is a good solution for single-phase Cascaded inverters as alternative phase opposition disposition (APOD) PWM for single-phase diode clamped inverters. PSC distributes the switching angles of APOD PWM waveform among the legs uniformly and reduces the switching frequency of each leg. This paper proposes a modified PSC technique based on partly shifted carriers for all disposition types including phase disposition (PD) which is suitable for three-phase cascaded inverters. Simulation results are also included for using carrier-based space-vector PWM (SVPWM).

Multicarrier PWM strategies for multilevel inverters

Analytical solutions of pulsewidth-modulation (PWM) strategies for multilevel inverters are used to identify that alternative phase opposition disposition PWM for diode-clamped inverters produces the same harmonic performance as phase-shifted carrier PWM for cascaded inverters, and hybrid PWM for hybrid inverters, when the carrier frequencies are set to achieve the same number of inverter switch transitions over each fundamental cycle. Using this understanding, a PWM method is then developed for cascaded and hybrid inverters to achieve the same harmonic gains as phase disposition PWM achieves for diode-clamped inverters. Theoretical and experimental results are presented in the paper.