Phase Noise Figure Of Merit Research Articles

Low <inline-formula> <tex-math notation="LaTeX">$1/f^{3}$ </tex-math> </inline-formula> Phase Noise Quadrature LC VCOs

Series-coupled quadrature LC voltage-controlled oscillators(SQVCOs) perform robustly over a wide tuning range, but have a higher $1/f^{3}$ phase noise than their single-phase counterparts. Switching transistors inject noise into the tank only once per cycle leading to an asymmetric impulse sensitivity function(ISF) and large flicker noise upconversion. Circuit topologies with additional capacitive paths from the drains of the switching transistors are proposed to make the switching transistors inject noise twice in a cycle and reduce the average ISF to nearly zero. The proposed SQVCOs have a phase noise figure of merit(FoM) close to that of a single-phase VCO for a given tank. They also eliminate mode ambiguity usually present in the coupled VCOs. The 2.4 GHz prototypes of two of the proposed SQVCOs in a 0.13 $\mu \text{m}$ CMOS process have $1/f^{3}$ phase noise corners of 400 and 150 kHz compared to 3 MHz in the conventional SQVCO. At 1 MHz/3 MHz offset, the proposed SQVCOs have measured phase noise(FoM) of −133.5/−145.1 dBc/Hz (188.2/190.2 dB) and −130/−140.2 dBc/Hz (192.5/193.2 dB) whereas the conventional SQVCO has −125.5/−137.6 dBc/Hz (180.3/183 dB). The average measured phase error over five chips is 0.9°.

An Efficient High-Power Fundamental Oscillator Above $f_{\max }/2$ : A Systematic Design

A novel approach to design efficient high-output-power fundamental oscillators beyond $f_{\max }/2$ of the employed process is presented. The idea is to shape and maximize the unilateral power gain ( $U$ ) of the network at the desired frequency using optimum passive internal and external feedback networks. The proposed technique significantly improves the output power and dc-to-RF efficiency of the oscillator. To show the feasibility of this novel approach, a 175 GHz fundamental oscillator is designed in a 130 nm SiGe BiCMOS process ( $f_{\max }\simeq ~280$ GHz), which achieves a measured dc-to-RF efficiency of 11.7% that is markedly higher than all reported oscillators above $f_{\max }/3$ of their active device. Measurements show that the designed oscillator generates a peak power of 3 mW (4.8 dBm) with a phase noise figure of merit (FoM) of −195.4 dBc/Hz at 1 MHz offset frequency, which is the highest phase noise FoM among all reported CMOS/BiCMOS millimeter-wave and terahertz oscillators. The proposed method considers the possible process, voltage, temperature variations as well as modeling errors of the passive components in the design stage.

Design of low power low phase noise negative resistance Ku‐band VCO using planar resonator pair

ABSTRACTNew negative resistance voltage‐controlled oscillator (VCO) at Ku‐band is designed. The proposed topology uses packaged NPN Silicon Germanium RF transistor and two parallel resonator structures connected to the device emitters. Novel active open ended planar structure is proposed as a resonator for the VCO. Resonator is analyzed in terms of required reflection coefficient and input impedance. Resonator's quality factor varies in between 159 and 235 as a function of tuning voltage. VCO microwave IC is fabricated on TMM10i soft substrate with 17.5μm Cr‐Cu‐Au metallization process. VCO can be tuned for 180MHz by varying resonators’ varactors from 0 to 22 V. Measured output power remains in between 4.2 and 8.06 dBm for the entire tuning range. Measured phase noise is −145 dBc/Hz at 1 MHz offset with 8 V tuning voltage. Normalized phase noise figure of merit for the VCO is −214.4 dBc/Hz. The circuit has low power consumption of 25.5 mW and high DC to RF conversion efficiency (ηDC‐RF). © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1938–1941, 2015

Low voltage low-phase-noise SB-QLCO using second harmonics coupling technique

A switched biasing quadrature oscillator with LC tanks (SB-QLCO) is proposed to achieve low voltage and low phase noise. In this work, coupling devices, capacitors, don’t contributes any noise and this second harmonics coupling technique leads to low voltage. The proposed QLCO was simulated in 0.18 μm CMOS process. Simulating results showed a phase noise of −126 dBc/Hz at an offset of 1 MHz and a phasenoise figure of merit of 193 dB while consuming 6 mA from a 0.8 V power supply.

Low Phase Noise GaN HEMT Oscillators With Excellent Figures of Merit

This letter presents guidelines for the design of low phase noise oscillators in GaN high electron mobility transistor (HEMT) technology. The design starts from bias-dependent low-frequency (LF) noise measurements. Oscillator topology and bias point are then chosen for operation in regions where LF noise is low. The best LF noise properties are obtained for low drain voltage and current. Thus, the low phase noise can be achieved at low dc power which also means that power normalized phase noise figure of merit (FOM) will be good.

Oscillator with High Harmonic Suppression Using Split Quarterwave Microstrip Resonator

This letter presents a new type of resonator, namely, the split quarterwave microstrip resonator (SQMR), to improve the poor harmonic suppression and low Q-factors in conventional quarterwave microstrip resonators. An oscillator incorporating the proposed SQMR is designed, fabricated, and tested to demonstrate that, not only the second harmonic suppression, but also the phase noise of the oscillator can be improved. The oscillator with the SQMR shows improved second harmonic suppression of –74.59 dBc and phase noise figure of merit of –169.77 dBc/Hz at 1 MHz offset.

A 66 $\mu$W 86 ppm$/^{\circ}$C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM

This paper presents the design of a new Wienbridge topology. Its phase noise performance, low temperature dependency and low power consumption make it suitable for use in wireless sensor nodes and time-based sensor readout circuitry. The noise as well as temperature behavior of the oscillator is explained using extensive calculations. Measurements on 7 samples of the same batch show a temperature stability of 86 ppm/ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C and a measured spread of 0.9% at an oscillation frequency of 6 MHz. The circuit consumes 66 muW and is realized in a 65 nm technology measuring 150 mum by 200 mum. The measured phase noise figure of merit is 172 dB at a frequency offset of 100 kHz.

A Magnetically Tuned Quadrature Oscillator

Continuous frequency tuning by control of the magnetic field of a transformer - capacitor tank, in a selective oscillator, is explored in this work. A quadrature generator is built connecting two identical transformer - capacitor oscillator cells in a feedback loop. The topology itself assures the currents in the transformer windings are aligned in phase, while their relative amplitude determines, via magnetic coupling, oscillators' tank reactance, i.e., oscillation frequency. This paper introduces the idea, analyzes oscillation amplitude, frequency tuning band, phase noise, and phase accuracy, and discusses design and experiments. Prototypes, realized in 65 nm CMOS, employing MOS varactors to further extend operation bandwidth, show the following performances: 3.2 GHz and 7.3 GHz minimum and maximum oscillation frequency, respectively. Phase noise figure of merit of 176.5 dB at 3.2 GHz and 170.5 dB at 6.4 GHz is observed, with 24 mW maximum power consumption and 1.5 maximum deviation from quadrature.

4.9-GHz low-phase-noise transformer-based superharmonic-coupled GaInP/GaAs HBT QVCO

The low-phase-noise GaInP/GaAs heterojunction bipolar transistor (HBT) quadrature voltage controlled oscillator (QVCO) using transformer-based superharmonic coupling topology is demonstrated for the first time. The fully integrated QVCO at 4.87GHz has phase noise of -131dBc/Hz at 1-MHz offset frequency, output power of -4dBm and the figure of merit (FOM) -198dBc/Hz. The state-of-the-art phase noise FOM is attributed to the superior GaInP/GaAs HBT low-frequency device noise and the high quality transformer formed on the GaAs semi-insulating substrate.