Phase Noise Of Phase-locked Loop Research Articles

A D-Band Joint Radar-Communication CMOS Transceiver

A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band joint radar-communication complementary metal–oxide–semiconductor (CMOS) transceiver featuring a dual-function mode multiplexer, a power-combining PA with high output power, a current choking high-gain mixer, a two-point modulation (TPM) frequency-modulated continuous-wave (FMCW) digital phase-locked loop (PLL) with a dual-core DCO, and a wideband I/Q local oscillator (LO) generator is implemented in 28-nm CMOS technology. In the radar mode, the RF front end demonstrates 46-GHz bandwidth (BW), and the on-chip PLL/LO generated FMCW chirp achieves a BW of 30 GHz and a slope of 30 GHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu \text{s}$ </tex-math></inline-formula> . In the communication mode, the transceiver including the analog baseband realizes 20-GHz BW, and the image rejection ratio (IRR) is better than 40 dB. The measured transmitter (TX) saturated output power is 13 dBm, and the output 1-dB compression point (OP1dB) is 8.3 dBm. The measured typical PLL phase noise is −111.3 dBc/Hz at a 1-MHz offset from an 11.69-GHz carrier frequency. The TX-to-RX over-the-air (OTA) modulation–demodulation measurement with QPSK and 16-QAM signals shows the error vector magnitude (EVM) of −16.5 and −19.7 dB, respectively.

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL

This article presents a wide input-range delay chain based time amplifier (TA) and its application to a 6.5-GHz digital fractional- N phase-locked loop (PLL). The TA includes a delay-averaging linearity enhancement technique and the PLL is based on an improved dual-mode ring oscillator (DMRO) delta-sigma (ΔΣ) frequency-to-digital converter (FDC). The TA mitigates contributions to the PLL's phase noise from DMRO flicker noise, which would otherwise degrade the PLL's in-band phase noise, and from ΔΣ FDC quantization error, which would otherwise degrade the PLL's phase noise at high bandwidth settings. This paper also presents a delay-free asynchronous DMRO phase sampling scheme, and the first experimental demonstration of a recently-proposed ΔΣ FDC digital gain calibration technique. The TA-assisted PLL achieves a random jitter of 145 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , a total jitter that ranges from 151 to 270 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> as a result of fractional spurs, and a worst-case fractional spur of -49 dBc without requiring nonlinearity calibration.

Impact of VCO and PLL Phase Noise on Distributed Beamforming Arrays With Periodic Synchronization

Distributed beamforming between separate wireless nodes in a distributed antenna array requires significant coordination of the relative electrical states of the systems to achieve and maintain a phase-coherent state. A principal factor impacting distributed phase coherence is the relative stability of the local oscillators on each node. Ensuring a coherent state requires the distribution of a reference frequency such that all nodes are operating on the same basis frequency. To support distributed beamforming, the reference frequency must furthermore be distributed wirelessly, typically using a phase-locked loop (PLL) on the secondary nodes. In large arrays, the wireless link used for frequency distribution will have limited capacity, necessitating intermittent updates during which the oscillators are locked, and between which their frequencies will drift. The stability of the oscillator therefore plays an important role in the overall performance relative to the update time. In this paper, we discuss the sources of phase noise generated by the reference oscillator and the PLL, and analyze the impacts of phase noise and update interval on distributed beamforming performance. We provide a framework for analyzing distributed beamforming performance from oscillator and PLL parameters in general, and we analyze beamforming performance for two specific cases using nominal high-stability and low-stability voltage-controlled oscillators, with a parametric comparison between their impact on beamforming performance.

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs

A fractional-N phase-locked loop (PLL) with four kinds of delta-sigma modulators (DSMs), is implemented to analyze and compare PLL phase noise and fractional spur performances among different DSMs, including 4th- and 5th-order single-loop (SL) and 3rd- and 4th-order multi-stage noise-shaping (MASH) ones. SL-DSMs with fewer output levels resulting in smaller instantaneous phase error, achieve better phase noise. MASH DSMs with wider quantization levels having more efficient randomization and dithering effects, generate less fractional spur. Experimental results show that in-band and out-of-band fractional spurs of MASH DSM are 10.5 and 5.8dB better than those of SL-DSM, respectively, while out-of-band phase noise of SL-DSM is 4.5dB lower than that of MASH DSM, with the same order. The fractional-N PLL is fabricated in 180nm CMOS with a 1.8V supply voltage and power consumption of approximately 23mW.

A 93.4–104.8-GHz 57-mW Fractional-${N}$ Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology

A fully integrated 93.4–104.8-GHz 57-mW fractional- ${N}$ cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional- ${N}$ PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm2. The measured phase noise of QVCO and PLL is −113.26 and −106.63 dBc/Hz at 10-MHz offset, respectively. The FOM and FOMT of the QVCO at 10-MHz offset are −178.4 and −180.0 dBc/Hz, respectively. The frequency resolution of the 100-GHz output is less than 3.6 kHz.

A Study of Phase Noise and Frequency Error of a Fractional-N PLL in the Course of FMCW Chirp Generation

This paper presents the theoretical and experimental results on the phase noise spectrum and the rms frequency error of a fractional-N phase-locked loop (PLL) under frequency-modulated continuous-wave (FMCW) chirp generation. The phase noise spectrum under modulation is analytically calculated for a second-order charge pump PLL with a feedback divider ratio linearly changing over time. This is followed by an analysis of the steady-state rms frequency error of the output frequency after PLL settling is achieved during chirp generation. A fractional-N PLL with integrated frequency ramp generator is presented. Phase noise and jitter measurements on the PLL under modulation are performed at the output of the programmable feedback divider. The resulting low-frequency rms jitter is reduced by about 9dB with doubling the charge pump current, and reduced by about 6dB with halving the ramp slope. The rms frequency error under FMCW modulation is measured at the modulated voltage-controlled oscillator output. The dependence of the frequency error on the loop filter capacitance for various ramp slopes is given. A frequency error of 112kHz is achieved with a ramp slope of 1.28GHz/80 μs at a carrier frequency of 62GHz. The noise measurements are in good agreement with the developed phase noise model. A programmable loop filter capacitance is suggested to accommodate the static phase offset and the resulting noise performance to the ramp slope.

Phase Noise and Frequency Stability of the Red-Pitaya Internal PLL.

In field-programmable gate array platforms, the main clock is generally a low-cost quartz oscillator whose stability is of the order of 10-9 to 10-10 in the short term and 10-7 to 10-8 in the medium term, with the uncertainty of tens of ppm. Better stability is achieved by feeding an external reference into the internal phase-locked loop (PLL). We report the noise characterization of the internal PLL of Red-Pitaya platform, an open-source embedded system architected around the Zynq 7010 System on Chip, with analog-to-digital and digital-to-analog converters. Our experiments show that, providing an external 10-MHz reference, the PLL exhibits a residual frequency stability of 1.2×10-12 at 1 s and 1.3×10-15 at 4000 s, Allan deviation in 5-Hz bandwidth. These results help to predict the PLL stability as a function of frequency and power of the external reference, and provide guidelines for the design of precision instrumentation, chiefly intended for time and frequency metrology.

A High-Resolution 2-GHz Fractional-N PLL With Crystal Oscillator PVT-Insensitive Feedback Control

This letter presents a 2-GHz fractional-N phase-locked loop (PLL) with a high-precision delta–sigma digital-to-analog converter (DAC) to overcome the frequency deviation of a crystal oscillator due to manufacturing process, supply voltage, and temperature (PVT). The delta–sigma DAC with high power efficiency and linearity consists of a second-order delta–sigma modulator, a finite impulse response filter, and a low-pass filter. With the proposed PLL architecture, the frequency resolution can be lower than a few thousands of pulse per minute. The PLL is implemented in a 0.13- $\mu \text{m}$ 1P6M CMOS process. With temperature from −40 °C to 80 °C, the measured results of 15 chips show that the frequency deviation of output frequency in PVT decreases from 1 to 0.002 ppm. The phase noise of PLLs is less than −126 dBc/Hz at 1-MHz offset at a carrier frequency of 1.99 GHz. The rms period jitter is below 1 ps at 1.99 GHz, while consuming a total power of no more than 10 mW.

Linear CMOS $LC$ -VCO Based on Triple-Coupled Inductors and Its Application to 40-GHz Phase-Locked Loop

A linear CMOS $LC$ voltage-controlled oscillator (VCO) utilizing triple-coupled inductors and a 40-GHz integer-N phase-locked loop (PLL) are fabricated in a standard 90-nm CMOS process. The VCO utilizes triple-coupled inductors to couple varactor pairs, which compensate each other to linearize the VCO gain. The triple-coupled $LC$ tank is theoretically analyzed using equivalent circuit models. With the triple-coupled inductors, there is no need for tuning-voltage shifting circuits or dc-block capacitors, suitable for high-performance millimeter-wave (mm-wave) VCO design. A 40-GHz PLL has also been design and built around this linear $LC$ -VCO to demonstrate a stable PLL with small loop bandwidth variations. The measured tuning bandwidth, phase noise, and figure of merit (FOM $_{T}$ ) of the linear VCO is 15.8%, −100.7 dBc/Hz at 1-MHz offset, and −181.8 dBc/Hz, respectively. Utilizing the linear VCO, the experimental PLL is stably locked from 38.61 to 44.55 GHz. The PLL without output buffer consumes 76 mW from 1.5/1.0 V supplies. The measured in-band and out-band phase noise of the 40-GHz PLL are −81 dBc/Hz at 100-kHz offset, and −114.5 dBc/Hz at 10-MHz offset, respectively. Thanks to the proposed linearization method, the VCO gain shows very small variations, compared with reported works. The implemented PLL demonstrates good stabilities with small loop bandwidth variations across the operation frequency range.

A 6.6 mW 1.25–2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO

A wide tuning range low phase noise phase-locked loop (PLL) frequency synthesizer based on Class-C voltage-controlled oscillator (VCO) for IEEE 802.11ah is presented. Feedback loop technique is adopted to provide dynamic gate bias to the core transistors of the Class-C VCO, guaranteeing robust start-up against process, voltage and temperature (PVT) variations. Automatic frequency control (AFC) algorithm with tail bias switching scheme is proposed to guarantee start-up condition and maintain optimum oscillation amplitude across the whole tuning range, avoiding the deterioration of figure-of-merit (FoM). Implemented in 65-nm CMOS, the presented frequency synthesizer prototype achieves a tuning range of 57%, from 1.25GHz to 2.25GHz. Drawing 5.5mA current from a 1.2-V power supply, the prototype demonstrates −127.8 dBc/Hz phase noise at 1-MHz offset and −94.6 dBc/Hz in-band phase noise from a carrier of 1.536GHz. With the proposed dynamic gate bias technique and AFC-assisted tail bias switching scheme, the wide tuning range Class-C VCO exhibits a peak FoM of 187.5 dBc/Hz, with only 2.5dB variation across the whole tuning range.

SPD를 이용한 2.4 GHz PLL의 위상잡음 분석

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

A –90 dBm Sensitivity Wireless Transceiver Using VCO-PA-LNA-Switch-Modulator Co-Design for Low Power Insect-Based Wireless Sensor Networks

This paper presents a wireless transceiver intended for insect-based wireless sensor networks (WSNs). The transceiver utilizes several design techniques developed to meet the challenging low power and low size requirements in insect-based WSNs. The techniques include current reuse in the voltage-controlled oscillator (VCO) and power amplifier (PA), fast PLL on/off switching for low-power on/off keying (OOK) modulation, and switching between transmit and receive (TX/RX) modes without an off-chip switch. Also, the VCO, PA, low noise amplifier (LNA), OOK modulator, and TX/RX switch are co-designed and integrated into a single block to reduce the system complexity significantly. The transceiver is designed and fabricated in a 0.13-μm CMOS process. The transmitter provides an output power in the range of -30 dBm to -4.4 dBm while consuming an average power of 1.2 mW to 4.5 mW. The phase locked-loop (PLL) does not use a high-Q external resonator, and its phase noise depends on the PA output power because of the current reuse in the VCO and PA. The PLL phase noise at 1 MHz offset at 2.4 GHz varies from -103.3 dBc/Hz to -116.7 dBc/Hz. The receiver achieves a sensitivity of -90 dBm at 1 Mbps data rate for a BER = 0.1%. An example wireless sensor node design utilizing the proposed wireless transceiver achieves a modest weight of 1 gram, and a small form factor of 12.5 mm × 12.5 mm.

Effects of Radio Front-end PLL Phase Noise on GNSS Baseband Correlation

This article presents a study of Global Navigation Satellite System (GNSS) receiver correlation performance in the presence of phase noise (PN) originating from the radio front-end's phase-locked loop (PLL). Various constituent PLL sub-blocks, such as the reference oscillator (RO), phase and frequency detector (PFD), voltage controlled oscillator (VCO), loop filter and frequency dividers contribute to the overall PN of the PLL. The PLL phase noise modeling is covered in detail. Correlation performance of GNSS baseband tracking loops is then calculated as a function of several PLL design parameters, such as the VCO thermal PN, loop filter bandwidth (BW), frequency division ratio (FDR), and the receiver correlator's pre-detection integration times (PIT). The effects of these parameters on the signal to noise ratio (SNR) of the correlation product are described and simulated. Based on the results of these simulations, we present guidelines for radio front-end PLL circuit design in order to maintain a minimum baseband correlation performance within the GNSS receiver. Copyright © 2014 Institute of Navigation.

A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing

A low-phase-noise integer-N phase-locked loop (PLL) is attractive in many applications, such as clock generation and analog-to-digital conversion. The sub-harmonically injection-locked technique [1–3], sub-sampling technique [4], and the multiplying delay-locked loop (MDLL) [5–8] can significantly improve the phase noise of an integer-N PLL. In the sub-harmonically injection-locked technique, to inject a low-frequency reference clock into a high-frequency voltage-controlled oscillator (VCO), the injection timing should be tightly controlled [2–3]. If the injection timing varies due to process variation, it may cause a large reference spur or even cause the PLL to fails to lock [3]. In [1], a sub-harmonically injection-locked PLL (SILPLL) adopts a sub-sampling phase-detector (PD) [4] to automatically align the phase between the injection pulse and a VCO. However, a sub-sampling PD has a small capture range and a low bandwidth. The high-frequency non-linear effects of a sub-sampling PD may degrade the accuracy and limit the maximum speed of a VCO. In addition, a frequency-locked loop is needed for a sub-sampling PD. In [3], a delay line is manually adjusted to achieve the correct injection timing. However, the delay line is sensitive to process variations. Thus, the injection timing should be calibrated.

Optimization of a 61.44 GHz BiCMOS HBT integrated PLL for ultra-fast settling time

The design of a 61.44 GHz integrated Phase-locked loop (PLL) on a 180 GHz BiCMOS technology is presented. The PLL was optimized for a very fast settling time of 4 µs as required by the system specifications. Because the receiver is using a carrier recovery circuit that can follow the slow changes of the carrier such as phase noise, the sensitivity of the bit error rate to phase noise at the receiver end is very low. As a result, to achieve the required dynamic behavior, the phase noise performance could be sacrificed and the loop bandwidth was increased until the needed settling time was achieved, while taking the suppression of the reference spurs into consideration. Capacitor multiplication was used to enable the integration of the loop filter (LF) on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. In addition, a very close matching between the measured and simulated phase noise of the system was achieved. The PLL consumes a power of 200 mW from 2 and 3 V supply voltages, while delivering a differential output power of −7 dBm, sufficient to drive the following I/Q modulator without additional amplification.

Analysis of PLL Phase Noise Effect for High Data-rate Underwater Communications

High data-rate underwater communications is demanded. This demand imposes stringent requirements on underwater communication equipment of phase-locked-loop (PLL). Phase noise in PLL is unwanted and unavoidable. In this paper, we investigate the PLL phase noise effect on high order QAM for underwater communication systems. The phase noise model using power spectral density is adopted for performance evaluation. The phase noise components considered in PLL are reference oscillator, voltage controlled oscillator (VCO), filter and divider. The filters in PLL noise are assumed to be second order active and passive low pass filters. Through simulation, we analyze the phase noise characteristics of the four components and then investigate the performance improvement factor of each component. Consequently, we derive specifications of VCO, phase detector, divider to meet performance requirement of high data-rate communication using QAM under phase noise influence.

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop (PLL) design for low voltage (0.8 V) applications is presented. The voltage controlled oscillator (VCO) operates from a 0.5 V voltage supply, while the other blocks operate from a 0.8 V supply. A differential NMOS-only topology is adopted for the oscillator, a modified precharge topology is applied in the phase-frequency detector (PFD), and a new feedback structure is utilized in the charge pump (CP) for ultra-low voltage applications. The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power. In addition, several novel design techniques, such as removing the tail current source, are demonstrated to cut down the phase noise. Implemented in the SMIC 0.13 μm RF CMOS process and operated at 0.8 V supply voltage, the PLL measures a phase noise of-112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166-3.383 GHz. The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply. The occupied chip area of the PFD and CP is 100 × 100 μm2. The chip occupies 0.63 mm2, and draws less than 6.54 mW from a 0.8 V supply.

A multiple-pass ring oscillator based dual-loop phase-locked loop

A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of –99 dBc/Hz @ 1 MHz offset from a 5.5 GHz carrier.

Write pulse Generator for 16x DVD recording with symmetric CMOS inverter ring oscillator

This paper reports the design and measurement results of a write pulse generator IC for rewritable CD and DVD disk drives implemented in a standard digital 0.35 /spl mu/m CMOS technology. The chip is the interface between a processor and a laser driver. It provides accurate timing signals to the laser driver via a four-level differential current interface. Transitions between current levels are programmable with 149 ps resolution at a data rate of 420 Mb/s, corresponding to 16x DVD write speed. The chip includes a digital core managing the different write strategies, a CMOS serial interface to the processor for programming, a low power, low phase noise, 64-phase ring voltage-controlled oscillator (VCO) based on CMOS inverters, a phase-locked loop (PLL) locking the VCO to the system clock, and a current interface to the laser driver. The PLL phase noise is -144 dBc/Hz at 10 MHz offset from the 105 MHz carrier. At this frequency, the rms jitter is 1.1 ps with 0.8 mA VCO core supply current. The chip is fully ESD protected.