Performance Of Phase Change Memory Research Articles

A-C/GeTe superlattices: Effect of interfacial impedance adaptation modeling on the thermal properties

Recently, nanostructuration has been proposed to improve the performance of phase change memories. This is the case of superlattices composed of amorphous carbon and crystalline germanium telluride, which we have investigated by molecular dynamics. For this, a modified Stillinger–Weber potential is adapted to reproduce their stiffness contrast/impedance ratio. In order to study the effect of the interface interaction, two sets of parameters are used to model the interfaces with different interactions between the two materials using the properties of the softer material or the average properties between the two creating an adaptation of impedance across the layers. The effects of interface roughness and carbon diffusion at grain boundaries are studied. Using equilibrium molecular dynamics as well as the propagation of wave-packets, we show first that without impedance adaptation, the anisotropy is high, and the roughness has a marked impact on the properties. However, the introduction of impedance adaptation destroys those effects on the thermal conductivity. Finally, we show that the periodic texturing of the interface increases the transmission of in-plane transverse phonons.

Unveiling the Effect of Superlattice Interfaces and Intermixing on Phase Change Memory Performance

Superlattice (SL) phase change materials have shown promise to reduce the switching current and resistance drift of phase change memory (PCM). However, the effects of internal SL interfaces and intermixing on PCM performance remain unexplored, although these are essential to understand and ensure reliable memory operation. Here, using nanometer-thin layers of Ge2Sb2Te5 and Sb2Te3 in SL-PCM, we uncover that both switching current density (Jreset) and resistance drift coefficient (v) decrease as the SL period thickness is reduced (i.e., higher interface density); however, interface intermixing within the SL increases both. The signatures of distinct versus intermixed interfaces also show up in transmission electron microscopy, X-ray diffraction, and thermal conductivity measurements of our SL films. Combining the lessons learned, we simultaneously achieve low Jreset ≈ 3-4 MA/cm2 and ultralow v ≈ 0.002 in mushroom-cell SL-PCM with ∼110 nm bottom contact diameter, thus advancing SL-PCM technology for high-density storage and neuromorphic applications.

Pt Modified Sb2Te3 Alloy Ensuring High-Performance Phase Change Memory.

Phase change memory (PCM), due to the advantages in capacity and endurance, has the opportunity to become the next generation of general−purpose memory. However, operation speed and data retention are still bottlenecks for PCM development. The most direct way to solve this problem is to find a material with high speed and good thermal stability. In this paper, platinum doping is proposed to improve performance. The 10-year data retention temperature of the doped material is up to 104 °C; the device achieves an operation speed of 6 ns and more than 3 × 105 operation cycles. An excellent performance was derived from the reduced grain size (10 nm) and the smaller density change rate (4.76%), which are less than those of Ge2Sb2Te5 (GST) and Sb2Te3. Hence, platinum doping is an effective approach to improve the performance of PCM and provide both good thermal stability and high operation speed.

Enhanced performance of phase change memory by grain size reduction

Phase change memory based on Ta-GST exhibits superior thermal stability and reliability, so it is expected to be used in high-temperature applications.

WN coating of TiN electrode to improve the reliability of phase change memory

The heating electrode contact (HEC), as the key part for collecting current and transferring heat in phase change memory (PCM), tends to be unevenly oxidized by the external SiO2 coating layer during manufacturing and fatigue, resulting in negative effects on the performance of PCM. In this paper, WN film is used as the protective layer to avoid oxidation of TiN HEC. The RESET/SET current of PCM cells is reduced because of the oxygen barrier and heat preservation effect of WN film. In the endurance test of HEC, the cycle times of TiN electrode double-coated by WN can reach 1012, which is significantly higher than the electrode double-coated by SiO2. Besides, the endurance characteristics of PCM cells with this new structure of HEC are proved to be better.

Sputter‐grown GeTe/Sb 2 Te 3 superlattice interfacial phase change memory for low power and multi‐level‐cell operation

The multi-level feature of GeTe/Sb2Te3 interfacial phase change memory was achieved by applying a designed voltage-based pulse. It stably demonstrated five multi-level states without interference for 90 cycles by varying the pulse width. GeTe/Sb2Te3 interfacial phase change memory demonstrated retention time of > 1.0 × 103 s, presenting the significantly low drift coefficient (ν) of < 0.009, indicating no resistivity drift due to the structure relaxation of glass. In addition, the reset energy consumption of GeTe/Sb2Te3 interfacial phase change memory was reduced by more than 85% compared to conventional Ge2Sb2Te5 phase change memory at each bottom electrode contact size. Multi-level-cell operation mechanism and gradual increase in conductance value of GeTe/Sb2Te3 interfacial phase change memory was explained by a partial resistance transition model where phase transition occurred partially in all layers. The result of the GeTe/Sb2Te3 interfacial phase change memory performance is expected to bring great advantages to the next-generation storage class memory industry that requires low energy and high density.

Investigation of the effect of blade electrode width on performance of phase change memory

The blade bottom electrode contact (BEC) can significantly reduce the programming current of the phase change memory (PCM) and achieve low power consumption compared with the typical T-shaped PCM cell. The method of controlling the electrode width by controlling the thickness of the deposited layer can make the size break through the limit of photolithography. This paper proves that the RESET programming current and power consumption of the PCM decrease linearly with the decrease of the blade BEC width, and builds a theoretical model to verify it by simulating the distribution internal temperature field. Based on the above research, the cell life of PCM with different electrode widths was tested, and it was proved that the endurance of PCM increased with the decrease of the width of the blade electrode, caused by the lower power consumption of the narrower electrode.

Chalcogenide Materials Engineering for Phase‐Change Memory and Future Electronics Applications: From Sb–Te to Bi–Te

Chalcogenide materials play essential roles in modern nonvolatile memory technology in the form of both phase‐change memory (PCM) and selector devices. Herein, Bi–Te binary alloys are explored as an alternative candidate for superlattice (SL) or interfacial PCM (iPCM). GeTe/Bi4Te3 (GT/BT) SL exhibits similar structural features to conventional GeTe/Sb2Te3 (GT/ST) SL, such as highly oriented crystal grains and intermixing. Furthermore, preliminary device measurements show that Ge–Bi–Te (GBT) SL switches in a similar manner to conventional Ge–Sb–Te (GST), suggesting that they may be a promising candidate for memory applications. In addition, Bi2Te3/Sb2Te3 (BT/ST) heterostructure films have been successfully fabricated and show clear interface stacking at the atomic level. Although the BT/ST heterostructure is ostensibly a p–n junction, rectifying behavior is not observed in current (I)–voltage (V) measurements due to the existence of a large number of carriers in both layers. Finally, density functional theory (DFT)‐based simulations suggest that an ideal BT/ST heterostructure may possess intriguing topological properties that can enable novel functional devices. The Bi–Te binary alloys offer promising potential for optimizing PCM performance as well as for the realization of novel functional electronic devices.

Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency, and Performance Enhancement

With the scaling limitations and increasing leakage power of the existing charge-based memories, next-generation memory technologies to overcome the issues are in development. Among the various emerging memories, phase change memory (PCM) is considered as a promising candidate due to its scalability potential and negligible leakage power. For enhanced storage density, the multilevel cell (MLC) operation has been proposed for PCM. This, however, comes at cost of poor reliability, write energy increase and performance degradation. Unlike DRAM, the MLC PCM has a much higher soft error rate due to the resistance drift phenomenon. Error correction code (ECC) schemes can be utilized to improve the MLC PCM reliability, however, this would lead to a lower storage density and an increase in write energy and latency. The iterative programming required for the MLC PCM also degrades its energy efficiency and performance. This paper introduces a simple yet effective encoding scheme to mitigate the problems of the MLC PCM. By using a simple XOR-based encoding, the proposed architecture minimizes the most drift-prone state in the data. The method divides the original data into several encoding blocks and analyzes initial pattern frequencies for each 2-bit pattern. Based on the initial pattern frequencies, the inputs for the XOR encoding are selected that result in minimal frequency of the drift-prone state. This considerably enhances the MLC PCM reliability, leading to a high storage density with a reduced ECC overhead. The energy efficiency and performance are also improved due to reduction in iterative current pulses and ECC overhead. The simulation results show a reduction of about $10^{5}$ X in soft error rate. The improvements in energy efficiency and performance over the conventional 4-level cell (4LC) PCM are 11.5% and 31.9%, respectively.

Improving the performance of phase-change memory by grain refinement

Many experiments have shown that three-dimensional-confined grain refinement (GR) textures in phase-change memory reduce power consumption and improve endurance performance. However, a lack of knowledge on the GR mechanisms and their influence on device performances challenges designs that concurrently enhance the comprehensive device performances using the same impurity-doped strategy. Here, we experimentally observe dramatic GR in carbon-doped Ge2Sb2Te5 (GST), which also presents reduced power consumption and enhanced endurance performances. We provide low power consumption evidence that thermal conductivity controls the thermal transport heat loss and is proportional to the size of nanoscale grains because the boundary severely scatters phonons. Our simulations indicate that the short carbon chains in the boundary interlace with each other and trend to form trialkyl carbon atoms that constitute the basic local environment of graphene. The stable sheet consists of aggregated carbon, which is even stable above the melting temperature of GST and acts as a second-phase drag to refine the grain size. The enhanced endurance is explained by the restricted migration from the stable carbon sheet, which is verified by the greatly reduced diffusion coefficient of the host atoms in the boundary because of the less shielding effect from the core electrons in carbon and strong bonds formed between host and carbon atoms. Our findings show that the reduced power consumption and enhanced endurance from GR engineering are feasible in phase-change memory, which has been largely overlooked.

Structural, vibrational and electronic properties in the glass-crystal transition of thin films Sb70Te30 doped with Sn

Antimony-telluride based phase-change materials doped with Sn have been proposed to be ideal materials for improving the performance of phase-change memories. It is well known that Sb70Te30 thin films show a sharp fall in the electrical resistance in a narrow temperature range when heating. Therefore, it is interesting to study the effect of adding Sn into this composition. In this work, undoped and Sn-doped Sb–Te thin films of composition Snx[Sb0.70Te0.30]100-x, with x = 0.0, 2.5, 5.0 and 7.5 at. %, have been obtained by pulsed laser deposition. Their electrical resistance has been measured while heating from room temperature to 650 K. A sharp fall in the electrical resistance, associated to the glass-crystal transition, has been detected in all the samples within a narrow temperature range. The onset temperature of this transformation increases with the Sn content. Both as-obtained and thermally-treated films have been structurally characterized by X-ray and by Raman spectroscopy. We have compared the results among these compositions in terms of the identified crystallization products, transformation onset temperatures, transformation temperature ranges and amorphous/crystallized electrical resistance ratio. We have found that the frequency of the Raman modes decreases with Sn-doping. Finally, in order to study the electronic structure and to determine the band gap, the frequencies of the allowed Raman modes and the vibration directions of the Sb70Te30 compound, Density Functional Theory based ab initio calculations have been performed as a function of the Sn concentration.

Sustainable disturbance crosstalk mitigation in deeply scaled phase-change memory

While Phase Change Memory (PCM) is gaining popularity in next generation systems compared to conventional DRAM and Flash, write disturbance due to crosstalk remains a significant challenge to PCM performance and reliability. To address this concern we propose a multi-tiered compression (MTC) technique combined with novel encoding that can decrease the probability of write disturbance. MTC compresses a high proportion (>94%) of cachelines by a small predictable amount (e.g., 40- or 56-bits of a 512-bit block) while maintaining data similarity vital for optimizing PCM writes. By detecting data patterns prone to crosstalk, we use encoding, correction pointers, and a hybrid approach to reduce the instances of write disturbance. We use MTC reclaimed bits to store the encoding. Thus, our approach requires only five additional auxiliary bits per 512-bit cacheline, minimizing the embodied energy (fabrication) overhead to mitigate write disturbance. Additionally, through a multi-objective optimization, dramatic endurance improvements are possible while maintaining nearly all write disturbance improvement.Our technique improves performance, endurance and write energy by 47%, 42% and 36% versus the state-of-the-art with nominal (circa 1%) increases to embodied energy. When considering the full life-cycle impact, the additional area of our MTC with encoding approach is mitigated by the use-phase benefits within 60 days for a high performance system and in less than four years of use for a desktop system. In nearly all studied scenarios, the improved lifetime provided by our MTC and encoding approach easily recoups the required additional upfront manufacturing energy.

Thermal conductivity of amorphous and crystalline GeTe thin film at high temperature: Experimental and theoretical study

Thermal transport properties bear a pivotal role in influencing the performance of phase change memory (PCM) devices, in which the PCM operation involves fast and reversible phase change between amorphous and crystalline phases. In this paper, we present a systematic experimental and theoretical study on the thermal conductivity of GeTe at high temperatures involving fast change from amorphous to crystalline phase upon heating. Modulated photothermal radiometry (MPTR) is used to experimentally determine thermal conductivity of GeTe at high temperatures in both amorphous and crystalline phases. Thermal boundary resistances are accurately taken into account for experimental consideration. To develop a concrete understanding of the underlying physical mechanism, rigorous and in-depth theoretical exercises are carried out. For this, first-principles density functional methods and linearized Boltzmann transport equations (LBTE) are employed using both direct and relaxation time based approach (RTA) and compared with that of the phenomenological Slack model. The amorphous phase experimental data has been described using the minimal thermal conductivity model with sufficient precision. The theoretical estimation involving direct solution and RTA method are found to retrieve well the trend of the experimental thermal conductivity for crystalline GeTe at high temperatures despite being slightly overestimated and underestimated, respectively, compared to the experimental data. A rough estimate of vacancy contribution has been found to modify the direct solution in such a way that it agrees excellently with the experiment. Umklapp scattering has been determined as the significant phonon-phonon scattering process. Umklapp scattering parameter has been identified for GeTe for the whole temperature range which can uniquely determine and compare Umklapp scattering processes for different materials

Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction

The existing charge-based memories like DRAM and flash are reaching their scaling limits. Phase change memory (PCM) is one of the most promising emerging memory technologies due to its good scalability and low leakage power. Multi-level cell (MLC) operation in PCM, which stores two or more bits in a single cell, is necessary to achieve a high storage density. However, a reduced resistance range in multiple storage levels of MLC PCM, introduces a lot of soft errors because of the resistance drift phenomenon. The poor reliability of MLC PCM requires strong error correction codes (ECC) which could severely degrade the storage density and performance. In this paper, we propose a cost-effective reliable MLC PCM architecture for improving MLC PCM reliability, storage density and performance. The proposed architecture exploits the data-dependent nature of resistance drift problem to reduce the ECC overhead. A simple state mapping is used to generate virtual data, which is half of the actual data size. ECC parity bits are generated based on virtual data bits instead of actual message bits, thus resulting in a reduced number of cells for parity bits. This improves the reliability and storage density of MLC PCM. The performance is also improved by minimizing the ECC overhead. Simulation results show an improvement of about 10 4 times in reliability and 10.9% in storage density compared to a conventional MLC PCM which uses a typical error correction scheme. Performance and energy efficiency are also improved up to 13.7% and 10%, respectively, by the proposed architecture.

Enhancing the Performance of Phase Change Memory for Embedded Applications

Focusing on meeting the requirements for embedded applications of faster switching and sensing, lower‐power consumption, higher reliability, longer cycling endurance, and higher temperature retention, a lot of progress in the phase change memory (PCM) field has been made, including materials improvement, process optimization, new circuits design, and better operation algorithms. Finally, a 128 MB embedded PCM chip has been demonstrated in 40 nm node. Using carbon‐doped Ge2Sb2Te5 phase change material and 3 nm thick heating bottom electrode contact (BEC) with nitride coating, a resistance ratio of more than two orders of magnitude has been achieved in Reset and Set states. Combined with the parasitic matched sensing circuit, optimized ramp‐down SET pulses, adaptive pre‐read and write‐verify methods, and automatic configure and test procedures, the chip exhibits excellent data retention and endurance characteristics with minimum program time of 200 ns, and the Reset/Set resistance ratio becomes even larger after 260 °C soldering test. The estimated data retention time is 10 years at 128 °C, and in a 128 MB full integrated chip the endurance over 109 cycles is achieved. It is confirmed that this PCM technology is suitable for embedded applications, especially for those with crucial requirements of high access speed, high thermal stability, and cycling endurance.

Improving MLC PCM Performance through Relaxed Write and Read for Intermediate Resistance Levels

Phase Change Memory (PCM) is one of the most promising candidates to be used at the main memory level of the memory hierarchy due to poor scalability, considerable leakage power, and high cost/bit of DRAM. PCM is a new resistive memory that is capable of storing data based on resistance values. The wide resistance range of PCM allows for storing multiple bits per cell (MLC) rather than a single bit per cell (SLC). Unfortunately, higher density of MLC PCM comes at the expense of longer read/write latency, higher soft error rate, higher energy consumption, and earlier wearout compared to the SLC PCM. Some studies suggest removing the most error-prone level to mitigate soft error and write latency of MLC PCM, hence introducing a less dense memory called Tri-Level memory. Another scheme, called M-Metric, proposes a new read metric to address the soft error problem in MLC PCM. In order to deal with the limited lifetime of PCM, some extra storage per memory line is required to correct permanent hard errors (stuck-at faults). Since the extra storage is used only when permanent faults occur, it has a low utilization for a long time before hard errors start to occur. In this article, we utilize the extra storage to improve the read/write latency in a 2-bit MLC PCM using a relaxation scheme for reading and writing the cells for intermediate resistance levels. More specifically, we combine the most time-consuming levels (intermediate resistance levels) to reduce the number of resistance levels (making a Tri-Level PCM) and therefore improve write latency. We then store some error correction metadata in the extra storage section to successfully retrieve the exact data values in the read operation. We also modify the Tri-Level PCM cell to increase its read latency when the M-Metric scheme is used. Evaluation results show that the proposed scheme improves read latency by 57.2%, write latency by 56.1%, and overall system performance (IPC) by 26.9% over the baseline. It is noteworthy that combining the proposed scheme and FPC compression method improves read latency by 75.2%, write latency by 67%, and overall system performance (IPC) by 37.4%.

Partial-PreSET: Enhancing Lifetime of PCM-Based Main Memory with Fine-Grained SET Operations

Phase change memory (PCM) is one of promising technology to replace DRAM with its attractive features such as zero leakage power and high scalability. In PCM, a SET operation needs much more time than a RESET operation. A typical write request concurrently writes 64 bytes to a PCM memory line. Therefore, write latency is mainly determined by SET operations. Previously, PreSET has been proposed to improve PCM performance by exploiting asymmetry in write time. A PreSET operation pro-actively SETs all the bits in the memory line before a dirty cache line is written to PCM . Later, when a write request is processed, only RESET operations are actually performed. Consequently, PreSET reduces write latency and improves system performance. However, such PreSET operations are conducted only at a very coarse-grained level, which reduces the endurance of PCM. Through empirical study, we observe that in most applications the number of dirty words in a dirty line is actually quite limited. If we only SET those dirty words, instead of the whole cache line, we would significantly extend the lifetime of PCM while still achieving desirable performance. Inspired by this observation, we propose a scheme called Partial-PreSET which balances performance and endurance of PCM. The core idea of this scheme is to SET those dirty bits of a cache line in a fine-grained fashion. Our experiments show that the proposed Partial-PreSET scheme significantly improves the average lifetime of PCM system, up to 2.79X, while incurring only 2% system performance loss, compared with the state-of-the-art scheme (i.e., PreSET).

Modelling of wire resistance effect in PCM‐based nanocrossbar memory

At nanoscale grain boundaries and surface scattering effects lead to an increase of connecting wires electrical resistivity with decreasing wire dimensions. This increase of resistivity leads to significant power loss across connecting wires in nanocrossbars. In this study, the resistance of connecting wire as a function of material properties and feature size is calculated. Then the effect of the connecting wires resistance in phase change memory (PCM) performance in PCM-based passive nanocrossbar was evaluated. The performance metrics tested are: programmed resistance levels, programming duration, and energy consumption. Based on the simulation results, it was found that the power consumed in connecting wires decreases the power supplied to PCM cells. This reduction in power results in higher programmed low resistive state (R ON). The effect of connecting wire resistance on PCM performance is studied as a function of the wire size, cell position on the nanocrossbar, and nanocrossbar size. Simulation results showed that the programmed R ON is inversely proportional to feature size. Moreover, it increases up to almost 40%, with decreasing feature size to 40 nm. Moreover, programmed R ON increases proportionally with increasing nanocrossbar size. Moreover, R OFF/R ON ratio drops almost 90% of targeted ratio at 1 kbit nanocrossbars. Furthermore, cells closer to supply sources are the least affected by wire resistance, while cells furthest from supply are the most affected. Finally, at the end of this study two methods are suggested to resolve the programmed R ON reliability issue caused by energy drop across connecting wires.

Study of phase change materials for phase change random access memory

Phase change memory technology, which is regarded as one of the most promising candidates for the next generation non-volatile memory technology, has achieved rapid development in the past ten years. Meanwhile, related products based on this technology have been put into the market and mass production has come true. With the development of phase change memory technology, the fundamental research has become a hot topic in the fields of information, materials, and so on. Phase change storage medium based on chalcogenide is the basis and core of phase change memory. The performance of phase change memory is determined by phase change material’s performance. In this paper, the industrialization status of phase change memory are briefly introduced firstly, then the research progress of the commonly used GeSbTe phase change materials and the main phase transition mechanism is summarized. Finally, the C doping modification of the traditional GeSbTe and the phase change mechanism of C-doped GeSbTe materials is analyzed.

Viscosity of liquid Ag-In-Sb-Te: Evidence of a fragile-to-strong crossover.

The temperature-dependent viscosity η(T) is measured for the equilibrium liquid of the chalcogenide Ag-In-Sb-Te (AIST), the first time this has been reported for a material of actual interest for phase-change memory. The measurements, in the range 829-1254 K, are made using an oscillating-crucible viscometer, and show a liquid with high fragility and low viscosity, similar to liquid pure metals. Combining the high-temperature viscosity measurements with values inferred from crystal growth rates in the supercooled liquid allows the form of η(T) to be estimated over the entire temperature range from above the melting point down to the glass transition. It is then clear that η(T) for liquid AIST cannot be described with a single fragility value, unlike other phase-change chalcogenides such as liquid Ge-Sb-Te. There is clear evidence for a fragile-to-strong crossover on cooling liquid AIST, similar to that analyzed in Te85Ge15. The change in fragility associated with the crossover in both these cases is rather weak, giving a broad temperature range over which η(T) is near-Arrhenius. We discuss how such behavior may be beneficial for the performance of phase-change memory. Consideration of the fragile-to-strong crossover in liquid chalcogenides may be important in tuning compositions to optimize the device performance.