Pattern Generation Process Research Articles

Direct observation of microcontact behaviours in pattern-generation step of reverse offset printing

In this study, we investigate the static and dynamic aspects of the nip formed during roll-to-sheet-type reverse offset printing. First, we show that several modes of roof collapses (bottom contact defects) could be formed depending on the poly(dimethylsiloxane) (PDMS) blanket thickness and pattern size. We regulate the manifestation of the defect modes driven by the local pile-up of the incompressible PDMS, as modelled by the contact mechanics formulation, together with a complementary numerical simulation. In dynamics, we first differentiate between the static nip and dynamic nip during printing, where the width is extended by the kinetically controlled adhesion of the blanket PDMS. Further, we observe that depending on the pattern structure, there was spatial deviation of the microscopic contact and subsequent separation behaviours of the cliché from a macroscopically recognizable nip, and consequently, local detachment rates were heterogeneous in the pattern-generation process of the reverse offset printing, even with a constant machine speed. In addition, we found that the parts of a pattern where the ink transfer fails in a high-speed patterning condition corresponded to the region of the locally enhanced detachment rates found during direct observation.

Implementation of Pedestrian Dynamic

Pattern generation is one of the ways to implement computer science in art. Many methods have been implemented. One of them is cellular automata. In a previous work, cellular automata (CA) has been used to create an image with stochastic and irregular pattern. There are problems in the performance of the method because the average number of the occupied cells is less than 50 percent. So, this method must be improved. In this research, the pedestrian dynamic concept is implemented into the pattern generation process. This method is used so that there is a combination between stochastic and deterministic approaches in generating the pattern. This combination is the key element of the method. This proposed model has successfully produced irregular pattern image too. Based on quantitative test, the occupied cell ratio is still less than 50 percent but the proposed model can make a better distance between last position and starting point nodes of the pattern. When the number of agents is 75, the target to reach the occupied cells ratio by more than 75 percent is achieved.

Protein patterns template arrays of magnetic nanoparticles

Pattern generation process for growth of magnetite nanoparticles (MNP), using patterns of octadecane thiol and poly(ethylene glycol) to selectively immobilize the biomineralization protein Mms6 and selectively form on the immobilized Mms6.

Reconfigurable Scan Networks

Efficient access to on-chip instrumentation is a key requirement for post-silicon validation, test, debug, bringup, and diagnosis. Reconfigurable scan networks, as proposed by, for example, IEEE Std 1687-2014 and IEEE Std 1149.1-2013, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. Reconfigurable scan networks are often hierarchical and may have complex structural and functional dependencies. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. To access an instrument in a reconfigurable scan network, a scan-in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the access pattern generation process ( pattern retargeting ) poses a complex decision and optimization problem. This article presents the first generalized formal model that considers structural and functional dependencies of reconfigurable scan networks and is directly applicable to 1687-2014-based and 1149.1-2013-based scan architectures. This model enables efficient formal verification of complex scan networks, as well as automatic generation of access patterns. The proposed pattern generation method supports concurrent access to multiple target scan registers ( access merging ) and generates short scan-in sequences.

Delivering Guaranteed Display Ads under Reach and Frequency Requirements

We propose a novel idea in the allocation and serving of online advertising. We show that by using predetermined fixed-length streams of ads (which we call patterns) to serve advertising, we can incorporate a variety of interesting features into the ad allocation optimization problem. In particular, our formulation optimizes for representativeness as well as user-level diversity and pacing of ads, under reach and frequency requirements. We show how the problem can be solved efficiently using a column generation scheme in which only a small set of best patterns are kept in the optimization problem. Our numerical tests suggest that with parallelization of the pattern generation process, the algorithm has a promising run time and memory usage.

Parallelized sequential value correction procedure for the one-dimensional cutting stock problem with multiple stock lengths

A heuristic approach with parallel computation is presented for the one-dimensional cutting stock problem with multiple stock lengths. The algorithm is based on the sequential heuristic procedure that generates each pattern to produce some items and repeats until all the required items are fulfilled. A recursion is used to solve the bounded knapsack problem heuristically in the pattern generation process to reduce running time. The item values are adjusted after the generation of each pattern using a value correction formula. The computational results show that the algorithm is more effective than a recently published evolutionary heuristic in improving solution quality, and can reduce computational time because of the efficient parallel implementation.

Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction

Eliminating the excessive test power for integrated circuits is a strict challenge within the nanometer era. This method combines test pattern generation with the scan chain disabling technique to achieve low capture power testing under the single stuck-at fault model. Testability analysis is exploited to assist in the test pattern generation process to generate the observation-oriented test patterns. In order to direct fault effects to the frequently-used circuit outputs, unbalanced observability costs are purposely assigned to circuit outputs to introduce unequal propagation probability. Observation-aware scan chain clustering is then performed through a weighted compatibility analysis to densely cluster the frequently-used scan cells into scan chains. Consequently, more scan chains can be disabled in the capture cycle and significant power reduction can be achieved without affecting the fault coverage. To simultaneously consider the reduction in large test data volume and capture power, the power-aware test vector compaction algorithm is also performed. Experimental results for the large ISCAS'89 benchmark circuits show that significant improvements can be simultaneously achieved including 71.7 % of capture power reduction, 43.7 % of total power reduction, 24.3 % of peak power reduction and 98.0 % of test data compaction ratios averagely. Results for three large ITC'99 benchmark circuits also demonstrate the effectiveness of the proposed method for the practical-scale circuits.

Symmetry preserving in Topological Mapping for tension structures

When using Topological Mapping (TM) together with the Force Density Method (FDM) in order to find a first form of equilibrium for a tension structure whose fixed nodes coincide in plan view with the vertices of a regular polygon, it has been observed that the symmetry may be lost. The problem is related to the mapping procedure that is introduced in the process. However, if some rules are followed in constructing the topology for the mesh, the symmetry can be preserved. With a symmetric mesh, the later cutting pattern generation process becomes simpler, easier, and cheaper. This paper will provide one simple algorithm that has been proved to work effectively in preserving the symmetry in the cited type of tension structures. Several examples are presented in order to better illustrate the applicability of these easy prescriptions.

Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults

Testing for small-delay defects (SDDs) has become necessary as technology further scales. Existing tools and methodologies for generating SDD patterns suffer from: limited long-paths sensitization capability, overwhelming pattern volume, time-consuming pattern generation process, and vague evaluations of pattern quality. Such situation places patterns in a dilemma where the generation and application effort are huge yet the results cannot reflect the physical phenomena clearly enough for correct binning and diagnosis. In this paper, we focus on establishing a pattern generation flow that produces patterns of high application value. Firstly, critical faults are identified in order to generate high-quality original pattern repository with n-detect ATPG.A novelpattern evaluation and selection method that further minimizes pattern count while maintaining the SDD detection ability is then presented. Top-off ATPG is then performed to ensure meeting the target fault coverage. Along with the flow, multiple evaluation metrics are also proposed to measure the pattern's efficiency on SDD coverage, unique SDD detection, detectable SDD size, long path distribution, etc. Experimental results demonstrate that the proposed critical fault-based method improves long path sensitization efficiency by 2.5× without impairing its average delay and saves approximately 80 % CPU runtime compared with total fault-based method. Comparing with timing-aware ATPG, the generated pattern set detects equivalent or even more SDDs with significantly reduced pattern count.

Study on Test Compaction in High-Level Automatic Test Pattern Generation (ATPG) Platform

Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.

Multi‐scale Assemblage for Procedural Texturing

AbstractA procedural pattern generation process, called multi‐scale “assemblage” is introduced. An assemblage is defined as a multi‐scale composition of “multi‐variate” statistical figures, that can be kernel functions for defining noise‐like texture basis functions, or that can be patterns for defining structured procedural textures. This paper presents two main contributions: 1) a new procedural random point distribution function, that, unlike point jittering, allow us to take into account some spatial dependencies among figures and 2) a “multi‐variate” approach that, instead of defining finite sets of constant figures, allows us to generate nearly infinite variations of figures on‐the‐fly. For both, we use a “statistical shape model”, which is a representation of shape variations. Thanks to a direct GPU implementation, assemblage textures can be used to generate new classes of procedural textures for real‐time rendering by preserving all characteristics of usual procedural textures, namely: infinity, definition independency (provided the figures are also definition independent) and extreme compactness.

Block pattern generation: From parameterizing human bodies to fit feature-aligned and flattenable 3D garments

Research on clothing related CAD is blooming rapidly in the last two decades. It speeds up the product development process significantly and shortens the time to market of fashion products. Although many important results have been obtained, particularly in the computer graphics community, the textile industry is somehow reluctance to adopt these results in actual apparel manufacturing. The main concern is the accuracy of the resulted patterns, because the pattern generation processes ignored some important textile material and manufacturing constraints. This paper introduces a method for generating 2D block patterns from 3D scanned body. A parameterization process is first conducted on a scanned body to create a parameterized model, represented by horizontal B-spline curves. A basic wire-frame aligned with body features is then established based on the parameterized model. Proper clothing ease is carefully incorporated into the model by scaling the wireframe to accomplish the desired fit. Based on the deformed wireframe, a 3D flattenable garment is modeled by boundary triangulation. The main contribution of the proposed method is that the created 3D garment blocks are geometrically flattenable to produce accurate 2D patterns with optimized ease distribution to ensure garment fit. The proposed method is validated and compared to two conventional block patternmaking methods. The experimental results indicate that the proposed method is easy to implement and can generate patterns with satisfactory fit. Furthermore, the method can be used to create fit-ensured mass-customized apparel product.

Binary genetic algorithm-based pattern LUT for grayscale digital half-toning

Grayscale digital half-toning is a popular technique to reproduce grayscale images with devices that can support only two levels at output, i.e., black and white. Printers, LCD displays, etc. are some common examples of such devices. Considering 0 and 1 as black and white, respectively, this can be represented as an image-wise binary pattern generation process. The binary patterns are aimed to retain the local tonal and structural characteristics of grayscale image for a faithful illusion of the original grayscale image. Apart from tonal and structural characteristics retention, desired blue-noise characteristics also contribute significantly toward eye pleasant appearance of half-tone images. The paper presents a binary genetic algorithm-based approach to generate such binary patterns through optimizing randomly generated binary strings against a visual cost function. Paper also presents a pattern look-up-table (LUT)-based approach toward conventional clustered dot ordered dithering which is suitable for devices like laser or offset printers that cannot recognize individual pixels. The pattern LUT approach is driven toward green-noise characteristics instead of the blue-noise characteristics. The results obtained with test images are presented pictorially and evaluated through half-tone quality evaluation metrics. The evaluation results and comparison with state-of-art techniques shows the potential of presented technique for practical implementations.

Improving pattern quality in web usage mining by using semantic information

Frequent Web navigation patterns generated by using Web usage mining techniques provide valuable information for several applications such as Web site restructuring and recommendation. In conventional Web usage mining, semantic information of the Web page content does not take part in the pattern generation process. In this work, we investigate the effect of semantic information on the patterns generated for Web usage mining in the form of frequent sequences. To this aim, we developed a technique and a framework for integrating semantic information into Web navigation pattern generation process, where frequent navigational patterns are composed of ontology instances instead of Web page addresses. The quality of the generated patterns is measured through an evaluation mechanism involving Web page recommendation. Experimental results show that more accurate recommendations can be obtained by including semantic information in navigation pattern generation, which indicates the increase in pattern quality.

A novel compensation method for polygonized mesa structures on (100) silicon substrate

A theoretical compensation method for polygonized mesa structures on (100) silicon substrate during the anisotropic etching process has been developed, which contains four stages as follows: prepare the information of the etching condition; predict the structure's undercutting profile; construct the topological structure of compensation patterns; and generate practical compensation patterns from the topological structure. The reasoning process is clearly stated, and detailed steps for the undercutting prediction and topological structure construction are summarized. Conclusions are also drawn about the rules which must be obeyed during the pattern generation process. The simulation and experimental results of some polygon structures are finally given to prove this method's validity and reliability.

A Conversational Agent Framework using Semantic Analysis

This paper focuses on the implementation of a novel semantic-based Conversational Agent (CA) framework. Traditional CAs interpret scripts consisting of structural patterns of sentences. User input is matched against such patterns and an associated response is sent as output. This traditional CA approach, which solely takes into account the structural form of a sentence, requires the scripter to anticipate the inordinate ways that a user may send input. This is a tiresome and timeconsuming process. As such, a semantic-based CA that interprets scripts consisting of natural language sentences alleviates this burden by removing the process of pattern generation. The CA was evaluated by participants using a domain of a specific nature, that is, student debt management, which indicated promising results.

Comparison of Traditional 2D and Virtual Patterns Design in 3D

This paper presents a garment pattern generation process and modelling of virtual garment design method in 3D. This work characterize our global project on virtual clothing design contains of the conception of virtual adaptive mannequin, and also of the creation and modelling of garment in 3D. According to the ideas of mass customization and e-commerce, as well the need of numerical innovations in garment industry we employ our model of virtual garment and methodology enabling to conceive the virtual clothing directly on a mannequin morphotype in 3D. This method gives us possibility to create a perfect garment and taking into account all peculiarities of human body. In 2D method we made two patterns: left and right side separately to obtain best result and to get possibility to compare two cases: when symmetric pattern is used and when we use pattern consisted of two parts specially made for each side of the body. In the present context we use the example of a basic women's shirt: bodice and sleeve. We used the method of making pattern employed in Russia compared with French method. Finally the superposition of virtual and real pattern was done in order to visualise the right results.

육각화소 기반의 지역적 이진패턴을 이용한 배경제거 알고리즘

동영상에서의 배경제거는 다양한 실시간 머신 비젼 응용에서 매우 중요한 단계이다. 본 논문에서는 이러한 배경제거를 위한 육각화소 기반의 새로운 접근 방법을 제안한다. 일반적으로 육각형 샘플링 영상은 양자화 오차가 적으며, 이웃화소의 연결성 정의를 크게 개선한다고 알려져 있는데, 제안된 방법은 비매개변수형 배경제거 방법의 하나인 지역적 이진패턴 기반 알고리즘에 이러한 육각 샘플링 영상을 적용하는 것을 특징으로 한다. 이를 통해, 지역적 이진패턴의 추출과정에서 필요한 쌍선형 보간을 없애고 계산량을 줄일 수 있었다. 실험을 통해 이러한 육각화소의 적용이 배경제거 분야에 매우 효율적으로 적용될 수 있음을 확인할 수 있었다. Background subtraction from video data is one of the most important task in various realtime machine vision applications. In this paper, a new scheme for background subtraction based on the hexagonal pixel sampling is proposed. Generally it has been found that hexagonal spatial sampling yields smaller quantization errors and remarkably improves the understanding of connectivity. We try to apply the hexagonally sampled image to the LBP based non-parametric background subtraction algorithm. Our scheme makes it possible to omit the bilinear pixel interpolation step during the local binary pattern generation process, and, consequently, can reduce the computation time. Experimental results revealed that our approach based on hexagonal spatial sampling is very efficient and can be utilized in various background subtraction applications.

The X factor

X-states in a circuit design complicate the process of pattern generation and defect detection. X-states complicate the design, verification and testing of advanced ICs. In particular, X-states interfere with test compression, which is becoming a necessity for efficient testing of large devices. Although newer design methods help prevent X-states from occurring in a functional design, many X-states still creep in when real devices are initialised for test, and even more can occur when at-speed testing is performed.

Demonstration and verification of a model that generates defoliation patterns in forested landscapes

Research into the sensitivity of a forest health monitoring network to outbreaks of defoliating insects spurred development of a new model that simulates outbreaks and generates patterns of defoliation in forested landscapes. Key features of the model included (1) input of a few data layers that were readily obtainable, (2) user control over the pattern generation process, (3) strong linkage between model parameters and a readily available source of parameter values, (4) simulation of large areas in a reasonable amount of time, and (5) detailed spatial output. A verification of the model was made by comparing model results with the results from actual outbreaks. Spruce budworm incidence maps for the period 1997–2003 in Minnesota were obtained and 12 different outbreaks identified. Model runs were developed, one for each of the outbreaks, and the numbers of plots defoliated in the actual outbreaks were compared to simulation frequencies. The number of plots falling in the actual outbreak matched the number of plots with the highest and second highest simulation frequency in nine and three of the verification runs, respectively. Results suggested that the computer model was an accurate implementation of the conceptual model and therefore suited to the intended application.