Partial Scan Design Research Articles

Editorial?Special issue on partial scan design

Editorial?Special issue on partial scan design

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.

A three-stage partial scan design method to ease ATPG

A new three-stage process for partial scan design is presented. The first two stages focus on cyclebreaking, and on limiting the maximum length of consecutive self-loops, as proposed by previous researchers. For the third stage, combinational blocks and their effects on sequential test generation are evaluated using a graphtheoretic representation designated the circuit flow graph. Costs calculated from the circuit flow graph representation are then used to select additional scan flip-flops. Sequential test generation results show that our selection of scan flip-flops is generally smaller than that reported by earlier researchers, and leads to a comparable fault coverage and smaller test generation time.

Partial scan design of register-transfer level circuits

Register-transfer level designs that are derived from high-level synthesis systems generally consist of functional blocks and registers that are interconnected by multiplexers and buses to maximize resource sharing These multiplexer and bus structures have the unique ability to behave asswitches, i.e., to logically partition the circuit when their control inputs are manipulated in different ways. The presence of switches, the selection of scan registers can be influenced. This leads to an efficient partial scan methodology presented in this paper. Second, switches help set up data transfer paths calledI-paths. By employingI-paths to transport test data, the functional logic in the circuit can be separated from the switching logic for the purpose of test generation. This can lead to a reduction in test generation costs for a partial scan design. Thus the techniques presented in this paper help to minimize both testability overhead and test generation cost in bus-based circuits. This methodology is implemented in the SIESTA system for serial scan design.

Single clock partial scan

Existing partial-scan designs use a separate scan clock to simplify scan flip-flop selection and test generation methods. Such designs require multiple clock trees and create clock-signal routing problems that, in general, require tight control of clock skew. The author examines using the system clock for the scan operation and includes experimental results based on ISCAS89 benchmark circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The economics of scan-path design for testability

In this article, scan design for testability (DFT) methods are categorized based on the percentage of storage elements made scannable. The non-scan element state retention problem that occurs in partial scan design methods, in which not all of the storage elements are implemented as scan elements, is discussed. Solutions to this problem are described and the overheads associated with them are discussed. An economic model that allows the costs of a range of scan methods that differ in the percentage of storage elements made scannable to be compared with each other is presented. It is shown that, for systems produced in low volumes, the adoption of full scan DFT can be more cost-effective than partial scan DFT when life-cycle costs are considered if it results in significant reductions in the time taken to get the product to market.

A test methodology for finite state machines using partial scan design

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.

New partial scan design based on hard fault distribution analysis

In the paper, a post-test generation partial scan method, called hard fault distribution (HFD), is proposed. The goals of this approach are to have the ability of co-operating with any test pattern generator and to obtain maximum fault coverage for the number of flip-flops selected to be scanned. The concept of the HFD method consists of the essence of previous relative works such as testability analysis, structure analysis and test generation based methods. This method has been applied to several sequential benchmark circuits by co-operating with a simulation-based directed-search test generator. Experimental results show that this HFD method is very efficient.

The Ballast methodology for structured partial scan design

An efficient partial scan technique called Ballast (balanced structure scant test) is presented. Scan path storage elements (SPSEs) are selected such that the remainder of the circuit has certain desirable testability properties. A complete test set is obtained using combinatorial automatic test pattern generation (ATPG). Some SPSEs may need to be provided with a HOLD mode; their number is minimized by ordering the registers in the scan path and formatting the test patterns appropriately. This methodology leads to a low area overhead and allows 100% coverage of irredundant faults.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A partial scan method for sequential circuits with feedback

A method of partial scan design is presented in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with the sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles and reducing the sequential depth. Tests for the resulting circuit are generated by a sequential logic test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequence produced by the test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequences produced by the test generator. 98% fault coverage is obtained for a 5000-gate circuit by scanning just 5% of the flip-flops. >