Effect Of Parasitic Capacitance Research Articles

A modified linear capacitive displacement transducer for any range

–In the present paper, a modified linear capacitive displacement transducer is developed, where the measurement errors and non-linearity errors due to the various effects such as the effect of the change of atmospheric parameters, the effect of parasitic fringe capacitance, the effect of stray capacitance, the effect of parallel position shifting of the sensing plates, etc. are minimized, and the output is linearly related with displacement for any range. The transducer consists of a sensing capacitor and a similar reference capacitor, each of which has a noninductive double layer short-circuited winding wound on an insulating uniform hollow cylinder. The sensing cylinder has a thin circular conducting disk, which is easily displaceable by the moving object along the inside walls of the cylinder from the outside by means of a thin conducting disk rod attached to the central position of the disk. The reference cylinder has a similar disk with a disk rod fixed at the reference zero position. The transducer circuit measures the difference of the combined cylindrical-perpendicular plate capacitances between the short-circuited terminal of vertical noninductive winding and the horizontal conducting disk of the two capacitors and gives an output that is found to be linearly related with displacement for the entire length of the sensing cylinder. The measurement is free from the non-linearity error for any range because the factors producing nonlinearity are similar for the two capacitors and tend to cancel each other. The derived characteristic equations are supported by the experimental results with very good accuracy and repeatability.

Threshold Voltage Extraction of nMOSFET Devices in Photovoltaic Inverters

Abstract In this paper, the electrical characteristics of nMOSFET devices at room temperature are measured, and the threshold voltage is extracted by three different methods according to the I-V transfer characteristic curve of the nMOSFTE devices. The applicability of the three methods and the extraction results are analyzed and compared. The conclusions indicate that: (1) the maximum transconductance extraction method is similar to the tangential extrapolation extraction method, both of which eliminate the influence of mobility degradation and parasitic capacitance effect. The second order derivative extraction methods include the fluctuation factors in the measured results, and has a larger error on the extracted threshold voltage; (2) Compared with the maximum transconductance extraction method, the errors of extracting threshold voltage using tangential extrapolation method is larger because mobility attenuation, sourcing-drain series resistance and tangential point is difficult to determine accurately are ignored. (3) In comparison, the threshold voltage extracted by the maximum transconductance method is more accurate and easy to achieve.

Minimization of Parasitic Capacitance between Skin and Ag/AgCl Dry Electrodes.

Conventional dry electrodes often yield unstable results due to the presence of parasitic capacitance between the flat electrode surface and the non-uniform skin interface. To address this issue, a gel is typically placed between the electrodes to minimize parasitic capacitance. However, this approach has the drawbacks of being unsuitable for repeated use, limited lifetime due to gel evaporation, and the possibility of developing skin irritation. This is particularly problematic in underserved areas since, due to the cost of disposable wet electrodes, they often sterilize and reuse dry electrodes. In this study, we propose a method to neutralize the effects of parasitic capacitance by attaching high-value capacitors to the electrodes in parallel, specifically when applied to pulse wave monitoring through bioimpedance. Skin capacitance can also be mitigated due to the serial connection, enabling stable reception of arterial pulse signals through bioimpedance circuits. A high-frequency structure simulator (HFSS) was first used to simulate the capacitance when injection currents flow into the arteries through the bioimpedance circuits. We also used the simulation to investigate the effects of add-on capacitors. Lastly, we conducted preliminary comparative analyses between wet electrodes and dry electrodes in vivo with added capacitance values ranging from 100 pF to 1 μF, altering capacitance magnitudes by factors of 100. As a result, we obtained a signal-to-noise ratio (SNR) that was 8.2 dB higher than that of dry electrodes. Performance was also shown to be comparable to wet electrodes, with a reduction of only 0.4 dB using 1 μF. The comparative results demonstrate that the addition of capacitors to the electrodes has the potential to allow for performance similar to that of wet electrodes for bioimpedance pulse rate monitoring and could potentially be used for other applications of dry electrodes.

Analysis of the parasitic capacitance effects on the layout of latch-based sense amplifiers for improving SRAM performance

Static random-access memory (SRAM) technology is utilized in designing cache memory to enhance the processing performance of computer systems. The sense amplifier (SA) circuit, a crucial component of memory design, significantly impacts data access time and power consumption. In comparison to conventional differential sense amplifiers (DSA) designs, latch-based sense amplifiers (LSA) used in memory-based computing platforms have specific requirements, including robust noise resistance in harsh working environments and low power consumption, particularly for internet of thing (IoT) embedded computing applications. However, the performance can be degraded due to various factors that arise during the layout, such as conductor resistance or the development of parasitic capacitance. Therefore, this study employs low-voltage 22 nm UMC CMOS technology for LSA design layout and analyzes the factors influencing design performance post-layout process. Layout design optimization techniques are applied to mitigate the impact of parasitic capacitance on important signal lines such as data line/data line bar (DLL/DLLB). Based on the performance analysis results, it is possible to achieve a reduction in power consumption of up to 15% and a 5% decrease in read delay time by implementing circuit layout LSA design optimization techniques.

Effects of parasitic gate capacitance and gate resistance on radiofrequency performance in LG = 0.15 μm GaN high‐electron‐mobility transistors for X‐band applications

AbstractThe effects of the parasitic gate capacitance and gate resistance (Rg) on the radiofrequency (RF) performance are investigated in LG = 0.15 μm GaN high‐electron‐mobility transistors with T‐gate head size ranging from 0.83 to 1.08 μm. When the device characteristics are compared, the difference in DC characteristics is negligible. The RF performance in terms of the current‐gain cut‐off frequency (fT) and maximum oscillation frequency (fmax) substantially depend on the T‐gate head size. For clarifying the T‐gate head size dependence, small‐signal modeling is conducted to extract the parasitic gate capacitance and Rg. When the T‐gate head size is reduced from 1.08 to 0.83 μm, Rg increases by 82%, while fT and fmax improve by 27% and 26%, respectively, because the parasitic gate–source and gate–drain capacitances reduce by 19% and 43%, respectively. Therefore, minimizing the parasitic gate capacitance is more effective that reducing Rg in our transistor design and fabrication, leading to improved RF performance when reducing the T‐gate head size.

Effect of Metal Oxide Semiconductor Field-Effect Transistor Output Parasitic Capacitance on Efficiency in Full-Bridge LLC DC/DC Converters.

This study analyzed the efficiency impact of a MOSFET output parasitic capacitance (Coss) on a full-bridge LLC DC/DC converter. The core of the converter was the control chip for a half-bridge LLC DC/DC converter, and the output signal of the chip controlled the first-arm power transistors of the primary side of the converter. The coupling transformer reversed the output signal to control the primary side of the second arm of the power transistor. The full-bridge converter comprises a half-bridge control chip that converts the high-voltage DC power supply to a low-voltage DC power supply, which is then synchronously rectified and supplied to the load. The primary side of the power transistor achieves a zero-voltage switching (ZVS) state through the resonance of the LLC converter. This design gives the converter high power density and a simple structure. Furthermore, to determine the appropriate output parasitic capacitance for improving converter efficiency, this study analyzed the effect of the output parasitic capacitance on the switching loss and conduction loss of the power transistor on the basis of the output parasitic capacitance of the primary-side power transistor. A 1200 W converter prototype was fabricated in this study, and when the output was 300 W, efficiency increased from 92.603% to 93.462%, a 0.859% increase. The empirical results verified the feasibility of the proposed theory.

Parasitic Capacitance in High-Density Neural Electrode Arrays: Sources and Evaluation Methods.

This study aims to identify sources of parasitic capacitance in high-density neural electrode arrays and to provide an approach for evaluating their associated capacitance values. We also represent the effect of parasitic capacitance on the electrochemical properties of electrodes. Electrochemical impedance spectroscopy (EIS) and voltage transient (VT) measurements were employed to assess the parasitic capacitance of a 16-channel ultramicro-sized electrode array (UMEA) (8×25 μm2 electrode sites). The effect of parasitic capacitance on cyclic voltammetry (CV), EIS, and VT measurements of 20-μm diameter electrodes was assessed by comparing two different array designs: narrow and wide trace arrays. The capacitive leakage currents and charge during CV measurements were not significant, however, during current pulsing 34% underestimation of the maximum charge injection capacity corresponded to capacitive leakage. Capacitive leakage during EIS resulted in an underestimation of the electrode impedance at frequencies >1.5 kHz. The electrode design and insulation thickness can play a significant role in determining the amount of capacitive leakage during current pulsing and EIS at higher frequencies. Determining the sources and levels of capacitive leakage current in high-density neural electrode arrays, enables us to correct the measured value for the leakage current and thus estimate the electrode impedance and stimulation thresholds more accurately. This study highlights the importance of electrode design in developing high-density arrays with minimum capacitive leakage.

An Improved Grouping Transformer's Secondary Windings Current-Sharing Method for Multiphase LLC Converter

Current balancing performance of the existing grouping transformer's secondary windings (GTSW) method is determined by leakage inductance mismatches. Nevertheless, the transformer's leakage inductance parasitic parameters in practice are difficult to accurately design, especially in high-frequency occasions, causing a large current-sharing error between phases. To solve this problem, this paper proposes an improved GTSW (IGTSW) current-sharing method. By ingeniously changing the connection mode of transformer's secondary windings, the influence of secondary leakage inductance mismatch on current sharing performance is eliminated, and the current sharing performance of secondary side is significantly improved. The first harmonic approximation (FHA) analysis method is used to establish the current sharing error model of the primary side and secondary side of the system. Furthermore, the current sharing performance of the existing GTSW method and the proposed method is quantitatively compared. Then, the effectiveness of the proposed method is verified by simulation and the two-phase 480W experiment results. Finally, some great performances of the proposed method are discussed, such as advantages in high-frequency applications, no effect of parasitic capacitance on the current sharing performance, the potential scalability in the case of other DC-DC topology and high current scenarios, and modular expansion capabilities, etc.

MOSFET Layout Design for High-Gain Amplifiers at mm-Wave and Sub-Terahertz

The parasitic capacitance and resistance originated from interconnect metals of MOSFETs degrade the high-frequency performance, including gain and bandwidth. The degradation is exacerbated as the frequency increases toward the mm-wave and sub-terahertz band. Fortunately, the adverse effect of parasitic capacitance can be relieved by circuit design techniques such as reactive impedance matching and neutralization. However, the parasitic resistance, particularly at the gate, causes loss and gain degradation, which is not easily compensated at the circuit level. In this work, the gate resistances induced by interconnect metals of two different gate feed structures are compared, which yields a layout suitable for the mm-wave and sub-terahertz band. It is experimentally confirmed that the proposed layout for a gate width of 20–60 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m lowers the gate resistance by 10%–19.4% and consequently increases the device <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm{MAX}}$</tex-math> </inline-formula> by 12.6%–23.9% compared to a reference layout. In addition, two <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$</tex-math> </inline-formula> -band single-stage amplifiers, each using the proposed or reference layout, are compared to verify the circuit-level benefit. The measured peak gain is improved by 1.6 dB at 133 GHz due to the reduced gate resistance.

Utilizing Parasitic Capacitance of Single‐Droplet Electricity Generator For Specific Bacterial Detection

AbstractSingle‐droplet electricity generator (SDEG) has superior potential over other solid–liquid triboelectric nanogenerators (TENGs) for energy harvesting. However, its shunting effect of parasitic capacitance is adverse and unavoidable, resulting in the reduction of the SDEG voltage. In addition, TENG‐based bacterial biosensors are still facing issues of incompetence in resolution, precision, and specificity. Therefore, a novel SDEG‐based bacterial biosensor is developed by making use of parasitic capacitance. By taking the advantages of aptamer and parasitic capacitance, the Pseudomonas aeruginosa (P. aeruginosa) can be specifically and precisely detected via signal change from a single droplet without energy accumulation. This study proves that the SDEG‐based bacterial biosensor exhibits an excellent performance for P. aeruginosa detection in low limit of detection (4.5×103 CFU mL−1) with high selectivity. Meanwhile, the established mathematical model yields consistent results to the experimental ones, which serves as a solid basis for quantifying bacterial concentration. This work contributes to TENG‐based bacterial biosensor, and opens up a new way for the diversified application of SDEG.

Analysis and Experiment of Self‐Powered, Pulse‐Based Energy Harvester Using 400 V FEP‐Based Segmented Triboelectric Nanogenerators and 98.2% Tracking Efficient Power Management IC for Multi‐Functional IoT Applications

AbstractA self‐powered system for the Internet of Things (IoT) is demonstrated for efficient energy harvesting of naturally available mechanical energy. In this system, new contact‐separation mode triboelectric nanogenerators (TENGs), based on fluorinated ethylene propylene, are investigated using the segmented multi‐TENG configuration to reduce the effect of parasitic capacitance. The TENG extraction is optimized using a unit step excitation involved with the Dawson function to achieve a high voltage (400 V) and a high current (26.6 µA). To fully extract the power of the TENGs, the power management integrated circuit (PMIC) specially designed for adaptively controlled, high‐voltage (HV) maximum power point tracking (MPPT) is proposed. The PMIC implemented in a bipolar CMOS‐DMOS 180 nm process can handle a wide input range (5–70 V) by consuming 420 nW. The MPPT control allows a wide range of impedance matching from 10 to 300 MΩ, achieving a tracking efficiency of up to 98.2%. The end‐to‐end efficiency of 88% demonstrates state‐of‐the‐art performance. To supply a higher instantaneous power than that available from the TENGs, a duty‐cycling technique is successfully demonstrated. The proposed energy harvesting system provides a promising approach to realizing sustainable and autonomous energy sources for various IoT applications.

A Transformer Design for High-Voltage Application Using LLC Resonant Converter

The inductor–inductor–capacitor (LLC) resonant converter is a suitable topology for wide output voltage and load range applications with limited circuit parameters. One of the most significant design boundaries of an LLC resonant converter in high-voltage applications is the parasitic capacitance effect of the main circuit components, particularly the transformer and junction capacitances of the secondary rectifier network. Parasitic capacitance effects are much higher in high-voltage applications than in low-voltage applications. Therefore, the use of an LLC resonant converter is limited to high-voltage applications. This study proposes to reduce the capacitive effects of high-voltage transformers and rectification networks with a multi-winding transformer with an integrated rectifier design and to use it in high-voltage applications with the advantages of the LLC resonant converter. For the proposed prototype, comparative experimental measurements were conducted using a conventional scheme. The measurements validate the reliability of the LLC converter for high-voltage applications, improving the output regulation performance while significantly reducing parasitic capacitances.

Broadband Equivalent Modeling and Common-Mode Voltage Conduction Analysis of Electrochemical Energy Storage System

Electrochemical energy storage system play an important role in the reform of the national energy system and the construction of the energy Internet. Whether small or large capacity battery storage converters, the characteristics of their power electronics can generate high frequency common mode voltage that can be potentially harmful to battery storage system. This paper systematically investigates the common-mode interference (CMI) of electrochemical energy storage system. The mechanism of common-mode interference is revealed, a broadband equivalent circuit model of common-mode voltage in electrochemical energy storage system is established, the effect of parasitic capacitance of the battery on common-mode voltage is simulated and analyzed, and the broadband equivalent circuit model is verified based on laboratory data.

A Deep Learning Approach for Efficient Electromagnetic Analysis of On-Chip Inductor with Dummy Metal Fillings

A deep learning approach for the efficient electromagnetic analysis of an on-chip inductor with dummy metal fillings (DMFs) is proposed. By comparing different activation functions and loss functions, a deep neural network for DMF modeling is built using a smooth maximum unit activation function and log-cosh loss function. The parasitic capacitive effect of DMFs is quickly and accurately extracted though this model, and the effective permittivity can be obtained subsequently. An on-chip inductor containing DMFs with different filling densities is analyzed using this proposed method and compared with the electromagnetic simulation of entire structures. The results validate the accuracy and efficiency of this proposed method.

Piezoelectric Micromachined Ultrasonic Transducers (PMUTs): Performance Metrics, Advancements, and Applications

With the development of technology, systems gravitate towards increasing in their complexity, miniaturization, and level of automation. Amongst these systems, ultrasonic devices have adhered to this trend of advancement. Ultrasonic systems require transducers to generate and sense ultrasonic signals. These transducers heavily impact the system's performance. Advancements in microelectromechanical systems have led to the development of micromachined ultrasonic transducers (MUTs), which are utilized in miniaturized ultrasound systems. Piezoelectric micromachined ultrasonic transducers (PMUTs) exhibit higher capacitance and lower electrical impedance, which enhances the transducer's sensitivity by minimizing the effect of parasitic capacitance and facilitating their integration with low-voltage electronics. PMUTs utilize high-yield batch microfabrication with the use of thin piezoelectric films. The deposition of thin piezoelectric material compatible with complementary metal-oxide semiconductors (CMOS) has opened novel avenues for the development of miniaturized compact systems with the same substrate for application and control electronics. PMUTs offer a wide variety of applications, including medical imaging, fingerprint sensing, range-finding, energy harvesting, and intrabody and underwater communication links. This paper reviews the current research and recent advancements on PMUTs and their applications. This paper investigates in detail the important transduction metrics and critical design parameters for high-performance PMUTs. Piezoelectric materials and microfabrication processes utilized to manufacture PMUTs are discussed. Promising PMUT applications and outlook on future advancements are presented.

Analysis of effects of MOSFET parasitic capacitance on non-synchronous buck converter electromagnetic emission

This paper aims to extract the correlation between parasitic capacitances of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and its influence in Electromagnetic (EM) Emission level of non-synchronous buck converter. In order to validate the proposed concept, the non-synchronous buck converter is designed and validated with dissimilar kind of MOSFETs which have different parasitic specifications. The effect of parasitic capacitance in MOSFET switching and transient characteristics are analyzed with time domain waveforms and the resultant electromagnetic emission due to those switching transients are analyzed and correlated with practical electromagnetic radiated and conducted emission results. The analysis and testing results shows the significant role of MOSFET parasitic capacitances in determining MOSFET switching transients, controlling the magnitude of electromagnetic emission and determining the frequency of EM noise propagation. Along with the time domain and frequency domain analysis the near field Electromagnetic scanning also performed to prove the proposed concept and reason for targeting MOSFET parasitic elements alone to control the EM emission level of the converter. The obtained results provide the evidence of controlling Electromagnetic emissions is possible with optimal selection of MOSFET parasitic capacitances without any additional control or filter circuits.

Single phase transformerless inverter for grid connected photovoltaic system with reduced leakage current

Introduction. Transformerless inverters are of vital importance in the field of grid connected solar photovoltaic systems offering higher efficiency than the conventional one. i.e., using transformer. General grid connected inverters are constituting of transformers requires more area besides the loss in them. Problem. Eliminating transformers can cause leakage current due to the variation of common mode voltage which in turn due to parasitic capacitance effect. Research literature in transformerless inverters has addressed the problems of common mode leakage current issues by offering the study of different inverter topologies like H4, H5, H6 and HERIC etc. utilizing variety of modulation strategies like unipolar, bipolar pulse width modulations. Goal. The paper significantly presents a new transformerless inverter topology, analyzes common mode voltage and leakage current behavior of the system. The simulation is carried out for comparing the leakage current profiles with other transformerless inverter topologies in literature. Novelty. This paper gives an impression of the efficient transformerless inverter for grid connected photovoltaic system. Results. The various inverter topologies full bridge with different pulse width modulation techniques are analyzed and to determine the common mode voltages and leakage currents.

An Accurate VSI Nonlinearity Modeling and Compensation Method Accounting for DC-Link Voltage Variation Based on LUT

The nonlinearity of the voltage source inverter (VSI) leads to the error between output voltage and reference voltage, and causes the phase current harmonics. It is necessary to compensate its influence in the fields such as parameter identification, sensorless control, and servo drives. In this article, an industrial solution for VSI nonlinear compensation method based on lookup table (LUT) is introduced. The characteristics of semiconductor devices, equivalent dead-time and influence of parasitic capacitance effects are calculated quantitatively though injecting increase and decrease current during self-commissioning process. The critical current value for parasitic capacitor and the variation of equivalent dead time are verified through different distorted voltage curves. Considering dc-link voltage variation is irresistible for industrial products, 3-D linear interpolation is adopted to compensate the variation of VSI nonlinearity under different voltage conditions. Proposed LUT method does not require VSI datasheet and complicated calculation formula during implementation. Experiments are carried out on a commercial permanent magnet synchronous motor drive system to verify the proposed LUT method.

Measurement of the effect of parasitic capacitance in minimum ignition energy spark generation circuits

To accurately measure electrostatic discharge energy, a resistive-capacitive voltage discharge approach was used to measure the parasitic capacitance in a circuit. As a result, an output-stage parasitic capacitance in the circuit during the discharge process and a non-negligible storage-stage parasitic capacitance during the charging process were identified. By comparing the data obtained from the resistive-capacitive discharge voltage model and spark current RCL circuit model, the maximum relative deviation from the total circuit capacitance was 5.4% for both approaches. A model based on graded-stage parasitic capacitance was established to analyze the effect of this capacitance on discharge energy. The energy stored in the charging process increased because of the storage-stage parasitic capacitance, and the discharge energy decreased because of the output-stage parasitic capacitance. The energy calculated by the graded parasitic capacitance model was larger than that calculated by the single-stage parasitic capacitance model, with a maximum relative deviation of 36.7% under the test conditions. The smaller the charging capacitor, the more evident the effect of the parasitic capacitance on the discharge energy.

On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node.

This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 57% of the wire diameter in order to have a folding ratio better than a FinFET with the same total height and footprint. Considering the technological constraints for the gate oxide and metal gate thicknesses, the minimum intersheet/interwire spacing should be in the range of 7 to 8 nm. Then, the VNSFET structure has the advantage of boosting the chip density over the FinFET ones only when the sheet width is wider than 8 nm. On the other hand, the VNWFET structure may have a better footprint sizing than the FinFET ones only when the nanowire diameter is larger than 14 nm. In addition, considering the different channel mobilities along the different surface directions of the silicon channel and also some other unfavorable natures such as more complicated processes, more significant surface roughness scattering, and parasitic capacitance effects, the nanosheet transistor does not show superior scaling capability than the FinFET counterpart when approaching the ultimate technology node.