Parasitic Capacitance Cancellation Research Articles

Comments on “Common-Mode Noise Reduction by Parasitics Capacitance Cancellation in the Three-Phase Inverter”

This article comments on the published article titled “Common-mode noise reduction by parasitics capacitance cancellation in the three-phase inverter” authored by Zhang and Wu (2019). The three-terminal electromagnetic interference (EMI) filter can effectively suppress the EMI noise on the output side in the paper. The numerical analysis and the relationship of converting negative inductance into capacitance at high frequency are discussed in detail. Zhang and Wu (2019) presented a parasitic capacitance cancellation method to reduce the conducted emissions exiting a three-phase inverter. The idea of parasitic capacitance cancellation is not novel, and Wang and Lee (2007, 2010) originally applied it to reduce the common mode noise exiting a boost PFC converter. The parasitic capacitance cancellation of inductors is discussed in papers by Neugebauer and Perreault (2006) and Piboonwattanakit and Khan-Ngern (2008). These papers should be cited in the introduction and the references.

Preparation and Characterization of Orthorhombic AgMn Alloys by the Pulsed Laser Welding Technique

AbstractHerein, AgMn alloys are prepared by the pulsed laser welding technique in an argon atmosphere. The effect of the laser pulses width and stoichiometric composition of the alloys on the structural, compositional, morphological, and electrical properties are investigated. In contrast to the traditional preparation techniques which reveal cubic structure of AgMn alloys, the pulsed laser welding technique reveals the orthorhombic phase of the alloys. The lattice parameters of the orthorhombic phase of AgMn are . It is observed that pulse widths of 50 ms are the optimum from preparing these alloys. From an electrical point of view, the AgMn alloys exhibit negative dielectric constant and negative conductance effect in the microwave frequency domain. The impedance spectroscopy analyses in the frequency domain of 0.01–1.80 GHz have shown that AgMn alloys can be employed as band filters with return loss value of ≈16 dB. The features of the AgMn alloys which are achieved by the pulsed laser welding technique nominate them for use as negative capacitance and negative conductance transistors. These devices are suitable for noise reduction and parasitic capacitance cancellation.

Capacitive Readout System for Micro Sensors and Actuators With Automatic Parasitic Cancellation

In this article, a capacitive readout system with automatic parasitic capacitance cancellation function is designed and implemented. The readout system is implemented with discrete components on a board level. The parasitic cancellation is realized by matching a digital programmable capacitor to the parasitic capacitance using a PI controller. The function of the readout system is verified by using standard ceramic capacitors and a MEMS micromirror device. Capacitance measurements up to 35 pF for ceramic capacitors are performed, the maximum error between the measurement results of the circuit and an LCR meter is 0.07 pF. For MEMS micromirror, the circuit cancels the parasitic capacitance of 32.63 pF and realizes a measurement error within 0.06 pF. The proposed system can be used as a proof-of-concept platform demonstrating the feasibility of the generic parasitic cancellation method for MEMS sensors and actuators.

PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The PLL consisting of a phase frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO) makes the driving frequency to be locked at the resonant frequency. The resonator is modeled by Butterworth–Van Dyke equivalent circuit model with motional resistance of 72.8 kΩ, capacitance of 6.19 fF, inductance of 79.4 mH, and parasitic parallel capacitance of 2.59 pF. To mitigate the magnitude and phase distortion in the resonator frequency response, it is necessary to compensate for the parasitic capacitance. The proposed automatic parasitic capacitance cancellation loop is operated in the open-loop mode. In the automatic parasitic capacitance cancellation phase, the outputs of the transimpedance amplifier (TIA) at the lower and higher frequency than the resonant frequency (VH and VL), are compared, and the programmable compensation capacitor array matches the VH and VL using binary-searched algorithm to cancel the parallel parasitic capacitance. The automatic gain control (AGC) loop keeps the oscillation at the suitable amplitude, and the AGC output can be used as a measurement of the motional resistance. The AGC loop is also digitally controlled. The proposed resonator driving IC is designed in a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm2. The simulated phase noise is −61.1 dBc/Hz at 1 kHz and the quality factor ( Q-factor) is 59,590.

Design of Au/Cdbr2/Au as Negative Capacitance Devices and as Band Filters Suitable for 4G Technologies

Herein, cadmium bromide thin film devices are designed for possible use in communication technology. The 1.0 μm thin layer of CdBr2 is sandwiched between two Au (1.0 μm thick) layers using the thermal evaporation technique under a vacuum pressure of 10-5 mbar. The Au/CdBr2/Au devices are structurally morphologically and electrically characterized. It is observed that the hexagonal cadmium bromide exhibits large lattice mismatches with cubic Au substrates. The randomly distributed nano- rod like grains is accompanied with average surface roughness of ~26 nm. When an ac signal of low amplitude is imposed between the terminals of the Au/CdBr2/Au devices, a negative capacitance effect in the frequency domain of 10-1800 MHz is observed. In addition, analysis of the impedance spectra in the same domain has shown that the device behaves as band pass/stop filters suitable for 4G technology. The microwave based standard analysis of the Au/CdBr2/Au band filters have shown that it displays a notch (fco) frequency of 2.0 GHz. The cutoff frequency at fco reaches 7.86 GHz. The features of the Au/CdBr2/Au devices nominate it for use as microwave resonators and as negative capacitance devices suitable for; 4G technology, noise reduction and for parasitic capacitance cancellation.

Design and Characterization of MoO3/Mg/MoO3 Interfaces

In this article, the physical design and performance of stacked layers of MoO3/Mg/MoO3 (MMM) is investigated by means of X-ray diffraction and biasing-dependent impedance spectroscopy techniques. The amorphous MMM films which are coated onto Au thin-film substrates in a vacuum media of 10−5 mbar are observed to exhibit metal oxide semiconductor (MOS) characteristics. The pMOS and nMOS inversion channels are initiated at biasing voltages of −2.0 and +2.0 V, respectively. In addition, the biasing-dependent spectral analysis of the device has shown that the negativity of the capacitance could be linearly increased or decreased based on the MOS mode and applied voltage value. The engineering of the negative capacitance effect in the device makes it preferable to use as voltage controlled linear oscillators which can be employed for noise reducing and parasitic capacitance cancellation. In addition, the analyses of biasing-dependent reflection coefficient spectra in the frequency domain of 0.01–1.80 GHz have shown that the MMM device exhibits features of bandpass/stop features below and above 1.40 GHz, respectively. The degree of wave transmission can be attenuated by the biasing voltage in the respective channel.

Effects of Au nanoslabs on the performance of CdO thin films designed for optoelectronic applications

Abstract In this work, the effect of 50 nm thick gold nanosheets on the structural, morphological, optical and electrical properties of stacked layers of CdO are investigated. The insertion of Au nanoslabs decreased the lattice parameters of the cubic unit cells of CdO. It also decreased the microstrain, the defect density, the stacking fault percentage and increased the crystallite and grain sizes. Optically, the light absorbability is enhanced, the energy band gap is shrunk and the optical conductivity is increased. The optical conductivity parameters presented by scattering time, plasmon frequency, drift mobility and free carrier density are all engineered via participation of Au nanosheets. On the other hand, electrical measurements in the frequency domain of 0.01–1.80 GHz indicated that the Au nanosheets forced the capacitance spectra to exhibit negative values and increased the electrical conductivity in the studied frequency domain. The terahertz cutoff frequency is tuned in the range of 5.0–22.0 THz indicating the applicability of the CdO/Au/CdO (CAC) films as terahertz filters. The direct current electrical conductivity measurements have shown that while the CC samples exhibit nondegenerate extrinsic nature of conduction, the CAC samples displayed degenerate/nondegenerate transitions at 400 K. With the feature of negative capacitance that can be used for noise reduction and parasitic capacitance cancellation, the CAC films can be regarded as promising structure for multifunctional device applications.

Common-Mode Noise Reduction by Parasitic Capacitance Cancellation in the Three-Phase Inverter

Electromagnetic interference (EMI) has drawn great attention in recent years. In this particular case, it is generated by the three-phase inverters in power electronics applications due to the power devices turning on and off at high frequency. In this paper, in order to alleviate such EMI noise, a high-frequency common-mode (CM) equivalent model is developed, which leverages the effect of parasitic parameters. Meanwhile, in order to eliminate the effect of the parasitic capacitance between the phase node and ground, which is the cause of main CM noise propagation, a coupled inductor connected with a capacitor circuit, which is equivalent to a negative capacitance is proposed. The parameter calculation for the passive negative capacitance circuit is given in detail. The experimental results demonstrated the effectiveness of the circuitry structure and its ability to reduce CM noise.

Influence of high frequency loss in an accumulating choke of boost power factor correction conventers under using of non-filter cancellation of conductive noise

In the paper, the influence of high frequency loss in a real accumulating input choke (AIC) of boost power factor correction converters on the capacitance in the circuit of converter’s parasitic capacitance cancellation is considered. The parasitic capacitance mentioned above causes the spreading of noise CM voltage generating by a converter, into a main. Under the studying of high frequency loss influence in the AIC it was analyzed the equivalent circuit of the converter containing the real AIC (with parasitic winding capacitance and high frequency loss) as a source of CM noise. The expression for the optimal capacitance which provides minimization of converters common mode noise was obtained, and correctness of the said expression was checked with the aid of PSPICE. The simulation confirmed the correctness of the expression mentioned above. As a result of investigations carried out and described in the paper it is estimated that for real values of the AIC parasitic parameters the optimal capacitance does not practically depend on its high frequency loss.

Analysis and Applications of Parasitic Capacitance Cancellation Techniques for EMI Suppression

This paper reviews and analyzes five parasitic capacitance cancellation methods. Critical parameters and constraints determining the cancellation frequency ranges are identified, and the effective frequency range for each cancellation method is derived based on these constraints. Due to these constraints, each method has specific advantages for certain applications. The cancellation techniques, which all make use of either mutual capacitance or mutual inductance, are applied to different applications based on their advantages, and the experiments are carried out to verify the analysis.

A K-Band High-Gain Down-Conversion Mixer in 0.18 $\mu$m CMOS Technology

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A high gain CMOS down conversion mixer with a gain enhancement technique is presented. This technique includes negative resistance generation, parasitic capacitance cancellation and current-injection. These are implemented with an additional circuitry. This mixer has a conversion gain of 9.12 dB, input 1 dB compression point of <formula formulatype="inline"><tex Notation="TeX">${-}11$</tex> </formula> dBm at 24 GHz, while consuming 16.2 mW from 1.8 V supply. Between 22 and 26 GHz, the LO-to-RF and RF-to-LO isolations are better than 35 dB and 26 dB, respectively. </para>

Winding Capacitance Cancellation forThree-Phase EMC Input Filters

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Techniques have been presented in the literature for canceling stray capacitances for inductors in single-phase power filters. With the same aim, the alternatives provided by three-phase systems are explored here. A thorough theoretical analysis is presented, where pros and cons of parasitic capacitance cancellation networks are highlighted and improvements are proposed. A systematic mathematical procedure to evaluate impedances for different noise modes in three-phase circuits is presented. The influence of parasitic effects is accessed and asymmetric capacitance cancellation is proposed, facilitating applications in switched power circuits. Experimental results are shown demonstrating the effectiveness of the presented techniques in an electromagnetic compatibility filtering application. </para>

Parasitic capacitance cancellation in filter inductors

This paper introduces a technique for improving the high-frequency performance of filter inductors and common-mode chokes by cancelling out the effects of parasitic capacitance. This technique uses additional passive components to inject a compensation current that cancels the parasitic current, thereby improving high-frequency filtering performance. Two implementation approaches for this technique are introduced. The first implementation achieves cancellation using an additional small winding on the filter inductor and a small capacitor. This approach is effective where very high coupling of the windings can be achieved or where only moderate performance improvements are required. The second implementation utilizes a small radio frequency transformer in parallel with the filter inductor to inject cancellation currents from the compensation capacitor. This technique requires an additional component (the transformer), but can provide a high degree of cancellation. Experimental results confirm the theory in both implementations.