Parametric Yield Prediction Research Articles

An Efficient Prediction Framework for Multi-parametric Yield Based on Uncertainty of Performance-Relevant Structure

Due to the aggressive shrinking of integrated circuit (IC) fabrication technology, variability in design parameters leads to significant yield loss. Therefore, efficient parametric yield prediction has been a critical task for today’s ICs, especially when multiple performances are considered simultaneously. However, most of the previous yield prediction works have failed to take into account uncertainty of performance-relevant structures. Neglecting the uncertainty effects will tend to result in predictive accuracy loss. To avoid the issue, this paper proposes a multi-parametric yield prediction framework based on the uncertainty of performance-relevant structures. In the proposed framework, saddle point estimation and mixed copula function are applied to maintain the uncertainty-relevant structures among performance metrics and predict the multi-parametric yield accurately. First, the framework constructs a general statistical model for performance metrics to illustrate the uncertainty of performance-relevant structures. The general model is explicitly expressed in terms of underlying process, voltage, and temperature (PVT) parameters. Then, based on the general performance model and taking total leakage current and gate delay for example, their marginal distributions are estimated by assuming the PVT parameters as normal random variables. Finally, a mixed copula-based yield prediction method is suggested to solve the uncertainty-relevant structure problem. Experimental results demonstrate that the proposed yield prediction framework is capable of predicting multi-parametric yield under arbitrary performance-relevant structures. Compared to Monte Carlo (MC) analysis, the relative errors of yield prediction are less than 5%, which means the framework has good accuracy and efficiency.

An efficient prediction framework for multi-parametric yield analysis under parameter variations

Due to continuous process scaling, process, voltage, and temperature (PVT) parameter variations have become one of the most problematic issues in circuit design. The resulting correlations among performance metrics lead to a significant parametric yield loss. Previous algorithms on parametric yield prediction are limited to predicting a single-parametric yield or performing balanced optimization for several single-parametric yields. Consequently, these methods fail to predict the multi-parametric yield that optimizes multiple performance metrics simultaneously, which may result in significant accuracy loss. In this paper we suggest an efficient multi-parametric yield prediction framework, in which multiple performance metrics are considered as simultaneous constraint conditions for parametric yield prediction, to maintain the correlations among metrics. First, the framework models the performance metrics in terms of PVT parameter variations by using the adaptive elastic net (AEN) method. Then the parametric yield for a single performance metric can be predicted through the computation of the cumulative distribution function (CDF) based on the multiplication theorem and the Markov chain Monte Carlo (MCMC) method. Finally, a copula-based parametric yield prediction procedure has been developed to solve the multi-parametric yield prediction problem, and to generate an accurate yield estimate. Experimental results demonstrate that the proposed multi-parametric yield prediction framework is able to provide the designer with either an accurate value for parametric yield under specific performance limits, or a multi-parametric yield surface under all ranges of performance limits.

Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty

Due to the hard-to-measure distributions of real process data, it is difficult to provide accurate parametric yield prediction for modern circuit design. Most existing approaches are not able to handle the uncertain distribution properties coming from the process data. Other approaches are inadequate in considering correlations among the distributions of variations. This paper suggests a new approach that not only takes care of correlations among distributions but also provides a low-cost and efficient computation scheme. The proposed method approximates the parameter variations with Chebyshev affine arithmetic (CAA) to capture both the uncertainty and nonlinearity in a cumulative distribution function. The CAA-based probabilistic range presentation describes, both fully and partially, specified process and environmental parameters. Thus, we are able to predict the probability bounds for leakage consumption with unknown dependences among variations. The end result is the chip-level parametric yield estimation based on leakage prediction. Experimental results demonstrate that the new approach provides a reliable bound estimation, which leads to a 20% yield improvement compared with only using the intervals of partially specified uncertainties.

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. The three methods are complementary in that they are designed to target different process variation conditions that occur in practice. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Timing analysis results in the face of statistical temperature and Vdd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results

Analytical yield prediction considering leakage/performance correlation

In addition to traditional constraints on frequency, leakage current has emerged as a stringent constraint in modern processor designs. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must consider the dependence of leakage current on frequency. In this paper, a new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability is presented. A closed-form equation for total chip leakage that models the dependence of the leakage current distribution on different process parameters is developed. The proposed analytical expression is obtained directly from pertinent design information and includes both subthreshold and gate leakage currents. Using this model, an integrated approach to accurately estimate the yield loss when both frequency and power limits are imposed on a design is then presented. The proposed method demonstrates the importance of considering both these limiting factors while calculating the yield of a lot

Modeling and Analysis of Parametric Yield under Power and Performance Constraints

Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate leakage currents. This model underlies an integrated approach to accurately estimating yield loss for a design with both frequency and power limits.

Statistically based parametric yield prediction for integrated circuits

This paper presents a novel procedure for predicting integrated circuit parametric performance and yield when provided with sample transistor test results and a circuit schematic. Two enhancements to the existing Monte Carlo simulation procedures are described: (1) a multivariate nested model is used to reproduce random process-induced device-variations, rather than the multivariate multinormal model typically used, and (2) the stochastic Monte Carlo method for mapping process variability into a performance distribution is replaced with a deterministic mapping technique. The use of multivariate nested distributions allows estimation not only of correlation between various model parameters, but also allows each of those variations to be apportioned among the various stages of the process (i.e., wafer to wafer, lot to lot, etc.). This allows matched devices to be more accurately simulated, without having to develop customized models for each configuration of matching, and provides focus for process improvement efforts into those areas with the maximum potential reward. The use of deterministic mapping provides simulation results which are repeatable and do not rely on chance to insure that the process parameter space has been evenly explored. A software package which implements the entire procedure has been written in C++.

Parametric yield prediction of complex, mixed-signal IC's

A method is presented which helps the designer predict the parametric yield of complex mixed-signal IC's in a reasonable time. It builds on previous approaches to IC yield prediction employing a Monte Carlo approach for flexibility, with behavioral simulation and response surfaces for speed. To analyze complex mixed-signal IC's, a novel feature termed the correction layer is introduced. Complex mixed-signal IC's have tests which are highly nonlinear. Consequently, it can be difficult to build accurate response surfaces whose response variables are the results of such tests. The correction layer is introduced to overcome this problem. It enables a response surface to be accurately used by the method. A commercial hard disk drive IC is analyzed as an example to show the necessity of having the correction layer in order to produce accurate parametric yield predictions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Manufacturing-based simulation: An overview

An overview is given of the VLSI fabrication process in order to define some terms and identify the primary causes of yield loss. The sources of disturbances in the manufacturing process are discussed next. It is seen that functional yield is dependent on the distribution of local disturbances in the process, such as spot defects on a mask and oxide pinholes, while parametric performance is dependent on global disturbances in the process, such as mask misalignment nd oxide growth rates. Further evaluation of manufacturing yield is based on the evaluation of functional and parametric yield. Methods for evaluating functional yield are presented, and applications of these methods are discussed. Applications of parametric yield prediction are presented. It is shown how parametric performance simulation forms the basis for an improved worst-case analysis methodology.

Statistical Modeling for Efficient Parametric Yield Estimation of MOS VLSI Circuits

Large statistical variations are often found in the performance of VLSI circuits; as a result, only a fraction of the circuits manufactured may meet performance goals. An automated system has been developed to obtain the process statistical variations and extract SPICE model parameters for a large number of MOS devices. Device length and width, oxide capacitance, and flat-band voltage are shown to be the principal process factors responsible for the statistical variation of device characteristics. Intradie variations are much smaller than the interdie variations, therefore, only the interdie variations are responsible for variations its circuit performance. This accurate and simple statistical modeling approach uses only four statistical variables, and thus enables the development of a very computationally efficient statistical parametric yield estimator (SPYE). A linear approximation for the yield body boundary is used to make an accurate prediction of parametric yield. With the addition of temperature and supply voltage as operating condition variables, a maximum of seven simulations are required; only slightly more than the three to five required for "worst case analysis". The method has also been adapted statistical parametric specification of standard cells; performance ranges of circuit building blocks can be characterized once the statistical variations of process-dependent parameters are known. Predicted performance variations from SPYE have been compared with measured variations in delay and power consumption for a 7000-gate n-MOS inverter chain. Agreement with the mean delay and power are better than 5 percent where SPICE model parameters were obtained from the same slice used for circuit characterization. Excellent agreement was obtained in the predicted spread in the circuit delay and power consumption using measured variations in the statistical variables.

Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits

Large statistical variations are often found in the performance of VLSI circuits; as a result, only a fraction of the circuits manufactured may meet performance goals. An automated system has been developed to obtain the process statistical variations and extract SPICE model parameters for a large number of MOS devices. Device length and width, oxide capacitance, and flat-band voltage are shown to be the principal process factors responsible for the statistical variation of device characteristics. Intradie variations are much smaller than the interdie variations, therefore, only the interdie variations are responsible for variations in circuit performance. This accurate and simple statistical modeling approach uses only four statistical variables, and thus enables the development of a very computationally efficient statistical parametric yield estimator (SPYE). A linear approximation for the yield body boundary is used to make an accurate prediction of parametric yield. With the addition of temperature and supply voltage as operating condition variables, a maximum of seven simulations are required; only slightly more than the three to five required for worst case analysis. The method has also been adapted statistical parametric specification of standard cells; performance ranges of circuit building blocks can be characterized once the statistical variations of process-dependent parameters are known. Predicted performance variations from SPYE have been compared with measured variations in delay and power consumption for a 7000-gate n-MOS inverter chain. Agreement with the mean delay and power are better than 5 percent where SPICE model parameters were obtained from the same slice used for circuit characterization. Excellent agreement was obtained in the predicted spread in the circuit delay and power consumption using measured variations in the statistical variables.