Parameter Extraction Procedure Research Articles

Analysis and Design of Two-Dimensional Resonant-Type Composite Right/Left-Handed Transmission Lines With Compact Gain-Enhanced Resonant Antennas

A two-dimensional (2-D) resonant-type composite right/left-handed transmission line (CRLH TL) is proposed consisting of complementary split-ring resonators (CSRRs) and series capacitive gaps. For characterization and design, the circuit parameters extraction procedure for the TL element is derived, and the unique 2-D dispersion characteristics (CRLH nature) are analytically investigated and further verified by eigenmode analysis performed in HFSS and phase analysis in ADS. A good agreement of dispersion diagram is obtained between full-wave simulation and theory. To demonstrate potential applications, two types of microstrip antennas have been designed, fabricated, and measured following the design procedures that are established. In the first design, a multifrequency antenna operating at three resonant modes of n = -1, n = 0, and n = + 1 is designed by arranging a 2×2 CRLH array in a conventional patch. The frequency ratios between these modes are 1.98 and 1.15, respectively, which can be arbitrarily modulated by controlling the proportion between the CRLH section and the patch. In the second design, zeroth-order resonant antennas are researched. These antennas exhibit simultaneously a leaky-wave characteristic and an omnidirectional radiation behavior, distinguishing them significantly from any previous designs. In both cases, the antenna gain is comparable, and the cell structure is uniplanar and electrically small.

Thyristor Compact Modeling based on Gummel-Poon Model Including Parameter Extraction Procedure

this paper, an improved approach for the modeling of power thyristors is presented. A modified two-transistor configuration based on the Gummel-Poon model is applied. This model takes into account the conductivity modulation and carrier-carrier scattering by using nonlinear current sources. The current gain of the transistor is studied relating it to the injection level in order to provide a more insight of some SPICE parameters. The design parameters of the thyristor are related to circuit parameters using some analytical expressions. Then, the SPICE model parameters are extracted using Silvaco. The simulation results are compared with measurements showing good agreement indicating that the developed model could efficiently describe the performance of the thyristor under various practical operating conditions.

Accurate optical parameter extraction procedure for broadband near-infrared spectroscopy of brain matter

Modeling behavior of broadband (30 to 1000 MHz) frequency modulated near-infrared (NIR) photons through a phantom is the basis for accurate extraction of optical absorption and scattering parameters of biological turbid media. Photon dynamics in a phantom are predicted using both analytical and numerical simulation and are related to the measured insertion loss (IL) and insertion phase (IP) for a given geometry based on phantom optical parameters. Accuracy of the extracted optical parameters using finite element method (FEM) simulation is compared to baseline analytical calculations from the diffusion equation (DE) for homogenous brain phantoms. NIR spectroscopy is performed using custom-designed, broadband, free-space optical transmitter (Tx) and receiver (Rx) modules that are developed for photon migration at wavelengths of 680, 780, and 820 nm. Differential detection between two optical Rx locations separated by 0.3 cm is employed to eliminate systemic artifacts associated with interfaces of the optical Tx and Rx with the phantoms. Optical parameter extraction is achieved for four solid phantom samples using the least-square-error method in MATLAB (for DE) and COMSOL (for FEM) simulation by fitting data to measured results over broadband and narrowband frequency modulation. Confidence in numerical modeling of the photonic behavior using FEM has been established here by comparing the transmission mode's experimental results with the predictions made by DE and FEM for known commercial solid brain phantoms.

Gate Leakage Current in GaN HEMT’s: A Degradation Modeling Approach

In this paper we p resent an empirical preliminary model able to simulate the degradation with t ime in the gate leakage current in GaN HEMT devices. The model is based on extensive reverse and forward current measurements, carried out on a wide range of different device designs and under different bias, performed over aged transistors by III-V Lab (Alcatel-Thales) within the European KORRIGA N. A closed form expression for the reverse gate current, depending on time, as well as the expression parameters extraction procedure are presented. The experimental and simulated results presented illustrate the validity of the model as well as it's usefulness in reliability studies.

Carbon Nano-Onion Ultracapacitor Model

ABSTRACTThis paper describes a novel ultracapacitor made from carbon nano-onions. Characterization of the material was performed including measurement of the impedance spectra and cyclic voltammetry. A new ultracapacitor model composed of an LRC circuit and a constant phase element was developed along with a parameter extraction procedure. The model was validated using experimental data and simulation.

Accurate Compact Modeling for Sub-20-nm nand Flash Cell Array Simulation Using the PSP Model

In this paper, we have developed a new floating-gate-type Flash cell compact model based on the channel potential by using PSP metal-oxide-semiconductor description. Cell-to-cell coupling, Fowler–Nordheim tunneling, and new leakage current formulas have been implemented on Verilog-A compact model. The channel potential calculation of the PSP model enables accurate modeling of channel coupling and leakage currents which are associated with the boosted channel. In addition, the model parameter extraction procedure through 3-D technology computer-aided design (TCAD) and SPICE simulation is presented. The simulation results agree well with measured data of sub-20-nm nand cells.

Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits

A copper chemical mechanical polishing (Cu CMP) process is reviewed and analyzed from the view of chemical physics. Three steps Cu CMP process modeling is set up based on the actual process of manufacturing and pattern-density-step-height (PDSH) modeling from MIT. To catch the pattern dependency, a 65 nm testing chip is designed and processed in the foundry. Following the model parameter extraction procedure, the model parameters are extracted and verified by testing data from the 65 nm testing chip. A comparison of results between the model predictions and test data show that the former has the same trend as the latter and the largest deviation is less than 5 nm. Third party testing data gives further evidence to support the great performance of model parameter optimization. Since precise CMP process modeling is used for the design of manufacturability (DFM) checks, critical hotspots are displayed and eliminated, which will assure good yield and production capacity of IC.

An improved compact model for CMOS cross-shaped Hall-effect sensor including offset and temperature effects

A compact model of a cross-shaped horizontal integrated Hall-effect sensor is presented in this paper. Compared to existing models, reliability is improved, especially to simulate systems in which biasing and measurement circuits are not independent. The Hall device model core, already published, is based on a network of six non-linear resistances and four Hall voltage sources, and includes only 11 physical parameters. In this paper, in order to improve model predictivity, four additional parameters have been added to take the offset issue into account. In addition, variations of parameters with temperature are also addressed. The model is implemented in Verilog-A and has been validated through experiments carried out on Hall devices designed in a CMOS 0.35μm technology. The parameters extraction procedure is detailed and the maximum error between simulations and experimental data is less than 1 % for a wide range of biasing currents and temperatures.

Analysis and modeling of on-chip transformers under two ground conditions

Two fabricated on-chip transformers under different ground conditions (i.e., CG and IG types) have been measured to compare their different characteristics. With the aid of the electromagnetic (EM) solver, we have analyzed the differences from the electric and magnetic aspects, and different effects in these aspects can be described with the lumped capacitor and inductor from the perspective of the equivalent circuit model. A physics-based equivalent circuit model is proposed to model transformers under different ground conditions. In addition, the simple parameter extraction procedure for the corresponding model is also provided. All the model parameters are extracted and agree with the analysis. In order to verify the model's validity and accuracy, we have compared the modeled and measured S-parameters, and an excellent agreement has been found over a broad frequency range.

Genetic algorithm-based neural-network modeling approach applied to AlGaN/GaN devices

An accurate equivalent circuit large-signal model (ECLSM) for AlGaN-GaN high electron mobility transistor (HEMT) is presented. The model is derived from a distributed small-signal model that efficiently describes the physics of the device. A genetic neural-network-based model for the gate and drain currents and charges is presented along with its parameters extraction procedure. This model is embedded in the ECLSM, which is then implemented in CAD software and validated by pulsed and continuous large-signal measurements of on-wafer 8 × 125-μm GaN on SiC substrate HEMT. Pulsed IV simulations show that the model can efficiently describe the bias dependency of trapping and self-heating effects. Single- and two-tone simulation results show that the model can accurately predict the output power and its harmonics and the associated intermodulation distortion (IMD) under different input-power and bias conditions. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.

A new equivalent circuit model for on-chip spiral transformers in CMOS RFICs

A new compact model has been introduced to model on-chip spiral transformers. Unlike conventional models, which are often a compound of two spiral inductor models (i.e., the combination of two coupled Π or 2-Π sub-circuits), our new model only uses 12 elements to model the whole structure in the form of T topology. The new model is based on the physical meaning, and the process of model derivation is also presented. In addition, a simple parameter extraction procedure is proposed to get the elements' values without any fitting and optimization. In this procedure, a new method has been developed for the parameter extraction of the ladder circuit, which is commonly used to represent the skin effect. In order to verify the model's validity and accuracy, we have compared the simulated and measured self-inductance, quality factor, coupling coefficient and insertion loss, and an excellent agreement has been found over a broad frequency range up to the resonant frequency.

Analysis of modeling approaches for on-chip spiral inductors

The recent modeling approaches for on-chip spiral inductors are extensively investigated and compared. The key features of the models are detailedly analyzed. By actual implementation of each model's parameter extraction procedure, the pros and cons of equivalent circuit topologies, parameter extraction techniques, and fitting capacity of models are provided, including 1-π, 2-π, and T-models. 1-π models and T-models are proved to be adequate for modeling distributed effect. 2-π models are more convenient in fitting asymmetric inductors. The transfer function of the spiral inductor is employed in the singularity analysis of the models. The proposals are verified by measured the S-parameters of 10 fabricated CMOS spiral inductors up to 40 GHz. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2012. © 2012 Wiley Periodicals, Inc.

Measurement technique for the thermal properties of thin-film diaphragms embedded in calorimetric flow sensors

In diaphragm-based micromachined calorimetric flow sensors, convective heat transfer through the test fluid competes with the spurious heat shunt induced by the thin-film diaphragm where heating and temperature sensing elements are embedded. Consequently, accurate knowledge of thermal conductivity, thermal diffusivity, and emissivity of the diaphragm is mandatory for design, simulation, optimization, and characterization of such devices. However, these parameters can differ considerably from those stated for bulk material and they typically depend on the production process. We developed a novel technique to extract the thermal thin-film properties directly from measurements carried out on calorimetric flow sensors. Here, the heat transfer frequency response from the heater to the spatially separated temperature sensors is measured and compared to a theoretically obtained relationship arising from an extensive two-dimensional analytical model. The model covers the heat generation by the resistive heater, the heat conduction within the diaphragm, the radiation loss at the diaphragm’s surface, and the heat sink caused by the supporting silicon frame. This contribution summarizes the analytical heat transfer analysis in the microstructure and its verification by a computer numerical model, the measurement setup, and the associated thermal parameter extraction procedure. Furthermore, we report on measurement results for the thermal conductivity, thermal diffusivity, and effective emissivity obtained from calorimetric flow sensor specimens featuring dielectric thin-film diaphragms made of plasma enhanced chemical vapor deposition silicon nitride.

Patterned electrode vertical field effect transistor: Theory and experiment

We present a theoretical and experimental investigation of the recently reported new architecture of a patterned electrode vertical field effect transistor (PE-VFET). The investigation focuses on the role of the embedded source electrode architecture in the device behavior. Current-voltage characteristics was unraveled through the use of a self-consistent numerical simulation resulting in guidelines for the PE-VFET architecture regarding the On/Off current ratio, output current density, and apparent threshold voltage. Current modulation characteristics are obtained through the formation of virtual contacts at the PE nano-features (i.e., perforations) under gate bias, which lead to the formation of vertical channels under drain bias. As the vertical channel is formed the device characteristics change from contact-limited to space-charge-limited. The analytical model strength is shown with the parameter extraction procedure applied to a measured PE-VFET device fabricated using block copolymer lithography and with the appropriate simulation results.

A design-oriented methodology for accurate modeling of on-chip interconnects

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.

Parameter Extraction Procedure for Vertical SiC Power JFET

A practical parameter extraction procedure for a power silicon carbide (SiC) junction field-effect transistor (JFET) is presented. The carrier mobility and carrier concentration are very important parameters, strongly affecting the device current capability and dynamic characteristics for a given design. When modeling JFETs, the values of these parameters are usually based on assumptions and given by a vendor in a range. As a result, model accuracy is compromised. In this paper, a step-by-step parameter extraction procedure is described that includes the extraction of mobility and carrier concentration in the channel and drift regions based on knowledge of device geometrical parameters. For the first time, carrier mobilities in the channel and drift regions of a power JFET are extracted individually. It is found that channel and drift region mobilities can be very different for a given device since they are strongly dependent on the fabrication process. The separate extraction of these two mobilities can also improve model accuracy in the case of imperfect knowledge of the device geometry. The developed procedure includes the extraction of empirical parameters describing the temperature dependence of mobilities in the channel and drift regions. A simple static <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characterization and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> measurements are the only measurements required for the parameter extraction. In this paper, the procedure is experimentally validated for both normally off (enhancement mode) and normally on (depletion mode) JFETs.

Complete Time-Domain Diode Modeling: Application to Off-Chip and On-Chip Protection Devices

Protection elements are commonly used in electronic systems: digital integrated circuits (ICs) include built-in electrostatic discharge protection devices, and sensitive lines or printed circuit boards traces are often protected using discrete elements, such as clamping or Zener diodes. In order to know if a perturbation is able to disturb or damage ICs, the actual level of signal entering the digital core of the components must be accurately determined, taking into account all the effects of the protection devices. Thus, assessing the perturbation signal at IC core level requires accurate models of the protection elements, even in the case they are inactive. Therefore, this paper focuses on the experimental and theoretical evaluation of the protective behaviors and parasitic effects of these elements. Some limitations of the standard SPICE diode and IBIS models are discussed, and a modeling methodology is presented. Based on a time-domain characterization method associated with a parameter-extraction procedure for enhanced SPICE diode models, the methodology is applied to both discrete and on-chip protection devices and has a good agreement with measurement.

The power law J–V model of an illuminated solar cell

We have earlier introduced the power law equation, j=1−(1− γ) v− γv m , where j=J/J sc and v= V/V ∝ , to simplify determination of the J–V curve, fill-factor and peak power point of an illuminated solar cell from a few measurements as well as physical parameters. However, the validity of the various formulae and parameter extraction procedure was established for a limited class of cells, having moderately convex J– V curves with fill-factors of 0.56–0.77 and obeying single exponential theory with bias independent photocurrent. This paper presents a thorough validation of the model proposed earlier. New formulae and parameter extraction procedure are presented to extend the applicability of the power law equation to a much wider variety of cells. The J– V curves considered in this paper range from concave (fill-factor<0.25) to highly convex (fill-factor>0.85), and their theoretical expressions contain bias dependent photocurrent and double exponential terms. It is shown that the power law equation also simplifies the calculation of the cell bias point for an arbitrary load.

Determining wave propagation characteristics of MV XLPE power cable using time domain reflectometry technique

In this paper, the wave propagation characteristics of single-phase medium voltage (MV) cross-linked polyethylene (XLPE) power cable are determined using time domain reflectometry (TDR) measurement technique. TDR delivers the complex propagation constant (attenuation and phase constant) of lossy cable transmission line as a function of frequency. The frequency-dependent propagation velocity is also determined from the TDR measurements through the parameters extraction procedure. The calibration of the measuring system (MS) is carried-out to avoid the effect of multiple reflections on the accuracy of measurements. The results obtained from the measurements can be used to localize the discontinuities as well as the design of communication through distribution power cables.

A Parameters Extraction Procedure Based on Integrated Evaluation of Static and Dynamic Characteristics -Application to a pin Diode Model-

This paper proposes a parameters extraction procedure based on the integrated evaluation of static and dynamic characteristics. The existing procedure available for various model is based on formal optimization with direct search, but it yields static characteristics with low accuracy, and its computation cost is high. The proposed procedure helps solve these problems since static characteristic evaluation is added to an objective function and the search range is narrowed. Validation with the simulation results of parameters optimization for a pin diode model demonstrates that the proposed procedure has high accuracy and low computation cost.