Parallel Optical Interconnects Research Articles

Theoretical Analysis of Energy Efficiency and Bandwidth Limit of Silicon Photonic Modulators

Parallel optical interconnects at the extreme scale hold the key to resolve the grand challenge of moving enormous amount of data between on-chip cores and within multi-chip modules. Silicon photonic modulators, as one of the most pivotal devices conducting electronic to photonic signal conversion, must excel in energy efficiency and bandwidth density in order to meet the stringent requirement of extreme scale photonic interconnects. In this manuscript, the energy efficiency and bandwidth limit of ultra-compact resonator-based silicon photonic modulators are analyzed from three fundamental perspectives: free carrier dispersion strength of the active materials, Purcell factors of the resonators, and electrical configuration of the capacitors. Our simulation results reveal convincing advantages of photonic crystal nanocavity over micro-ring and micro-disk resonators in terms of energy efficiency and device footprint. While for the electro-optic modulation region, metal-oxide-semiconductor (MOS) capacitors truly outperform reversed PN junctions due to the large capacitance density. However, all resonator-based silicon photonic modulators suffer the intrinsic trade-off between energy efficiency and resistance-capacitance-delay limited bandwidth. The general model developed herein lays the theoretical foundation and identify possible routes to achieve atto-joule per bit energy efficiency and how to approach the bandwidth limit of silicon photonic modulators.

30 Gb/s integrated receiver array for parallel optical interconnects

A 30 Gb/s integrated receiver array for parallel optical interconnects with four channels have been designed and implemented in a 0.13 μm CMOS technology. To achieve small area and low power consumption while maintaining large bandwidth and high gain, the integrated receiver has been implemented with a regulated cascode (RGC) transimpedance amplifier (TIA), resistive and capacitive degeneration and inductorless limiting amplifier (LA), which employs active feedback and negative capacitance. From the measurement results of the optical module using 850 nm photodiode (PD), the receiver showed a constant single-ended output swing of 320 mV up to 7.5 Gb/s/ch with clear eye diagrams and BER of <10−12. With a voltage supply of 1.2 V, a figure of merit (FOM) of 8 mW/Gb/s was obtained with a small chip area per channel of 0.28 mm2/ch.

Wet-Etched Three-Level Silicon Interposer for 3-D Embedding and Connecting of Optoelectronic Dies and CMOS ICs

Ultracompact optical submodules for parallel optical interconnects are demonstrated based on a three-level silicon interposer, which is fabricated through a low-cost wet etching process. Using three steps of wet etching of silicon, a multilevel cavity is formed for embedding and flip-chipping optical and electrical dies, and opening optical through-silicon vias. In order to reduce thermal coupling between CMOS and GaAs dies, a 50-μm thermal isolation air gap is formed between dies as a part of the assembly concept, and thermal simulations and experiments are carried to validate its effectiveness. Based on this 3-D packaging concept, compact 4 mm × 6 mm, 10-Gb/s 12-channel transmitter and receiver submodules are fully assembled and tested. Clear and uniform eye patterns for both modules are captured at 10 and 15 Gb/s for every channel. Bit error rate (BER) testing is also performed. Both transmitter and receiver submodules show uniform BER curves, with receiver sensitivity spreading less than 1 dB at a BER lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . Also, crosstalk for both modules is tested, yielding only a 0.1and 0.8-dB additional penalty for transmitter and receiver, respectively.

Cost-effective parallel optical interconnection module based on fully passive-alignment process

In optical interconnection technology, high-speed and large data transitions with low error rate and cost reduction are key issues for the upcoming 8K media era. The researchers present notable types of optical manufacturing structures of a four-channel parallel optical module by fully passive alignment, which are able to reduce manufacturing time and cost. Each of the components, such as vertical-cavity surface laser/positive-intrinsic negative-photodiode array, microlens array, fiber array, and receiver (RX)/transmitter (TX) integrated circuit, is integrated successfully using flip-chip bonding, die bonding, and passive alignment with a microscope. Clear eye diagrams are obtained by 25.78-Gb/s (for TX) and 25.7-Gb/s (for RX) nonreturn-to-zero signals of pseudorandom binary sequence with a pattern length of 231 to 1. The measured responsivity and minimum sensitivity of the RX are about 0.5 A/W and ≤−6.5 dBm at a bit error rate (BER) of 10−12, respectively. The optical power margin at a BER of 10−12 is 7.5 dB, and cross talk by the adjacent channel is ≤1 dB.

Chip Scale 12-Channel 10 Gb/s Optical Transmitter and Receiver Subassemblies Based on Wet Etched Silicon Interposer

In this paper, compact optical subassemblies are demonstrated based on a novel silicon interposer, which is designed and fabricated in a wafer scale process. The interposer includes the design of optical and electrical connections. A low-cost fabrication method, wet etching, is used to define light inputs and outputs as well as create the required recesses in the interposer to embed the chips into the silicon wafer at the same time. Impedance matched traces, for the high speed signals of the CMOS and opto–electronic ICs, are designed using advanced design system software and transferred onto the interposer by photolithography and electro-plating, which are accomplished on the deeply etched topology. The whole process flow of the silicon interposer patterning is designed and demonstrated, and the challenges are discussed. After the process, the optoelectronic dies and their complimentary CMOS parts are flipped and bonded on the interposer in close proximity, and a mechanical optical interface (MOI) is mounted for light coupling. Both transmitter and receiver subassemblies provide 12 parallel optical interconnections, and are scaled down to an area measuring 6 by 8 mm. Signal integrity testing is performed on a probe station for 10 Gb/s data signal delivering clear eye patterns for all channels (in both Rx and Tx subassemblies). The performance is further characterized using bit error rate (BER) testing. Both transmitter and receiver assemblies outperform a reference SFP+, with receiver sensitivity of −10 dBm at a BER lower than 10−12 after compensating for the MOI insertion loss. Finally, we also test the assemblies for crosstalk and demonstrate that the current design has a maximal additional penalty lower than 0.2 and 0.8 dB for transmitter and receiver, respectively.

Capacitively-Coupled CMOS VCSEL Driver Circuits

A capacitively-coupled laser diode driver (LDD) for common-cathode vertical-cavity surface-emitting lasers (VCSELs) designed in 65 nm CMOS intended for short-reach parallel optical interconnects is presented. The LDD consists of a capacitively-coupled voltage-mode high-frequency path and a direct-coupled path that provides low-frequency signal components. By increasing the low-frequency path bandwidth an order of magnitude compared to previous capacitively-coupled drivers, the on-chip coupling capacitor is reduced to 1.05 pF, occupying 3 times less area than prior art. The driver incorporates capacitively-coupled two-tap pre-emphasis to equalize the VCSEL’s optical response. The VCSEL was modulated with an optical modulation amplitude (OMA) of up to +5.1 dBm and an extinction ratio of 9 dB at 15 Gb/s, the highest extinction ratio achieved in high-speed anode-driving CMOS LDDs. The driver is programmable and is also demonstrated with +2.3 dBm OMA at a power consumption of only 30 mW, corresponding to an energy efficiency of 2 pJ/bit.

Pioneering research in parallel optical interconnect technology for cloud computing

Pioneering research in parallel optical interconnect technology for cloud computing

Fully passive-alignment pluggable compact parallel optical interconnection modules based on a direct-butt-coupling structure for fiber-optic applications

A low-cost packaging method utilizing a fully passive optical alignment and surface-mounting method is demonstrated for pluggable compact and slim multichannel optical interconnection modules using a VCSEL/PIN-PD chip array. The modules are based on a nonplanar bent right-angle electrical signal path on a silicon platform and direct-butt-optical coupling without a bulky and expensive microlens array. The measured optical direct-butt-coupling efficiencies of each channel without any bulky optics are as high as 33% and 95% for the transmitter and receiver, respectively. Excellent lateral optical alignment tolerance of larger than 60 μm for both the transmitter and receiver module significantly reduces the manufacturing and material costs as well as the packaging time. The clear eye diagrams, extinction ratios higher than 8 dB at 10.3 Gbps for the transmitter module, and receiver sensitivity of better than −13.1 dBm at 10.3 Gbps and a bit error rate of 10−12 for all channels are demonstrated. Considering that the optical output power of the transmitter is greater than 0 dBm, the module has a sufficient power margin of about 13 dB for 10.3 Gbps operations for all channels.

Display glass for low-loss and high-density optical interconnects in electro-optical circuit boards with eight optical layers.

Parallel optical interconnects on-board level requires low propagation loss in wavelength range between 850 and 1550 nm to be compatible with datacom and telecom optical engines. For highest integration density tight waveguide bends and a scalable number of optical layers should be manufacturable for 2D interfaces to optical fiber array connectors and photonic assembly I/O's. We developed a glass waveguide panel process for double-sided processing of commercial available display glass by applying a two-step thermal ion-exchange process for low-loss multi-mode graded-index waveguides. Multiple glass waveguide panels can be embedded between electrical layers. The generic concept enables fabrication of high-density integration (HDI) electro-optical circuit boards (EOCB) with high number of optical and electrical layers. Waveguides with high NA of 0.3 for low bend losses could be achieved in glass with propagation loss of 0.05 dB/cm for all key wavelengths. Four of those glass waveguide panels were embedded in an EOCB demonstrator with size of 280 x 233 mm² providing eight optical layers with 96 channels in an area of 2.8 x 1.5 mm². To the best of our knowledge it's the highest number of layers that has ever been demonstrated for an EOCB.

Sixteen-element Ge-on-SOI PIN photo-detector arrays for parallel optical interconnects

We describe the structure and testing of one-dimensional array parallel-optics photo-detectors with 16 photodiodes of which each diode operates up to 8 Gb/s. The single element is vertical and top illuminated 30-μm-diameter silicon on insulator (Ge-on-SOI) PIN photodetector. High-quality Ge absorption layer is epitaxially grown on SOI substrate by the ultra-high vacuum chemical vapor deposition (UHV-CVD). The photodiode exhibits a good responsivity of 0.20 A/W at a wavelength of 1550 nm. The dark current is as low as 0.36 μA at a reverse bias of 1 V, and the corresponding current density is about 51 mA/cm2. The detector with a diameter of 30 μm is measured at an incident light of 1.55 μm and 0.5 mW, and the 3-dB bandwidth is 7.39 GHz without bias and 13.9 GHz at a reverse bias of 3 V. The 16 devices show a good consistency.

VSR5 optical transmission system and 12 × 10 Gbps VCSEL driver array design

This paper introduces VSR (Very Short Reach) parallel optical interconnection in OC-768 applications, which is compliant with OIF (Optical Internetworking Forum) OIF-SFI5-01.0 and VSR5-01.0 agreements. A point to point experimental parallel transmission system is set up to convert 16×2.5Gbps electrical signals to 12×3.318Gbps optical signals, and vice versa. An OC-768 framer dichotomy search algorithm logic has been implemented in an converter IC, which greatly boosts up working speed and saves logic resources. In addition, a 12×10Gbps VCSEL common cathode driver array has been fabricated by 0.18μm CMOS technology. Tested by an OC-768 tester, a system bit error rate (BER) of lower than 1×10−12 has been obtained.

Si3N4 waveguide-based parallel optical interconnect incorporating an interface comprising arrayed grating couplers combined with fiber arrays

A high-speed parallel optical interconnect (POI) incorporating silicon nitride (Si(3)N(4)) waveguides was realized that takes advantage of an eight-channel input/output interface based on grating couplers (GCs) in alignment with fiber arrays. For each of the channels, a straight waveguide in the middle is linked to a GC via a taper, which is addressed by a single-mode fiber (SMF) at the input and a multimode fiber at the output. To verify the feasibility of the interconnect, the alignment tolerance has been explored in terms of the position and angle of incidence of the SMF with respect to the GC. This has been conducted by probing into the optical throughput of the proposed POI, which is determined by different sources of loss associated with the proposed Si(3)N(4) waveguide device. For a typical GC, the measured coupling loss was 5.2 dB at the center wavelength of 1590 nm, when addressed by a SMF. For a 1 dB loss penalty, the positional tolerance of the fiber was discovered to about ±3 μm and 45 μm along the lateral direction and the direction inclined at 16 deg normal to the device, respectively. The corresponding angular tolerance was ±1 deg. We ultimately confirmed that 8×10 Gbps high-speed digital signals were efficiently delivered through the proposed POI.

High-Speed Reconfigurable Free-Space Card-to-Card Optical Interconnects

A reconfigurable free-space-based card-to-card optical interconnect architecture employing MEMS-based steering mirror arrays in conjunction with VCSEL and photodiode arrays is proposed and demonstrated in this paper. Theoretical studies and simulations indicate that error-free [bit error rate (BER) of <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> ] optical interconnects with a range on the order of tens of centimeters can be achieved, and the major factors limiting the performance are the VCSEL beam divergence and interchannel optical crosstalk. The tradeoff between the BER performance and the channel spacing of the receiver MEMS mirror array is also investigated. A proof-of-concept 3 × 10 Gb/s reconfigurable optical interconnect architecture is developed, demonstrating a BER of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> and a receiver sensitivity better than ~ -11.5 dBm. Both the port-to-port and board-to-board reconfigurability of the proposed architecture are also experimentally demonstrated, opening the way for attaining higher throughputs through highly dense 3-D parallel optical interconnects.

Performance optimization of a free space optical interconnect system with a metal-semiconductor-metal detector

In this paper we study the possibility and the potentiality of using metal semiconductor-metal photodetector (MSM-PD) in three-dimensional parallel free space optical interconnect (FSOI) systems. The signal-to-noise ratio (SNR) and time response are used as performance measures to optimize the geometry of MSM-PD used in FSOI systems. Both SNR and time response are evaluated, analyzed, and their dependence on feature parameters of the MSM-PD, including finger size, spacing, and number of fingers, are considered. Based on the results obtained, we show that the use of MSM-PD in FSOI improves the interconnect speed at a given acceptable SNR.

Simple and high-accuracy integration for parallel optical subassembly with 120-Gbits/s data transmission

Abstract. We integrate transmitting and receiving parallel optical sub-assemblies POSAs that are suitable for high-speed and parallel opticalmodules between optical components by using a simple and high-accuracy alignment technique. Characteristics of the proposed POSAsinclude a low coupling loss of 0.75 dB, a wide bandwidth for 10 Gbits/stransmission per channel, and low optical and electrical crosstalk of lessthan 30 dB. As a result, a data transmission rate of 10 Gbits/s 12channels is well demonstrated with clean eye diagrams. © 2010 Society ofPhoto-Optical Instrumentation Engineers. DOI: 10.1117/1.3486205 Subject terms: parallel optical subassembly; microlens; silicon optical bench;passive alignment technique . Paper 100082R received Jan. 30, 2010; revised manuscript received Jul. 16,2010; accepted for publication Jul. 23, 2010; published online Sep. 2, 2010. 1 Introduction With the increasing construction of servers in office build-ings and data centers, the networks of these centers must beable to provide high-capacity data transmissions.Also, highdata transmissions are required for various multimedia ser-vices such as real-time data communications. Thus, thedriving force for these requirements has stimulated the re-cent development of parallel optical interconnections.

Cost-effective integration of plastic optical fiber and total internal reflection mirrors in printed circuit boards for parallel optical interconnects

A novel method of integrating a total internal reflection (TIR) mirror into an optical waveguide embedded in a printed circuit board (PCB) was demonstrated for application in chip-to-chip optical interconnects. Plastic optical fiber (POF) was placed into channels that were mechanically machined into FR-4 composite plates. The TIR mirror was created by a second mechanical machining. The mirror loss was measured to be approximately −1.6 dB per reflection. The use of POF resulted in attenuation losses in the waveguide over an order of magnitude lower than what is obtainable with typical planar waveguides that are integrated into PCBs. Monte Carlo ray tracing was used to determine the theoretical efficiency of the system as well as cross talk between channels due to optical device alignment tolerances.

Configuration of an optical waveguide interconnect mesh network based on EOPCB

An optical waveguide interconnect mesh network scheme for parallel multiprocessor systems based on an electro-optical printed circuit board (EOPCB) with multimode polymer waveguide is proposed. The system consists of 22 processor element chips interconnected in a mesh network configuration. An additional layer with optical waveguide structure is embedded in a conventional printed circuit board to construct the EOPCB. Vertical cavity surface emitting laser (VCSEL)/positive intrinsic-negative (PIN) arrays are applied as the optical transmitters/receivers. Three 112 VCSEL/PIN parallel optical transmitting/receiving modules are used to provide 32 input/output optical channels required by the 22 chip-to-chip optical mesh interconnect system. The data rate in each optical channel is 3.125 Gbps and thus 10 Gbps parallel optical interconnect link for each direction of a chip is obtained. The optical signals from a processor element chip can be transmitted to another chip through optical waveguide interconnect embedded in the board. Thus the optical interconnect mesh network for parallel multiprocessor system can be implemented.

Quantitative analysis on the computing performance improvement by parallel optical interconnection

This paper compares the optical and electrical interconnect systems by analyzing the efficiency and evaluating the total processing time, and design an experiment to demonstrate this performance promotion. With the increasing demand on large-scale parallel computing tasks, data transmission instead of data computing has become more and more important, so the rapid development of optical chip-to-chip interconnects techniques has gotten more attention. In this paper, we take fast Fourier transform (FFT) computation as an example to study whether and how the optical interconnection has influence on the computing performance, and three topology models are used to judging the transmission latency, and the relationship between the total processing time and the FFT points is also under investigation. Both results show parallel optical interconnection can bring large advantages in promoting computing performance. It is also found that the larger the transmission scale is, the more saving optical interconnection makes.

160 Gb/s Bidirectional Polymer-Waveguide Board-Level Optical Interconnects Using CMOS-Based Transceivers

We have developed parallel optical interconnect technologies designed to support terabit/s-class chip-to-chip data transfer through polymer waveguides integrated in printed circuit boards (PCBs). The board-level links represent a highly integrated packaging approach based on a novel parallel optical module, or Optomodule, with 16 transmitter and 16 receiver channels. Optomodules with 16 Tx+16 Rx channels have been assembled and fully characterized, with transmitters operating at data rates up to 20 Gb/s for a 27-1 PRBS pattern. Receivers characterized as fiber-coupled 16-channel transmitter-to-receiver links operated error-free up to 15 Gb/s, providing a 240 Gb/s aggregate bidirectional data rate. The low-profile Optomodule is directly surface mounted to a circuit board using convention ball grid array (BGA) solder process. Optical coupling to a dense array of polymer waveguides fabricated on the PCB is facilitated by turning mirrors and lens arrays integrated into the optical PCB. A complete optical link between two Optomodules interconnected through 32 polymer waveguides has been demonstrated with each unidirectional link operating at 10 Gb/s achieving a 160 Gb/s bidirectional data rate. The full module-to-module link provides the fastest, widest, and most integrated multimode optical bus demonstrated to date.

Synchronous Parallel Optical I/O on CMOS: A Case Study of the Uniformity Issue

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Short-range parallel optical interconnect between integrated circuits can alleviate bandwidth, power, and packaging density issues that are associated with low-latency high-bandwidth input–output over electrical interconnect. In this paper, we evaluate the option of using true source-synchronous signaling over optical interconnect with a large number of channels, reducing the substantial per-channel clock synchronization circuitry to one instance. We also look into dc-unbalanced signaling to remove the need for data coding. Uniformity across channels is key to the feasibility of such an approach. An actual 64-channel parallel optical interconnect setup at 1.25 Gb/s/channel is examined, and models for the performance and uniformity of the different constituent parts of the interconnect are drawn up. Major attention is given to the statistical modeling of the coupling efficiency between a vertical cavity surface emitting laser array and a multifiber connector. Although derived in the context of a uniformity study, the stochastic models and the modeling approach are valuable in their own right. In our case study, the usage of a common logic threshold across all channels, which is required for dc-unbalanced signaling, appears infeasible after all models are combined. Efficient true source-synchronous signaling turns out to be within reach in carefully designed systems. </para>