Parallel Input Data Research Articles

A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform

Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy for extension. To eliminate high frequency components, the pixel values outside the boundary of the image are mirror-extended as the symmetric wavelet transform (SWT) and the mirror-extension is realized via the routing network. Owing to the property of the parallel processing, we adopt the row-based recursive pyramid algorithm (RPA), similar to 1-D RPA, as the data scheduling. This design has been implemented and fabricated in a 0.35 mm 1P4M CMOS technology and the working frequency is 50 MHz. The chip size is about 5200 mm × 2500 mm. For a 256 × 256 image, the chip can perform 30 frames per second with the filter length varying from 2 to 20 and with various levels. The proposed architecture is suitable for real-time applications such as JPEG 2000.

New microprocessor based approach to binary multiplication using recorded multipliers

Multibit overlapped scanning is used to reduce the time to perform binary multiplication. The scanning and recording of the multiplier vector is done using combinational logic. Circuits for both parallel and serial input data are designed. An implementation using multi-microprocessors is proposed and simulated results are discussed. A possible application to digital filtering is suggested.

Bit-level systolic array circuit for matrix vector multiplication

A bit-level systolic array for computing matrix x vector products is described. The operation is carried out on bit parallel input data words and the basic circuit takes the form of a 1-bit slice. Several bit-slice components must be connected together to form the final result, and the paper outlines two different ways in which this can be done. The basic array also has considerable potential as a stand-alone device, and its use in computing the Walsh-Hadamard transform and discrete Fourier transform operations is briefly discussed.

Anthropometric Considerations in Human Impact Tolerance Research

The primary experimental methodologies of human impact tolerance research require the availability of anthropometric and other body measurement information. Somewhat standard anthropometric procedures are available to describe human volunteer and general populations exposed to dynamic situations. However, classical anthropometry is inadequate to the task of specifying joint mobility and resistance to force. In addition, no common procedures or lists of useful measurements are available for cadaver or laboratory animal subjects. These factors have led to major shortcomings in the current designs of crash test dummies and the parallel input data sets required for the operation of computerized mathematical crash victim simulations. The paper briefly reviews the problems and the activities being carried out for their resolution.

Generator Differential Protection Using a Hybrid Computer

This paper presents a rea1-time hybrid, analog-digital, computer technique for differential protection of generators. The fault/no fault decisions are based on the amplitude ratio of the "fault"' and "average through" currents from a selected generator phase. Analog input data pre-processor, fault monitor and soft-ware segments suitable for valid comparison during the transient period after the inception of a fault are described. Typical examples, from out of approximately 800 case studies, including internal and external faults using a three phase generator are presented.

Input Data Source Limitations for Real-Time Operation of Digital Computers

The purpose of this paper is to consider the limiting conditions associated with the handling of many unrelated input data sources by a digital computer which utilizes binary internal logic. Equations are derived which relate the number of distinct input sources to their frequency through inequalities which specify the limiting conditions, i.e. the maximum number of data sources for a given input data frequency. Inequalities are derived for both serial and parallel input data configurations. The limiting conditions for real-time queuing are derived. The modification of the above conditions when program operations are taken into account is examined, and the information content associated with the limiting conditions is discussed. The absolute limit on computer capacity is derived by considering the limit on the information which can be stored in a given computer. Finally, theoretical conclusions are applied to an exemplary model.