Parallel Current Paths Research Articles

A Wideband Hybrid Envelope Tracking Supply Modulator with Slew-Rate-Enhanced Linear Amplifier

A wideband hybrid envelope tracking supply modulator (HETSM) with a slew-rate-enhanced linear amplifier (LA) is described in this work. The proposed slew-rate enhancement (SRE) structure introduces a parallel auxiliary current path directly to the gate of the class-AB output stage, significantly accelerating the charging and discharging processes of the Miller capacitor without modifying the operating point of the remaining LA. The current delivered via this supplementary path shows a rapid increase, with changes in input voltage, culminating in diminished quiescent current levels. The supply modulator is fabricated in a 180 nm CMOS process. The measurement results show that HETSM is able to track a 100 MHz, 16QAM signal accurately, achieving the maximum efficiency of 87.4% at a 5.12 W output power, with a load that consists of a 5 Ω resistor and a paralleled 100 pF capacitor. The proposed LA realizes a slew rate of −1857/+1239 V/μs and a bandwidth of 226.6 MHz under a 24 mA quiescent current.

Optical Investigation of a Spark Gap for DC Protection around Current Zero

The applied experimental setup consists of a pair of fixed electrodes forming a short gap in air. The electrodes are connected with a thyristor forming a parallel current path. Once the thought flashover ignited arc has burnt a given time in the range of several hundreds of microseconds, the thyristor will be fired causing a commutation of the current in the semiconductor path. Hence, the current through the electrode gap will be reduced. The extinguishment of the arc permits the creation of a current zero in the gap. The focus of the experimental work is set to the analysis of the arc plasma during the DC phase and its distinction in the current extinction phase (current zero). High speed camera observation and optical emission spectroscopy are carried out and combined with the electrical measurements.

Detection, Analysis, and Behavior of Soft-Shorts in Solid-State Batteries

Lithium metal batteries face numerous challenges before being employed in practical energy storage systems. Chief among these is the suppression of lithium dendrites, which lead to cell shorting and thermal runaway. In the field of solid-state batteries, there is often talk of “soft-shorts”, where small lithium dendrites form, short, then disappear. However, there is no clear consensus on the definition of soft-shorts, how they behave, and what their presence means for solid electrolyte development. Here, we use composite polymer electrolytes as exemplary solid electrolytes to detect, analyze, and thoroughly describe the varied behavior of soft-shorts. We define soft-shorts and show quantitatively that both ionic and electronic current flow simultaneously in a soft-shorted cell. The amount of each current depends on dendrite size, which dictates the resistance to the electronic pathway as well as Joule heating of the thin metal filaments. This heating leads to the “burning out” of the dendrites, which is responsible for the rapid un-shorting of soft-shorted cells. We use computational modeling to quantify the dendrite properties and explain how this leads to the observed transient behavior. More persistent soft-shorts are analyzed with temperature-dependent, quantitative electrochemical impedance fitting, where it is shown that parallel ionic and electronic current paths present impedance data that can be misinterpreted without rigorous analysis. The advantages and disadvantages of several soft-short characterization techniques are discussed. In the end, we show that soft-shorts are diverse in nature and thus require diverse tools and keen eyes from researchers to avoid the over-selling of flawed materials for lithium metal batteries.

A Dual-Branch Series-Parallel Hybrid Buck DC-DC Converter With Flying Capacitor Voltage Auto-Balancing

This paper presents a dual-branch series-parallel hybrid buck converter with flying capacitor voltage auto-balancing and reduced output impedance. The proposed converter automatically and inherently balances the flying capacitor voltages as one-third of the input voltage. Besides, the proposed converter operates in four states per cycle rather than the conventional six states, leading to a feasible Type-III compensation of the analog pulse-width modulation (PWM) controller. Moreover, due to the multiple parallel current paths in the switched-capacitor network, the proposed converter reduces the output impedance, thus decreasing the conduction loss. Finally, validated in 65-nm CMOS, the proposed converter regulates a 0.55 V–1 V output voltage from a 3.6 V input voltage over a large output power of 0.45 W with 82% peak efficiency, and switching frequency up to 5 MHz. It also automatically sets the flying capacitor voltages at 1.2 V.

Vertical Stacked LEGO-PoL CPU Voltage Regulator

This article presents a 48–1 V merged-two-stage hybrid-switched-capacitor converter with a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">linear extendable group operated point-of-load</i> (LEGO-PoL) architecture for ultrahigh-current microprocessors, featuring 3-D stacked packaging and coupled inductors for miniaturized size, fast speed, and vertical power delivery. The architecture is highly modular and scalable. The switched-capacitor circuits are connected in series on the input side to split the high input voltage into multiple stacked voltage domains. The multiphase buck circuits are connected in parallel to distribute the high output current into multiple parallel current paths. It leverages the advantages of switched-capacitor circuits and multiphase buck circuits to achieve soft charging, current sharing, and voltage balancing. The inductors of the multiphase buck converters are used as current sources to soft-charge and soft-switch the switched-capacitor circuits, and the switched-capacitor circuits are utilized to ensure current sharing among the multiphase buck circuits. A 780-A vertical stacked CPU voltage regulator with a peak efficiency of 91.1% and a full load efficiency of 79.2% at an output voltage of 1 V with liquid cooling is built and tested. The switched capacitor circuits operate at 286 kHz and the buck circuits operate at 1 MHz. It regulates output voltage between 0.8 and 1.5 V through the entire 780-A current range. This is the first demonstration of a 48–1 V CPU voltage regulator to achieve over 1-A/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\text{2}$</tex-math></inline-formula> current density and the first to achieve 1000-W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^3$</tex-math></inline-formula> power density.

Coexistence of parallel and series current paths in parallel-coupled double quantum dots in nonlinear transport regime

We investigated the electron transport properties of parallel-coupled double quantum dot (DQD) devices under magnetic fields. When a low magnetic field was applied, electron tunneling through parallel-coupled DQDs was observed. Under a high magnetic field, we observed both electron tunneling through parallel- and series-coupled DQDs under nonlinear transport conditions. In addition, the Pauli spin blockade was observed, indicating tunneling through the series-coupled DQDs. We attribute these behaviors to the magnetic-field-induced changes in the tunnel-couplings that allow the coexistence of the current paths of the parallel and series configurations.

Startup and Quench Electromagnetic Simulation of a Bitter Plate TF Coil Concept For the Fusion Nuclear Science Facility (FNSF)

Current distributions during startup and quench of very large reactor relevant coil systems will vary significantly from the smaller prototype magnets. A reactor scale simulation is needed. In this study, the FNSF magnet from the 2017 study is used as an example of a full sized reactor. The intent of the study is to investigate use of HTS conductors in the FNSF and how sizing and performance might be affected. A pancake or Bitter magnet like winding pattern is investigated to allow inductive and resistive redistribution of currents. A portion of the winding pack retains some resistivity to aid in redistribution of current during a transient or quench. Resistive materials can be used to support energy absorption for stability or to provide partial current dump capability during a quench, however, the primary quench mitigation mechanism is inductive redistribution of currents around the quench zone. In this implementation, the Bitter plate is both structural - similar to radial plates in ITER and electrical, intended, to limit current concentration during ramp-up. Use of localized resistors and parallel current paths are used to encourage more uniform startup currents. The analysis is a transient electromagnetic simulation using ANSYS. It is a cyclic symmetry modeling of an individual plate and is limited by the assumption that a local quench is repeated by the cyclic symmetry. This is a concession to the model size. Results are discussed in the context of performance needed for the FNSF.

On-chip ionic current sensor.

Neural implants that deliver drugs or electrical stimuli via microfluidic ports are promising in providing therapy for various disorders such as epilepsy, chronic pain, and vestibular diseases. To deliver the stimuli to a neural target, these devices incorporate two or more electrodes that apply an electric field to drive charged particles or ions along an aqueous route provided by microfluidic channels. The amount of drug/current delivered is determined by measuring the ionic current flow. When the ionic current can only travel from one electrode to another via a single route or channel, the amount of therapeutic current is stoichiometrically equal to the electronic current applied by the device and therefore can be measured with an electronic current sensor. However, some recently developed devices contain networks of branched channels. In this case, the presence of multiple parallel ionic current paths makes it so that the current through any one individual channel is no longer measurable by observing electronic current alone. Here, we present an on-chip sensor that uses two Pt/Ir electrodes to transduce the ionic current through a target channel into a measurable voltage signal. The size of the metal wires did not impact the measured voltage, the size of the channel between the two sensing electrodes determines sensitivity of the sensor, change in temperature can cause a change in readings, and input impedance of the voltage measuring equipment must be greater than 1 GΩ to maintain measurement stability. The sensor showed stability of reading in a one-week longevity test.

Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP

Modern analog placement techniques require consideration of current path and symmetry constraints. The symmetry pairs can be efficiently packed using the symmetry island configurations, but not all these configurations result in minimum gate interconnection, which can impact the overall circuit routing and performance. This article proposes the first work that reformulates this problem considering all of them together in the form of parallel current path (PCP) constraints. PCP constraints, in addition to monotonic current paths, also consider partial-monotonic current paths to generate a more compact placement. We use a novel two-step approach to detect symmetry-feasible sequence-pairs (SFSPs) without doing placement construction by using representative sequence-pair (RSP). Then a placement algorithm satisfying these constraints is formulated to reduce a vast search space via efficient sequence pair manipulation. The experimental results show that this formulation and algorithm can generate multiple placement solutions that satisfy all the constraints in a more tightly packed configuration, resulting in smaller wirelength, reduced parasitics, and thus better post-layout performance.

Parasitic Inductance Modeling and Reduction for Wire-Bonded Half-Bridge SiC Multichip Power Modules

This article first developed an inductance model that includes the parasitic mutual inductance between parallel current path segments for SiC multichip power modules. Based on the developed model, the SiC multichip module's transient response was analyzed, important parasitic inductances were identified. The layout was improved based on the transient analysis. The improved package layout can reduce the parasitic inductance without increasing the fabrication difficulty. Experiments were conducted to validate the reduction of parasitic inductances. The parasitic ringing and the crosstalk effect were significantly reduced with the proposed technique. The thermal performance was also improved with the proposed layout.

A New Low-Capacitance High-Voltage-Tolerant Protection Clamp for High-Speed Applications

A new low-capacitance clamp is introduced for high-voltage-tolerant and high-speed interface applications. An embedded stacking architecture is proposed to address latch-up-immune design requirements without degradation in the electrostatic discharge (ESD) stress-handling capability, leakage, or capacitance. Thanks to a parallel current conduction path activated during ESD stress, a state-of-the-art failure threshold current per unit area is obtained for high-voltage-tolerant interface applications in sub-28-nm CMOS process technologies. The device design concept introduced in this article facilitates the implementation of compact, high-performance interface applications, extended in general to protection clamp devices requiring a higher holding voltage.

Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier

A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and a slew-rate enhanced linear amplifier (LA) are presented. In addition to smaller ripple and lower losses of 3L-SWCs, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80 MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage $V_{\mathrm{ CF}}$ and eliminates the conventionally required calibration loop to control it. The hysteretic-controlled 3L-SWC provides a high percentage of power amplifier (PA) supply load current with lower ripple, reducing the LA high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the LA, resulting in slew rate of over 307 V/ $\mu \text{s}$ and bandwidth of over 275 MHz for the LA. The SRE circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of output without modifying the operating point of the remaining LA, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in a 65-nm CMOS process. The measurement results show the tracking of long-term evolution (LTE)-40-MHz envelope with 93% peak efficiency at 1-W output power, while the SRE is disabled. Enabling the SRE, it can track LTE-80-MHz envelope with peak efficiency of 91%.

Nanoparticle-Induced Anomalous Hall Effect in Graphene.

Schemes for introducing magnetic properties into graphene are of fundamental interest and could enable the development of electrically controlled magnetic devices, thereby extending graphene's applications from conventional electronics to spintronics. Proximity-induced ferromagnetism (PIFM) has been reported for graphene coupled to adjacent ferromagnetic insulators (FMIs). PIFM from an FMI preserves graphene's high carrier mobility and does not introduce a parallel current path. However, few FMIs other than yttrium-iron-garnet are suitable for practical applications due to difficulties in their growth and deposition and to their typically low Curie temperatures. Furthermore, it is difficult to obtain a high-quality FMI/graphene interface by graphene transfer methods, which are essential for obtaining the required interfacial exchange coupling. Here, we report the observation of the anomalous Hall effect (AHE) in graphene proximity coupled to an array of magnetic nanoparticles. This observation of AHE in graphene in proximity to a discontinuous magnetic structure opens the door to realizing magnetic properties in graphene from a greatly expanded range of materials and offers new possibilities for realizing patterned spintronic devices and circuitry.

Internal resistance of rear totally diffused solar cells with line shaped contacts

We present an analytical model for the internal resistance of passivated emitter and rear totally diffused (PERT) solar cells. First, we apply the model of Saint-Cast for the spreading resistance of a passivated emitter and rear cell (PERC) structure with line-shaped contacts. To account for the additional vertical current flow through the silicon wafer and the lateral current flow through the back surface field of a PERT structure, we add a parallel current path using common analytical expressions. We compare the analytical models with two-dimensional numerical simulations based on Quokka 3 and find deviations of less than 6% for the internal resistance. In addition, we compare the analytical model of the internal resistance of PERC and PERT solar cells with experimental data of the series resistance of PERC and PERT solar cells.

Improved Operating Range of RSFQ-Controlled Current Steering Switches

For spectroscopic and imaging applications in the submillimeter wavelength band, superconducting radiation sensors are widely used. Thereby, sensor arrays with a rising number of pixels require multiplexing techniques in order to reduce the number of wires leading to the cryogenic stage. A current steering switch (CSS) provides the basis for one kind of promising code division multiplexers. It is composed of two identical superconducting quantum interference devices (SQUIDs) in parallel current paths. Switching one of them from the superconducting into the normal state, which is controlled by the applied magnetic flux, alters the signal path; thus, they can act as a polarity switch for analog signals. In this paper, we describe a method that uses rapid single-flux quantum (RSFQ) electronics for controlling these switches. Therefore, their SQUIDs are inductively coupled each to the storing loop of an RSFQ delay flip-flop (DFF); hence, the state of the analog switch can be controlled by means of digital RSFQ signals. As a first step, we show the change in the critical current of the SQUIDs by the coupled operating digital circuit. For a wider operating range of the CSS, we developed a DFF, which is able to store a larger quantity of magnetic flux to make it possible to apply more flux to the coupled SQUID. For further improvements, we tested asymmetric SQUIDs to reduce the required magnetic flux. The results of the simulations and measurements are discussed.

AC transport current loss analysis for anti-parallel current flow in face-to-face stacks of superconducting tapes

In this study we investigated ac transport current losses in the face to face stack for the anti-parallel current flow, and compared the electromagnetic properties with those of the single SC tape as well as those of the same stack for the parallel current path. The gap between the SC tapes in the stack varied in order to verify the electromagnetic influence of the neighbors when current flows in opposite direction, and the model was implemented in the finite element method program by the commercial software, COMSOL Multiphysics 4.2a. Conclusively speaking, the loss was remarkably decreased for the anti-parallel current case, which is attributed the magnetic flux compensation between the SC layers due to the opposite direction of the current flows. As the gap between SC tapes was increased, the loss mitigation became less effective. Besides, the current density distribution is very flat cross the sample width for the narrower gap case, which is believed to be benefit for the power electric system. These results are all in good agreement with those predicted theoretically for an infinite bifilar stack.

A Planar Magnetically Coupled Resonant Wireless Power Transfer System Using Printed Spiral Coils

A fully planar wireless power transfer (WPT) system via strongly coupled magnetic resonances is presented. In it, both the transmitter and the receiver are planarized with the use of coplanar printed spiral coils (PSCs) and a printed loop. An equivalent circuit model of the proposed planar WPT system is derived to facilitate the design, and a flowchart is provided for the optimization of the system with given size constraints. To realize high peak power transfer efficiency, the quality factor of individual loop or resonator, the mutual coupling between resonators, and the frequency splitting phenomenon of the system are analyzed in addition to the effect of the input impedance of the system on the transmission efficiency. Furthermore, parallel current paths are created by applying auxiliary strips to the backside of the substrates and connecting to the prime resonators using vias to decrease the resistance and to increase the quality factor of the PSC resonators, and this in turn further improves the transfer efficiency of the proposed planar WPT system. The measured results show that the proposed WPT system is able to provide a stable wireless power transfer with up to 81.68% efficiency at a distance of 10 cm. The planar structure and the high transfer efficiency make the proposed design a suitable candidate for wireless power transfer of small portable electronic devices.

RF-sheath patterns modification via novel Faraday screen and strap voltage imbalance on Tore Supra ion cyclotron antennae

Using high-resolution diagnostics, this paper investigates experimentally two ways of influencing the radiofrequency (RF) sheath patterns (magnitude and spatial distribution) developing around active Tore Supra ion cyclotron antennae. Firstly two types of Faraday screen electrical designs were compared. The new design aimed at reducing the parallel RF electric field integrated along “long field lines” passing in front of the antenna, by interrupting all parallel RF current paths on its front face. This proved inefficient for attenuating the RF-sheaths on the screen itself, and only weakly modified their distribution. Secondly the ratio of strap RF voltage amplitudes was varied, either during spontaneous bifurcations of the antenna electrical operational point or through the power balance between RF generators. This affected the left–right symmetry of screen heat loads: the local fluxes tended to evolve as the RF voltages on the nearest strap. Both experiments question the method used to optimize the new screen.

RSFQ electronics for controlling superconducting polarity switches

Superconducting radiation sensors are of particular interest for imaging applications in the sub-mm wavelength band because of their extraordinary sensitivity. The rising number of sensors integrated in one array entails the requirement of multiplexing techniques in order to reduce the number of wires leading into the cryogenic stage and thus reduce the thermal losses. One kind of promising code division multiplexing technique is based on a current steering switch (CSS), which is composed of two identical superconducting quantum interference devices (SQUIDs) in parallel current paths. One of them is switched from the superconducting into the normal state controlled by the applied magnetic flux. In this way the signal path can be altered and they can act as a polarity switch for analogue signals. We pursue this concept to use rapid single flux quantum (RSFQ) electronics for controlling these switches. As a first step, the SQUIDs of the CSS are inductively coupled to the storing loops of two delay flip flops (DFFs). Thus, one is able to toggle the polarity of the analogue switch by controlling the state of the DFF by RSFQ control signals. The results of simulations and measurements and also margin analyses are discussed.

Effect of interface charge on the dc bias stress-induced deformation and shift of the transfer characteristic of amorphous oxide thin-film transistors

The presence of a deformation or hump in the subthreshold region of the transfer characteristic of Amorphous Oxide Semiconductor (AOS) Thin-Film Transistors (TFTs) has been observed after DC stress and related to different causes. In previous works, it has been shown that in devices with active-layer thickness greater than 120nm, a region with relatively high conductivity remains near the back interface of the active layer, providing a parallel current path between drain and source giving rise to this deformation. If this is the cause of the hump, it should be present independently of bias stress. However, experiments show that the hump is observed in AOS TFTs with active layer thickness below 120nm and only after DC stress. In this work we show that, if during DC bias stress, the density of positively charged states at the interface between the active layer and the passivation layer of an AOS TFT becomes high enough to provide a parallel conduction path, the deformation or hump in the transfer curve can appear. This condition is more likely to occur in devices passivated with dielectrics that can present charged traps at the dielectric–semiconductor interface and agrees well with experimental data reported for AOS TFTs.