Parallel Chien Search Research Articles

Low-delay parallel Chien search architecture for RS decoder

Low-delay parallel Chien search architecture for RS decoder

Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization

To achieve a high-throughput decoder, massive-parallel computations are normally applied to the Chien search, but the parallel realization increases the hardware complexity significantly. To reduce the hardware complexity of the parallel Chien search, this brief proposes a 2-D optimization method. In contrast to the previous 1-D optimizations, the proposed method maximizes the sharing of common subexpressions in both the row and column directions. All the partial products needed in the parallel structure are represented in a single matrix, and the finite-field adders are completely eliminated in effect. Simulation results show that the proposed 2-D optimization leads to a significant reduction of the hardware complexity. For the (8191, 7684, 39) BCH code, the count of xor gates in the parallel Chien search is reduced by 92% and 22%, compared to the straightforward and strength-reduced structures, respectively.

Efficient Generalized Minimum-distance Decoders of Reed-Solomon Codes

Generalized minimum distance (GMD) decoding of Reed---Solomon (RS) codes can correct more errors than conventional hard-decision decoding by running error-and-erasure decoding multiple times for different erasure patterns. The latency of the GMD decoding can be reduced by the Kotter's one-pass decoding scheme. This scheme first carries out an error-only hard-decision decoding. Then all pairs of error-erasure locators and evaluators are derived iteratively in one run based on the result of the error-only decoding. In this paper, a more efficient interpolation-based one-pass GMD decoding scheme is studied. Applying the re-encoding and coordinate transformation, the result of erasure-only decoding can be directly derived. Then the locator and evaluator pairs for other erasure patterns are generated iteratively by applying interpolation. A simplified polynomial selection scheme is proposed to pass only one pair of locator and evaluator to successive decoding steps and a low-complexity parallel Chien search architecture is developed to implement this selection scheme. With the proposed polynomial selection architecture, the interpolation can run at the full speed to greatly increase the throughput. After efficient architectures and effective optimizations are employed, a generalized hardware complexity analysis is provided for the proposed interpolation-based decoder. For a (255, 239) RS code, the high-speed interpolation-based one-pass GMD decoder can achieve 53% higher throughput than the Kotter's decoder with slightly more hardware requirement. In terms of speed-over-area ratio, our design is 51% more efficient. In addition, compared to other soft-decision decoders, the high-speed interpolation-based GMD decoder can achieve better performance-complexity tradeoff.

Design of High-Speed Decoder for New High-Speed Bus

This paper presents a new type of high-speed error correction for the requirements of new high-Speed Bus. Use RS (255, 239). Not only optimization traditional algorithm, but also design bidirectional synchronous calculated adjoint form module, Fast B-M algorithm module. and full parallel Chien Search module. These design used in new high-Speed Bus, Larger than usual decoder designed to significantly shorten the critical path decoding, and achieve continuous decoding. In addition, this error correction system separated error detection and correction module modules, And after error detection module add intelligent control, which reduced the complexity and power consumption of equipment. The error correction system design for the requirements of the new bus which speed is above 400m / s.

Strength-Reduced Parallel Chien Search Architecture for Strong BCH Codes

The Chien search process is the most complex block in the decoding of Bose-Chaudhuri-Hochquenghem (BCH) codes. Since the BCH codes conduct the bit-by-bit error correction, they often need a parallel implementation for high throughput applications. The parallel implementation obviously needs much increased hardware. In this paper, we propose a strength reduced architecture for the parallel Chien search process. The proposed method transforms the expensive modulo-f(x) multiplications into shift operations, by which not only the hardware for multiplications but also that for additions are much reduced. One example shows that the hardware complexity is reduced by 90% in the implementation of binary BCH (8191, 7684, 39) code with the parallel factor of 64. Consequently, it is possible to achieve a speedup of 64 with only 13 times of the hardware complexity when compared with the serial processing.