Parallel Analog-to-digital Converters Research Articles

An Enhanced Photonic-Assisted Sampling Approach for Spectrum-Sparse Signal by Compressed Sensing

Spectrum-sparse signals are vital for wideband radars and wireless communication applications. A high-speed analog-to-digital converter (ADC) with the capacities of tens of gigahertz sampling rates is often required to acquire these signals. In this work, an enhanced photonic-assisted sampling approach with the combination of the photonic-assisted time-interleaved ADC and compressed sensing techniques is presented, which enables the measured signal to be reconstructed through very few samples by utilizing the sparsity of the spectrum-spare signal. An ultrahigh spectral resolution Fourier dictionary is introduced to suppress the spectrum leakage and obtain the actual sparse expression of the spectrum-sparse signals. Moreover, a layered tracking orthogonal matching pursuit signal recovery algorithm is employed to reduce computational complexity and enhance processing speed. The performance of the proposed approach has been investigated via simulations and laboratory experiments by varying the applied spectrum-sparse signals over 100 times. The experimental result demonstrated that the proposed approach can capture the blind-frequency spectrum-sparse signal at the equivalent sampling rate of 1 GS/s by utilizing four parallel ADCs with a sampling rate of 50 MS/s. It is proven that the proposed approach achieves ~5 times higher equivalent sampling rate than the conventional PTIADC at the same sampling rate. This work provides a useful method for the acquisition of spectrum sparse signals in practical applications.

Nonlinear error analysis and calibration model for cyclic ADCs in large array CMOS image sensors

A mathematical model is established to study the impact of nonlinear errors on the performance of cyclic analog-to-digital converters (ADCs) and imaging quality of CMOS image sensors (CIS). And a radix-based foreground digital calibration method for cyclic ADCs in large array CIS is proposed and modeled. The nonlinear errors caused by capacitor mismatch and finite operational amplifier (OPAMP) gain are mainly studied. Simulation results show that the proposed calibration method based on the statistical characteristics of large array CIS can effectively reduce the influence of nonlinear errors, greatly improve ADC linearity under large capacitor mismatch and finite OPAMP gain. In a CIS with 1500 columns of parallel ADCs, when the capacitor mismatch and OPAMP gain are 1% and 40 dB respectively, the effective number of bits (ENOB) of the calibrated ADC can be increased from about 6bit to 13bit. These results provide a new guideline for the calibration of cyclic ADCs in large array CMOS image sensors.

Time- and Frequency-Interleaving: Distinctions and Connections

This paper connects the linear steady-state systematic error models of the time- and frequency-interleaved analog-to-digital converters (ADCs). Exposing their relations is of importance because estimation and compensation methods developed for one architecture may therefore apply to the other. Most critical impairments in both ADC structures include static mismatches and random jitter. The former has been well studied and can be generalized to the model connection, whereas not much is known regarding the latter. To support designers becoming more capable of making optimal design and architectural decisions on parallel ADCs, comprehensive phase noise analysis and comparison are carried out to reveal the distinctions between these two sampling architectures. Design examples with considerations are also provided for demonstration purposes.

An 8-Gs/s 12-Bit TIADC System With Real-Time Broadband Mismatch Error Correction

High sampling speed can be achieved using multiple Analog-to-Digital Converters (ADCs) based on the Time-Interleaving A/D Conversion (TIADC) technique. Various types of methods were proposed to correct the mismatch errors among parallel ADC channels in TIADC systems, which would deteriorate the system performance. Traditional correction methods based on digital signal processing have good performance, however often only for input signals limited in a narrow frequency band. In this paper, we present our recent work on design of an 8-Gsps 12-bit TIADC system and implementation of real-time mismatch correction algorithms in FPGA devices, over a broad band of input signal frequencies. Tests were also conducted to evaluate the systems performance, and the results indicate that the Effective Number of Bits (ENOB) is enhanced to be better than 8.5 bits (<800 MHz) and 8 bits from 800 MHz to 1.6 GHz after correction, almost the same with that of the ADC chip employed.

The Flash ADC [A Circuit for All Seasons

Flash analog-to-digital converters (ADCs) find wide application both as stand-alone components and as building blocks of more complex systems. This architecture dates back to at least the early 1960s. For example, in a patent filed in 1963, Stephenson [1] describes the parallel ADC as a known technique. In this article, we study the properties and design issues of this topology.

Millimeter Wave Receiver Design Using Low Precision Quantization and Parallel &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta \Sigma $ &lt;/tex-math&gt; &lt;/inline-formula&gt; Architecture

The use of high-frequency millimeter wave (mmWave) bands for 5G communication systems has received much attention over the last few years. Analog-to-digital converters (ADCs) contribute significantly to the implementation cost and power consumption of wireless receivers. The use of large antenna arrays in mmWave communications causes these costs to rise even further. Using low precision quantizers in ADCs can reduce these costs significantly. In this paper, we propose a novel receiver design using low precision quantizers drawing ideas from the parallel ADC design literature. Utilizing structural similarities between multi-antenna receivers and parallel ADCs, we show that the signal-to-noise ratio and achievable rate, respectively, scale linearly and logarithmically with the number of antennas. We also extend the idea to the scenario where multiple streams can be transmitted simultaneously. Our simulations of the receiver show promising bit error rate performance under different scenarios and also show how error control coding can be incorporated to improve performance. All our designs depend only on symbol rate sampling, which eliminates costly oversampling of high bandwidth signals.

A Low-Power Pilot-DAC Based Column Parallel 8b SAR ADC With Forward Error Correction for CMOS Image Sensors

Successive-Approximation-Register (SAR) Analog- to-Digital Converters (ADC) have been shown to be suitable for low-power applications at aggressively scaled CMOS technology nodes. This is desirable for many mobile and portable applications. Unfortunately, SAR ADCs tend to incur significant area cost and reference loading due to the large capacitor array used in its Digital-to-Analog Converter (DAC). This has traditionally made it difficult to implement large numbers of SAR ADC in parallel. This paper describes a compact 8b SAR ADC measuring only 348 μm×7 μm. It uses a new pilot-DAC (pDAC) technique to reduce the power consumption in its capacitor array; moreover, the accuracy of the pDAC scheme is protected by a novel mixed-signal Forward Error Correction (FEC) algorithm with minimal circuit overhead. Any DAC error made during pDAC operation can be recovered later by an additional switching phase. Prototype measurements in 0.18 μm technology shows that the DAC's figure-of-merit (FoM) is reduced from 61.3 fJ/step to 39.8 fJ/step by adopting pDAC switching with no apparent deterioration in Fixed-Pattern Noise (FPN) and thermal noise.

Impact of Decorrelation Techniques on Sampling Noise in Radio-Frequency Applications

Analog-to-digital converter (ADC) noise limits the dynamic range of many radio-frequency systems for test and measurement, sensor, and communications applications. Improvements in the total dynamic range (as measured by the SNR) can be achieved by combining M ADCs in parallel, yielding an increase in SNR of M if the noise is fully uncorrelated across ADC units. However, the presence of correlated noise will limit the SNR improvement to a factor less than <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> . Noise in an ADC is due to thermal processes, quantization, and clock jitter. In an array of ADCs, thermal and quantization noise are independently generated in each ADC, but if a common clock is used, its jitter will generate correlated sampling noise in all the ADCs in the array. In this paper, we analyze and experimentally measure the impact of previously proposed harmonic decorrelation techniques on the sampling noise of an array of parallel ADCs driven by a common clock, sampling at an intermediate frequency. Both theory and experiments reveal that the decorrelation techniques reduce the total sampling noise by half, which is a result that could substantially relax clock requirements for high-dynamic-range systems and thus reduce clock costs.

Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation

The paper describes the implementation of a novel Analog-to-Digital-Converter (ADC) test technique for next generation low cost massive parallel ADC testing using a Field Programmable Gate Array (FPGA) on tester load board. The goal is to test the ADC which is embedded in an automotive micro controller with only pure digital tester sources. Therefore, the analog test stimulus for the ADC is generated by using ??-modulation technique off-line and analog filtering on load board. The digital test response is analyzed by a FPGA in real time by comparing the measured data with a reference signal. The modular concept of FPGA evaluation allows for quick and flexible reaction on changing production test requirements. Simply by reprogramming the FPGA with a new module there is no need of any hardware reconfigurations. Measurements with a high precision reference ADC in laboratory environment show that the method is ready for production.

Time-stretched ADC arrays

This brief analyzes the performance of a new type of analog-to-digital converters (ADCs) architecture. The approach contemplates stretching the analog signal in time prior to digitization. Its benefits include an increase in the effective sampling rate and the input bandwidth, and a reduction in the sampling-jitter noise of the digitizer. It builds on the recent demonstration of high-speed analog-to-digital (A/D) conversion where a photonic preprocessor was used to successfully stretch an analog electrical signal before electronic digitization. The brief considers parallel time stretch ADC arrays capable of processing continuous time signals. In particular the effects of interchannel offset and gain mismatch, and clock skew are described and are contrasted with those in a conventional time-interleaved system. A mode of operation unique to this system is outlined wherein interchannel mismatch errors are entirely avoided at the expense of resolution bandwidth.

Calibration of parallel ΔΣ ADCs

A method of calibrating the gain and offset of each channel in parallel /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) is presented. It uses a digital /spl Delta//spl Sigma/ modulator to perform fast and simple offline calibration. Simulations performed on the converter show greater than 30-dB reduction in unwanted tones when this calibration algorithm is used on an eight-channel second-order time-interleaved parallel converter with a 1% gain mismatch and 1-mV offset mismatch. The calibration method is general and can be used with any parallel /spl Delta//spl Sigma/ ADC including time-interleaved- and Hadamard-modulation-based architectures.