The Spectre family of attacks exploits speculative execution to access secret data and transmit it across isolation boundaries using a microarchitectural covert channel. Whereas prior work has predominantly examined the use of speculative loads for constructing such channels, we investigate speculative stores and flush operations across a wide range of Intel and AMD processors. We find that speculative memory operations either update the data cache or initiate page table walks. Depending on the microarchitecture, the walk may complete and update the TLB or be aborted after populating data caches, leaving clear microarchitectural traces of the translation. We further characterize the effects of page table attributes, memory fences, and cache-coherence states on this behavior. Building on these findings, we introduce a covert channel that leverages only the page table walk activity of speculative stores to encode information, without relying on store-induced cache fills. Finally, we demonstrate that Speculative Load Hardening (SLH)---a widely deployed Spectre-v1 mitigation in LLVM---does not prevent speculative store-based leakage of register values, consistent with its threat model and design assumptions.

The support for virtual memory is a key aspect of modern system on a chip (SoC). Traditional address translation schemes rely on a single translation lookaside buffer (TLB) entry to translate a virtual page to a physical page. To improve the TLB utilization, various TLB coalescing schemes merge multiple pages into a single TLB entry. TLB coalescing can be further enhanced by compressing multiple blocks into a group of page-table entries (PTEs). However, the previous compression schemes do not fully exploit the system characteristics and efficiently utilize PTE resources. To further enhance TLB coalescing, we propose the clustered range-compressed page table (cRCPT). This scheme combines compression and clustering techniques to improve the memory system performance. By exploiting potential spatial locality, the presented scheme can improve the address translation efficiency for high-bandwidth I/O devices.

The memory demand of modern applications has been rapidly increasing with the continuous growth of data volume across industrial and academic domains. As a result, computing devices (i.e., IoT devices, smartphones, and tablets) often experience memory shortages that degrade system performance and quality of service by wasting CPU cycles and energy. Thus, most operating systems rely on the swap mechanism to mitigate the memory shortage situation in advance, even if the swap memory fragmentation problem occurs over time. In this paper, we analyze the fragmentation behavior of the swap memory space within storage devices over time and demonstrate that the latency of swap operations increases significantly under aged conditions. We also propose a new extension of the traditional swap mechanism, called VSwap, that mitigates the swap memory fragmentation problem in advance by introducing two core techniques, virtual migration and address remapping. In VSwap, virtual migration gathers valid swap pages scattered across multiple clusters into contiguous regions within the swap memory space, while address remapping updates the corresponding page table entries to preserve consistency after migration. For experiments, we enable VSwap on the traditional swap mechanism (i.e., kswapd) by implementing it with simple code modifications. To confirm the effectiveness of VSwap, we performed a comprehensive evaluation based on various workloads. Our evaluation results confirm that VSwap is more useful and highly valuable than the original swap mechanism. In particular, VSwap improves the overall performance up to 48.18% by harvesting available swap memory space in advance with negligible overhead; it performs close to the ideal performance.

Virtual memory management (VMM) code is a critical piece of general-purpose OS kernels, but verification of this functionality is challenging due to the complexity of the hardware interface (the page tables are updated via writes to those memory locations, using addresses which are themselves virtualized). Prior work on verification of VMM code has either only handled a single address space, or trusted significant pieces of assembly code. In this paper, we introduce a modal abstraction to describe the truth of assertions relative to a specific virtual address space: [r]P indicating that P holds in the virtual address space rooted at r. Such modal assertions allow different address spaces to refer to each other, enabling complete verification of instruction sequences manipulating multiple address spaces. Using them effectively requires working with other assertions, such as points-to assertions about memory contents — which implicitly depend on the address space they are used in. We therefore define virtual points-to assertions to definitionally mimic hardware address translation, relative to a page table root. We demonstrate our approach with challenging fragments of VMM code showing that our approach handles examples beyond what prior work can address, including reasoning about a sequence of instructions as it changes address spaces. Our results are formalized for a RISC-like fragment of x86-64 assembly in Rocq.

The classical paging problem, introduced by Sleator and Tarjan in 1985, formalizes the problem of caching pages in RAM in order to minimize IOs. Their online formulation ignores the cost of address translation: programs refer to data via virtual addresses, and these must be translated into physical locations in RAM. Although the cost of an individual address translation is much smaller than that of an IO, every memory access involves an address translation, whereas IOs can be infrequent. In practice, one can spend money to avoid paging by over-provisioning RAM; in contrast, address translation is effectively unavoidable. Thus address-translation costs can sometimes dominate paging costs, and systems must simultaneously optimize both. To mitigate the cost of address translation, all modern CPUs have translation lookaside buffers (TLBs), which are hardware caches of common address translations. What makes TLBs interesting is that a single TLB entry can potentially encode the address translation for many addresses. This is typically achieved via the use of huge pages, which translate runs of contiguous virtual addresses to runs of contiguous physical addresses. Huge pages reduce TLB misses at the cost of increasing the IOs needed to maintain contiguity in RAM. This tradeoff between TLB misses and IOs suggests that the classical paging problem does not tell the full story. This paper introduces the Address-Translation Problem, which formalizes the problem of maintaining a TLB, a page table, and RAM in order to minimize the total cost of both TLB misses and IOs. We present an algorithm that achieves the benefits of huge pages for TLB misses without the downsides of huge pages for IOs.

The evolving memory landscape for larger capacity prompts alternative approaches due to scalability challenges in multi-level page tables, which require multiple serial memory accesses for address translation. Hashed Page Tables (HPTs) have gained attention for ideally facilitating a single memory access per translation. However, current HPTs increase minor page fault latency, thereby impeding its superiority over conventional multi-level page table design. This paper provides a comprehensive analysis of HPTs regarding minor page fault latency concerning memory management subsystems. In particular, we demonstrate how feasibility issues in memory management with HPTs can escalate minor page fault latency. We observe that different page types in HPTs (anon pages and page caches) exhibit distinct behaviors on the occurrence of minor page faults, indicating a significant correlation between page types and minor page faults. To address these challenges, we propose <i>HashScape</i>, a scheme that harmonizes with memory management using tailored HPTs per segment and size-tailored allocation via Virtual Memory Areas. Our evaluation demonstrates that HashScape significantly improves the insertion latency, with average, 95^th, and 99^th percentiles improving by 1.8<inline-formula><tex-math notation="LaTeX">$\boldsymbol{\times}$</tex-math></inline-formula>, 1.9<inline-formula><tex-math notation="LaTeX">$\boldsymbol{\times}$</tex-math></inline-formula>, and 2.2<inline-formula><tex-math notation="LaTeX">$\boldsymbol{\times}$</tex-math></inline-formula>, respectively, resulting in an overall 10% reduction in minor page fault latency compared to a state-of-the-art HPT design.

The non-uniform memory access (NUMA) architecture is the de facto norm in modern server processors. Applications running on NUMA processors may suffer significant performance degradation (NUMA effect) due to the non-uniform memory accesses, including data and page table accesses. Recent studies show that the NUMA effect of long-running memory-intensive workloads can be mitigated by replicating or migrating page tables to nodes that require accesses to remote page tables. However, this technique cannot adapt to the situation where other applications compete for the memory controller. Furthermore, it was only implemented on x86 processors and cannot be readily applied on ARM server processors, which are becoming increasingly popular. To address this issue, we designed the page table access latency aware (PTL-aware) page table auto-migration (Auto-PTM) mechanism. Then we implemented it on Linux ARM64 (the Linux kernel name for AArch64) by identifying the differences between the ARM architecture and the x86 architecture in terms of page table structure and the implementation of the Linux kernel source code. We evaluate it on real ARM NUMA servers. The experimental results demonstrate that, compared to the state-of-the-art PTM mechanism, our PTL-aware mechanism significantly enhances the performance of workloads in various scenarios (e.g., GUPS by 3.53x, XSBench by 1.77x, Hashjoin by 1.68x).

The density of memory cells in modern DRAM is so high that frequently accessing a memory row can flip bits in nearby rows. That effect is called Rowhammer, and an attacker can exploit this phenomenon to flip bits by rapidly accessing the contents of nearby memory rows. In recent years, researchers have developed sophisticated exploits based on this vulnerability, which enable privilege escalation on desktop computers, mobile devices, and even cloud systems without requiring any software vulnerability. However, rows are not equally vulnerable to Rowhammer. Therefore, an attacker has to massage the memory, for instance, with Page Table Entry (PTE) spraying, to increase the chance of successful exploitation. More bit flips mean the attacks become easier and faster to conduct. In this paper, we present Flipper, a Rowhammer amplification attack against DDR3, consisting of two components: cmpIST exploits the cmpsb and repe x86 instructions to get DRAM access with higher frequency. cmpP AR exploits the effect of hammering in multiple threads, which increases the number of bit flips found in a given time, as shown in previous work. As a result, we can increase the number of bit flips by a factor of 830 on the measured devices, even on systems featuring mitigation techniques, without using administrative privileges. We evaluate our technique on six DDR3 DIMMs. Although DDR3 memory has been superseded by DDR4 and DDR5 memory technologies, it is still widely used in devices that do not require frequent replacement, such as projectors, smart displays, servers, embedded devices, routers, and printers.

Modern embedded system on a chip (SoC) usually accommodates input/output (I/O) memory management units to support virtual memory. When a translation look-aside buffer (TLB) is miss, a page-table walk occurs and frequent page-table walks can significantly degrade the memory system performance. To improve TLB utilization, a number of TLB coalescing schemes have recently been reported. The TLB coalescing schemes exploit the contiguous memory allocation and can efficiently coalesce the contiguous virtual-to-physical page mappings into a single TLB entry. Accordingly, TLB coalescing schemes efficiently utilize TLB entries, reduce page-table walks, and can improve the memory system performance. However, the conventional page table is still organized in the page level and contains redundant page information. Subsequently, it is difficult for operating system to effectively represent the block-level contiguity in the page table and it is difficult for TLB coalescing hardware to exploit the contiguity. In this work, to improve the memory system performance, we propose a range compression technique in a page table. In the presented page-table entry, the redundant page attributes are removed and multiple block mappings are added. Considering high-bandwidth memory intensive mobile workloads, we conduct the performance experiments. As a result, the presented scheme can significantly perform better than the traditional scheme and the reference TLB coalescing schemes.

In the ever-evolving landscape of computing, operating system (OS) performance remains a paramount concern. Efficient memory management serves as the cornerstone of OS performance, ensuring seamless resource utilization and delivering a responsive user experience. This comprehensive study delves into the realm of advanced memory management techniques, meticulously exploring their impact on system performance and resource utilization. The study commences with a comprehensive overview of fundamental memory management concepts and techniques, laying the foundation for a deeper understanding of advanced approaches. It meticulously dissects the intricacies of paging, segmentation, and virtual memory, unraveling their underlying principles and implementation mechanisms. Venturing into the realm of advanced memory management techniques, the study delves into the intricacies of memory virtualization, a revolutionary paradigm that transcends the physical limitations of hardware memory. It elucidates the concepts of shadow page tables, copy-on-write (COW) techniques, and memory ballooning, unraveling their role in enhancing system flexibility, scalability, and isolation. To comprehensively assess the impact of advanced memory management techniques, the study employs a rigorous methodology, encompassing extensive experimentation and benchmarking. Through meticulous evaluation under diverse workloads and system configurations, the study unveils the performance gains and resource utilization benefits associated with each technique.

FIMAR: Fast incremental memory acquisition and restoration system for temporal-dimension forensic analysis

Virtual memory support is one of the major challenges of near-memory processing (NMP). Many previous works focused on this issue, but there are practical limitations that conventional CPU hardware or memory allocation schemes should be modified. Another technique uses a specialized page table for NMP to avoid such limitations. However, the previous work proposed NMP-specific page table that has static page table walk latency regardless of data size. This causes unnecessarily long address translation time for relatively small data. In this paper, we propose an operand-oriented technique for virtual memory support. Our scheme does not pre-determine the size of shared space; rather, it allocates shared space depending on the size of operands data for NMP. Then, we significantly reduce page table walk latency by using our flexible page table, which adapts the page table hierarchy to the size of shared spaces. To prove our concept, we implement our scheme in a full-system simulator and an FPGA-based verification platform. We then compared it with CPU's page table and the previous NMP-specific page table. The experimental results show that our technique outperforms page table walk latency by 69.3 percent and 43.8 percent compared to the CPU's page table and the comparison, respectively.

As the volume of data processed by applications has increased, considerable attention has been paid to data address translation overheads, leading to the widespread use of larger page sizes (“superpages”) and multi-level translation lookaside buffers (TLBs). However, far less attention has been paid to instruction address translation and its relation to TLB and pipeline structure. In prior work, we quantified the impact of using code superpages on a variety of widely used applications, ranging from compilers to web user-interface frameworks, and the impact of sharing page table pages for executables and shared libraries. Within this article, we augment those results by first uncovering the effects that microarchitectural differences between Intel Skylake and AMD Zen+, particularly their different TLB organizations, have on instruction address translation overhead. This analysis provides some key insights into the microarchitectural design decisions that impact the cost of instruction address translation. First, a lower-level (level 2) TLB that has both instruction and data mappings competing for space within the same structure allows better overall performance and utilization when using code superpages. Code superpages not only reduce instruction address translation overhead but also indirectly reduce data address translation overhead. In fact, for a few applications, the use of just a few code superpages has a larger impact on overall performance than the use of a much larger number of data superpages. Second, a level 1 (L1) TLB with separate structures for different page sizes may require careful tuning of the superpage promotion policy for code, and a correspondingly suboptimal utilization of the level 2 TLB. In particular, increasing the number of superpages when the size of the L1 superpage structure is small may result in more L1 TLB misses for some applications. Moreover, on some microarchitectures, the cost of these misses can be highly variable, because replacement is delayed until all of the in-flight instructions mapped by the victim entry are retired. Hence, more superpage promotions can result in a performance regression. Finally, our findings also make a case for first-class OS support for superpages on ordinary files containing executables and shared libraries, as well as a more aggressive superpage policy for code.

The demand for memory capacity has increased, and cloud energy usage has soared. The performance and scalability of virtualization interfaces in cloud computing are hampered by a lack of sufficient memory. To figure out this problem, a technique defined as memory deduplication is widely used to reduce memory consumption utilizing the page-sharing method. However, this method of memory deduplication using KSM has significant drawbacks, such as overhead owing to many online comparisons, which will consume so many CPU resources. In this research, a modified approach of Memory Deduplication of Static Memory Pages (mSMD), which is based on the identification of similar applications by Fuzzy hashing and clustering them using the Hierarchical Agglomerative Clustering approach, followed by similarity detection between static memory pages based on Genetic Algorithm and details stored in Multilevel shared page table, both operations performed in offline and final memory deduplication is carried out during online, is proposed for achieving performance optimization in virtual machines by reducing memory capacity requirements. When compared to existing techniques, the simulation results indicate that the proposed approach mSMD efficaciously minimizes the memory capacity required while improving performance.

Article Tools UNDERSTANDING THE PATHWAY Article Tools OPTIONS & TOOLS Export Citation Track Citation Add To Favorites Rights & Permissions COMPANION ARTICLES Randomized Phase II Trial of Ficlatuzumab With or Without Cetuximab in Pan-Refractory, Recurrent/Metastatic Head and Neck Cancer. March 28, 2023 ARTICLE CITATION DOI: 10.1200/JCO.23.00460 Journal of Clinical Oncology - published online before print June 15, 2023 PMID: 37319388 Rationale for Cotargeting Hepatocyte Growth Factor and Epidermal Growth Factor Receptor in Recurrent/Metastatic Head and Neck Cancer Stéphanie Kermorgant, PhD1xStéphanie KermorgantSearch for articles by this author Show More 1Spatial Signalling Group, Barts Cancer Institute–a CR-UK Centre of Excellence, Queen Mary University of London, John Vane Science Centre, London, United Kingdom https://doi.org/10.1200/JCO.23.00460 First Page Full Text PDF Figures and Tables © 2023 by American Society of Clinical OncologySUPPORTSupported by Rosetrees Trust (M314 and M346), Barts Charity (MGU0511, G-001868, G-002205), and the MRC (MR/R009732/1).AUTHOR'S DISCLOSURES OF POTENTIAL CONFLICTS OF INTERESTRationale for Cotargeting Hepatocyte Growth Factor and Epidermal Growth Factor Receptor in Recurrent/Metastatic Head and Neck CancerThe following represents disclosure information provided by the author of this manuscript. All relationships are considered compensated unless otherwise noted. Relationships are self-held unless noted. I = Immediate Family Member, Inst = My Institution. Relationships may not relate to the subject matter of this manuscript. For more information about ASCO's conflict of interest policy, please refer to www.asco.org/rwc or ascopubs.org/jco/authors/author-center.Open Payments is a public database containing information reported by companies about payments made to US-licensed physicians (Open Payments).No potential conflicts of interest were reported. Companion Randomized Phase II Trial of Ficlatuzumab With or Without Cetuximab in Pan-Refractory, Recurrent/Metastatic Head and Neck Cancer

Most database management systems cache pages from storage in a main memory buffer pool. To do this, they either rely on a hash table that translates page identifiers into pointers, or on pointer swizzling which avoids this translation. In this work, we propose vmcache, a buffer manager design that instead uses hardware-supported virtual memory to translate page identifiers to virtual memory addresses. In contrast to existing mmap-based approaches, the DBMS retains control over page faulting and eviction. Our design is portable across modern operating systems, supports arbitrary graph data, enables variable-sized pages, and is easy to implement. One downside of relying on virtual memory is that with fast storage devices the existing operating system primitives for manipulating the page table can become a performance bottleneck. As a second contribution, we therefore propose exmap, which implements scalable page table manipulation on Linux. Together, vmcache and exmap provide flexible, efficient, and scalable buffer management on multi-core CPUs and fast storage devices.

Article Tools CASE REPORTS Article Tools OPTIONS & TOOLS Export Citation Track Citation Add To Favorites Rights & Permissions COMPANION ARTICLES No companion articles ARTICLE CITATION DOI: 10.1200/PO.22.00697 JCO Precision Oncology no. 7 (2023) e2200697. Published online June 1, 2023. PMID: 37262390 Response to Repotrectinib After Development of NTRK Resistance Mutations on First- and Second-Generation TRK Inhibitors Monica F. Chen , MD1,2xMonica F. ChenSearch for articles by this author; Soo-Ryum Yang, MD3xSoo-Ryum YangSearch for articles by this author; Jinru Shia , MD3xJinru ShiaSearch for articles by this author; Jeffrey Girshman , MD4xJeffrey GirshmanSearch for articles by this author; Sippy Punn, RN5xSippy PunnSearch for articles by this author; Clare Wilhelm , PhD1xClare WilhelmSearch for articles by this author; Mark G. Kris, MD1xMark G. KrisSearch for articles by this author; Emiliano Cocco , PhD6xEmiliano CoccoSearch for articles by this author; Alexander Drilon , MD1,2xAlexander DrilonSearch for articles by this author; and Nitya Raj , MD5xNitya RajSearch for articles by this author Show More 1Thoracic Oncology Service, Division of Solid Tumor Oncology, Department of Medicine, Memorial Sloan Kettering Cancer Center and Weill Cornell Medicine, New York, NY2Early Drug Development Service, Division of Solid Tumor Oncology, Department of Medicine, Memorial Sloan Kettering Cancer Center and Weill Cornell Medical College, New York, NY3Department of Pathology, Memorial Sloan Kettering Cancer Center and Weill Cornell Medical College, New York, NY4Department of Radiology, Memorial Sloan Kettering Cancer Center and Weill Cornell Medical College, New York, NY5Gastrointestinal Medical Oncology Service, Division of Solid Tumor Oncology, Department of Medicine, Memorial Sloan Kettering Cancer Center and Weill Cornell Medical College, New York, NY6Department of Biochemistry and Molecular Biology/Sylvester Comprehensive Cancer Center, University of Miami, Miller School of Medicine, Miami, FL*M.F.C. and S.-R.Y. contributed equally to this work as cofirst authors. A.D. and N.R. contributed equally to this work as cosenior authors. https://doi.org/10.1200/PO.22.00697 First Page Full Text PDF Figures and Tables © 2023 by American Society of Clinical OncologySUPPORTSupported by grants from the National Cancer Institute (R01CA226864 to E.C. and A.D; and P30CA008748 to M.F.C., S.-R.Y., J.S., J.G., M.G.K., A.D., N.R.); and Nonna’s Garden Foundation (to A.D.).AUTHORS' DISCLOSURES OF POTENTIAL CONFLICTS OF INTERESTThe following represents disclosure information provided by authors of this manuscript. All relationships are considered compensated unless otherwise noted. Relationships are self-held unless noted. I = Immediate Family Member, Inst = My Institution. Relationships may not relate to the subject matter of this manuscript. For more information about ASCO's conflict of interest policy, please refer to www.asco.org/rwc or ascopubs.org/po/author-center.Open Payments is a public database containing information reported by companies about payments made to US-licensed physicians (Open Payments).Monica F. ChenStock and Other Ownership Interests: NordiskSoo-Ryum YangHonoraria: Prime EducationConsulting or Advisory Role: InVitaeJinru ShiaConsulting or Advisory Role: PAIGE.AIMark G. KrisConsulting or Advisory Role: AstraZeneca, Pfizer, Janssen, Merus, BerGenBioTravel, Accommodations, Expenses: Genentech, AstraZenecaOpen Payments Link: https://openpaymentsdata.cms.gov/physician/markgkris/summaryEmiliano CoccoEmployment: AstraZenecaConsulting or Advisory Role: Entos Pharmaceuticals, Institutional Biosafety CommitteeResearch Funding: Innocare, Erasca IncAlexander DrilonStock and Other Ownership Interests: Treeline BiosciencesHonoraria: Pfizer, Loxo/Bayer/Lilly, IASLC, Helsinn Therapeutics, BeiGene, Remedica, TP Therapeutics, Verastem, Ignyta/Genentech/Roche, AstraZeneca, Liberum, Lungevity, NIH, PER, OncLive/MJH Life Sciences, Clinical Care Options/NCCN, Lung Cancer Research Foundation, Associazione Italiana Oncologia Toracica (AIOT), Chugai Pharma, Sirio Libanes Hospital, Answers in CME, Research to Practice, i3 Health, RV MaisConsulting or Advisory Role: Ignyta, Loxo, AstraZeneca, Pfizer, Blueprint Medicines, Genentech/Roche, BeiGene, Hengrui Therapeutics, Exelixis, Bayer, Tyra Biosciences, Takeda/Millennium, BerGenBio, MORE Health, Lilly, AbbVie, 14ner Oncology/Elevation Oncology, Monopteros Therapeutics, Novartis, EMD Serono/Merck, Repare Therapeutics, Melendi, Archer, Nuvalent, Inc, Janssen, Amgen, Merus, Axis Pharma, Medscape, Liberum, Med Learning, PeerView, EPG Health, Journal of the National Comprehensive Cancer Network, Ology Medical Education, Ology Medical Education, Clinical Care Options, touchIME, Entos, Prelude Therapeutics, Applied Pharmaceutical Science, Treeline Biosciences, Monte Rosa TherapeuticsResearch Funding: Foundation MedicinePatents, Royalties, Other Intellectual Property: Wolters Kluwer (Royalties for Pocket Oncology)Other Relationship: Merck, GlaxoSmithKline, Teva, Taiho Pharmaceutical, Pfizer, PharmaMar, Puma Biotechnology, Pfizer, Merus, Boehringer IngelheimNitya RajConsulting or Advisory Role: Ipsen, HRA Pharma, Advanced Accelerator Applications/Novartis, ProgenicsResearch Funding: Novartis (Inst), Xencor (Inst), Corcept Therapeutics (Inst), ITM Isotope Technologies Munich (Inst), Camarus AB (Inst)No other potential conflicts of interest were reported.

Article Tools CASE REPORTS Article Tools OPTIONS & TOOLS Export Citation Track Citation Add To Favorites Rights & Permissions COMPANION ARTICLES No companion articles ARTICLE CITATION DOI: 10.1200/PO.22.00363 JCO Precision Oncology no. 7 (2023) e2200363. Published online May 24, 2023. PMID: 37224427 Exceptional Response to Dual Colony-Stimulating Factor 1 Receptor/PD-L1 Targeting After Primary Resistance to PD-1 Inhibition in a Patient With a Metastatic Uveal Melanoma Stéphane Champiat , MD, PhD1,2,3xStéphane ChampiatSearch for articles by this author; Hélène Salaün, MD4xHélène SalaünSearch for articles by this author; Francesca Lucibello, MD, PhD5xFrancesca LucibelloSearch for articles by this author; Jean-Yves Scoazec , MD, PhD6xJean-Yves ScoazecSearch for articles by this author; Benjamin Besse , MD, PhD7xBenjamin BesseSearch for articles by this author; Ana Ines Lalanne, PhD8,9xAna Ines LalanneSearch for articles by this author; Etienne Rouleau , MD, PhD6xEtienne RouleauSearch for articles by this author; Nolwenn Metzger , BSc10xNolwenn MetzgerSearch for articles by this author; Mathilde Saint-Ghislain, MD4xMathilde Saint-GhislainSearch for articles by this author; Thomas Ryckewaert, MD11xThomas RyckewaertSearch for articles by this author; Sophie Gardrat, MD11,12xSophie GardratSearch for articles by this author; Raymond Barnhill , MD, PhD13xRaymond BarnhillSearch for articles by this author; Nathalie Cassoux, MD, PhD14xNathalie CassouxSearch for articles by this author; Marc-Henri Stern , MD, PhD12xMarc-Henri SternSearch for articles by this author; Olivier Lantz, MD, PhD5,8,9xOlivier LantzSearch for articles by this author; Leanne de Koning , PhD13xLeanne de KoningSearch for articles by this author; Aurélien Marabelle , MD, PhD1xAurélien MarabelleSearch for articles by this author; and Manuel Rodrigues , MD, PhD4,12xManuel RodriguesSearch for articles by this author Show More 1Drug Development Department, Gustave Roussy Comprehensive Cancer Center, Villejuif, France2Department of Translational Research, University Paris-Saclay, Inserm U1015, Villejuif, France3University Paris-Saclay, Inserm, Clinical Investigation Center (CIC-BT1428) Biotheris, Villejuif, France4Medical Oncology Department, PSL Research University, Institut Curie, Paris, France5Center for Cancer Immunotherapy, INSERM U932, Institut Curie, PSL Research University, Paris, France6Department of Biopathology, University Paris-Saclay, Gustave Roussy Cancer Center, Villejuif, France7Paris Saclay University, Department of Cancer Medicine, Gustave Roussy, Villejuif, France8Clinical Immunology Laboratory, Institut Curie, Paris, France9Clinical Investigation Center (CIC-BT1428), Institut Curie, Paris, France10Department of Somatic Genetics, Institut Curie, PSL Research University, Paris, France11Department of Medical Oncology, Centre Oscar Lambret, Lille, France12Unit 830 (Cancer, Heterogeneity, Instability and Plasticity) INSERM, Institut Curie, PSL Research University, Paris, France13Department of Translational Research, Institut Curie, PSL Research University, Paris, France14Department of Ophthalmology, Institut Curie, PSL Research University, Paris, France*S.C., H.S., and F.L. are coprimary authors. https://doi.org/10.1200/PO.22.00363 First Page Full Text PDF Figures and Tables © 2023 by American Society of Clinical OncologySUPPORTM.R. was supported by the Interface INSERM program. The MATCH-R trial was supported by a Natixis foundation grant, a Philanthropy Lombard-Odier foundation grant, and Gustave Roussy Foundation. MOSCATO trial was supported by Gustave Roussy Foundation (Revolution Cancer initiative), INCa-DGOS-INSERM 6043 (SIRIC SOCRATE), and ANR-10-IBHU-0001 (MMO) and received an unrestricted grant from Genentech and Sanofi.DATA SHARING STATEMENTThe data that support the findings of this study are available upon reasonable request to the corresponding author, M.R.AUTHOR CONTRIBUTIONSConception and design: Stéphane Champiat, Hélène Salaün, Jean-Yves Scoazec, Olivier Lantz, Aurélien Marabelle, Manuel RodriguesProvision of study materials or patients: Stéphane Champiat, Jean-Yves Scoazec, Etienne Rouleau, Nathalie Cassoux, Aurélien MarabelleCollection and assembly of data: Stéphane Champiat, Hélène Salaün, Francesca Lucibello, Jean-Yves Scoazec, Mathilde Saint-Ghislain, Thomas Ryckewaert, Sophie Gardrat, Nathalie Cassoux, Aurélien Marabelle, Manuel RodriguesData analysis and interpretation: Stéphane Champiat, Jean-Yves Scoazec, Benjamin Besse, Ana Ines Lalanne, Etienne Rouleau, Nolwenn Metzger, Raymond Barnhill, Marc-Henri Stern, Olivier Lantz, Leanne de Koning, Aurélien Marabelle, Manuel RodriguesManuscript writing: All authorsFinal approval of manuscript: All authorsAccountable for all aspects of the work: All authorsAUTHORS' DISCLOSURES OF POTENTIAL CONFLICTS OF INTERESTThe following represents disclosure information provided by authors of this manuscript. All relationships are considered compensated unless otherwise noted. Relationships are self-held unless noted. I = Immediate Family Member, Inst = My Institution. Relationships may not relate to the subject matter of this manuscript. For more information about ASCO's conflict of interest policy, please refer to www.asco.org/rwc or ascopubs.org/po/author-center.Open Payments is a public database containing information reported by companies about payments made to US-licensed physicians (Open Payments).Stéphane ChampiatHonoraria: Amgen, AstraZeneca, Bristol Myers Squibb, MSD, Novartis, Roche, Fresenius Kabi, Eisai Europe, Genmab, Janssen, Merck KGaA, Merck SeronoConsulting or Advisory Role: Alderaan Biotechnology, Amgen, AstraZeneca, Avacta Life Sciences, Celanese, Domain Therapeutics, Ellipses Pharma, Genmab, Immunicom, Nanobiotix, Oncovita, Pierre Fabre, Seagen, Tatum Bioscience, Tollys, UltraHuman8, NextCure, BioNTech SEResearch Funding: AstraZeneca (Inst), Bristol Myers Squibb (Inst), Boehringer Ingelheim (Inst), Janssen-Cilag (Inst), Merck (Inst), Novartis (Inst), Pfizer (Inst), Roche (Inst), Sanofi (Inst), AbbVie (Inst), Adaptimmune (Inst), Aduro Biotech (Inst), Agios (Inst), Amgen (Inst), arGEN-X BVBA (Inst), Arno Therapeutics (Inst), Astex Pharmaceuticals (Inst), AstraZeneca (Inst), Bayer (Inst), BB Biotech Ventures (Inst), BeiGene (Inst), BioAlliance Pharma (Inst), BioNTech (Inst), Blueprint Medicines (Inst), Boehringer Ingelheim (Inst), Boston Pharmaceuticals (Inst), Bristol Myers Squibb (Inst), Celgene (Inst), Cephalon (Inst), Chugai Pharma (Inst), Clovis Oncology (Inst), Cullinan Oncology (Inst), Daiichi Sankyo (Inst), Debiopharm Group (Inst), Eisai (Inst), Lilly (Inst), Exelixis (Inst), FORMA Therapeutics (Inst), GamaMabs Pharma (Inst), Genentech (Inst), Gilead Sciences (Inst), GlaxoSmithKline (Inst), Glenmark (Inst), H3 Biomedicine (Inst), Roche (Inst), Incyte (Inst), Innate Pharma (Inst), Pierre Fabre (Inst), Servier (Inst), Janssen-Cilag (Inst), Kura Oncology (Inst), Kyowa Hakko Kirin (Inst), Loxo (Inst), Lytix Biopharma (Inst), MedImmune (Inst), Menarini (Inst), Merck KGaA (Inst), Merck Sharp & Dohme (Inst), Merrimack (Inst), Merus (Inst), Millennium (Inst), Molecular Partners (Inst), Nanobiotix (Inst), Nektar (Inst), Nerviano Medical Sciences (Inst), Novartis (Inst), Octimet (Inst), OncoEthix (Inst), OncoMed (Inst), Oncopeptides (Inst), Onyx (Inst), Orion (Inst), Oryzon Genomics (Inst), Ose Pharma (Inst), Pfizer (Inst), PharmaMar (Inst), Philogen (Inst), Pierre Fabre (Inst), Plexxikon (Inst), RigonTEC (Inst), Sanofi/Aventis (Inst), Sierra Oncology (Inst), Sotio (Inst), Syros Pharmaceuticals (Inst), Taiho Pharmaceutical (Inst), Tesaro (Inst), Tioma Therapeutics (Inst), Wyeth (Inst), Xencor (Inst), Y's Therapeutics (Inst), Cytovation, Eisai/H3 Biomedicine, ImCheck therapeutics, Molecular Partners, MSD, OSE Immunotherapeutics, Pierre Fabre, Sanofi, Sotio, Transgene, Boehringer Ingelheim, AbbVie, Amgen, Adlai Nortye (Inst), AVEO (Inst), Basilea Pharmaceutical (Inst), BBB Technologies (Inst), Bicycle Therapeutics (Inst), CASI Pharmaceuticals (Inst), CellCentric (Inst), CureVac (Inst), Faron Pharmaceuticals (Inst), ITeos Therapeutics (Inst), Relay Therapeutics (Inst), Seagen (Inst), Transgene (Inst), Turning Point Therapeutics (Inst), GlaxoSmithKline (Inst)Patents, Royalties, Other Intellectual Property: T-cell immunogens derived from anti-viral proteins and methods of using same WO2010039223A2Travel, Accommodations, Expenses: MSD, AstraZeneca, Amgen, Bristol Myers Squibb, Merck, OSE Immunotherapeutics, Roche, SotioOther Relationship: AstraZeneca (Inst), Bayer (Inst), Bristol Myers Squibb (Inst), Boehringer Ingelheim (Inst), Boehringer Ingelheim (Inst), Johnson & Johnson (Inst), Lilly (Inst), MedImmune (Inst), Merck (Inst), Pfizer (Inst), Roche (Inst), Roche (Inst), GlaxoSmithKline (Inst), NH TherAguix (Inst)Hélène SalaünTravel, Accommodations, Expenses: PfizerBenjamin BesseResearch Funding: AstraZeneca (Inst), Inivata (Inst), AbbVie (Inst), Amgen (Inst), Sanofi (Inst), Daiichi Sankyo (Inst), Janssen Oncology (Inst), Roche/Genentech (Inst), Aptitude Health (Inst), Chugai Pharma (Inst), Genzyme (Inst), Ipsen (Inst), Turning Point Therapeutics (Inst), Eisai (Inst), Ellipses Pharma (Inst), Genmab (Inst), Genzyme (Inst), Hedera Dx (Inst), MSD Oncology (Inst), PharmaMar (Inst), Taiho Pharmaceutical (Inst), Socar (Inst)Etienne RouleauHonoraria: AstraZeneca (Inst), Roche (Inst), BMS (Inst), GlaxoSmithKline (Inst), Clovis Oncology (Inst), MSD Oncology (Inst), MSD Oncology (Inst), MSD Oncology (Inst)Consulting or Advisory Role: AstraZenecaResearch Funding: AstraZeneca (Inst)Travel, Accommodations, Expenses: AstraZeneca, BMSMathilde Saint-GhislainHonoraria: OncostreamNathalie CassouxTravel, Accommodations, Expenses: FCI (Inst)Marc-Henri SternHonoraria: GlaxoSmithKlineConsulting or Advisory Role: GlaxoSmithKlineResearch Funding: Bionano Genomics (Inst)Patents, Royalties, Other Intellectual Property: Royalties on the licensing of the HRD patent included in the myChoice HRD test (Inst)Olivier LantzHonoraria: BiomunexResearch Funding: Biomunex (Inst), Transgene (Inst)Patents, Royalties, Other Intellectual Property: BioLegend royalties for 3C10 antibody (Inst)Aurélien MarabelleStock and Other Ownership Interests: Shattuck Labs, Centessa Pharmaceuticals, Deka Biosciences, HotSpot Therapeutics, Marengo TherapeuticsConsulting or Advisory Role: Lytix Biopharma, EISAI, Pierre Fabre, AstraZeneca, Servier, Roche, Redx Pharma, Sotio, Innate Pharma, ImCheck therapeutics, MSD, OSE Immunotherapeutics, HiFiBiO Therapeutics, Centessa Pharmaceuticals, Clover Biopharmaceuticals, Shattuck Labs, Deka Biosciences, Hotspot Therapeutics, Medicxi, Depth Charge Therapeutics, BioLineRx, Gritstone Bio, Johnson & Johnson/Janssen, Third Rock Ventures, Sanofi, PegaOne, Guidepoint Global, Neogene Therapeutics, Gray Wolf Therapeutics, AdageneResearch Funding: Bristol Myers Squibb (Inst), Boehringer Ingelheim (Inst), Transgene (Inst), MSD (Inst)Patents, Royalties, Other Intellectual Property: Monoclonal antibodies against CD81 (Stanford University)Travel, Accommodations, Expenses: SotioOther Relationship: ElsevierManuel RodriguesHonoraria: ImmunocoreConsulting or Advisory Role: AstraZeneca, GlaxoSmithKlineResearch Funding: Daiichi Sankyo/AstraZenecaTravel, Accommodations, Expenses: AstraZenecaNo other potential conflicts of interest were reported.

Article Tools FLASHBACK FOREWORD Article Tools OPTIONS & TOOLS Export Citation Track Citation Add To Favorites Rights & Permissions COMPANION ARTICLES Randomized Phase II Trial Comparing Bevacizumab Plus Carboplatin and Paclitaxel With Carboplatin and Paclitaxel Alone in Previously Untreated Locally Advanced or Metastatic Non-Small-Cell Lung Cancer. April 26, 2023 ARTICLE CITATION DOI: 10.1200/JCO.22.02790 Journal of Clinical Oncology - published online before print April 26, 2023 Flashback Foreword: Bevacizumab + Carboplatin/Paclitaxel in NSCLC Thomas E. Stinchcombe , MD1,2xThomas E. StinchcombeSearch for articles by this author Show More 1Associate Editor, Journal of Clinical Oncology, Alexandria, VA2Duke Cancer Institute, Durham, NC https://doi.org/10.1200/JCO.22.02790 First Page Full Text PDF Figures and Tables © 2023 by American Society of Clinical OncologyTHE TAKEAWAYThis randomized phase II trial1 compared carboplatin and paclitaxel alone (the control arm) with carboplatin and paclitaxel with bevacizumab at two doses in patients with non–small-cell lung cancer (NSCLC). Bevacizumab 15 mg/kg once every 3 weeks was the dose selected for future clinical trials, and an excessive rate of toxicity was observed in the subset of patients with squamous histology, leading to the exclusion of patients with NSCLC with squamous histology from future trials of bevacizumab in NSCLC.AUTHOR'S DISCLOSURES OF POTENTIAL CONFLICTS OF INTERESTFlashback Foreword: Randomized Phase II Trial Comparing Bevacizumab Plus Carboplatin and Paclitaxel With Carboplatin and Paclitaxel Alone in Previously Untreated Locally Advanced or Metastatic Non–Small-Cell Lung CancerThe following represents disclosure information provided by the author of this manuscript. All relationships are considered compensated unless otherwise noted. Relationships are self-held unless noted. I = Immediate Family Member, Inst = My Institution. Relationships may not relate to the subject matter of this manuscript. For more information about ASCO's conflict of interest policy, please refer to www.asco.org/rwc or ascopubs.org/jco/authors/author-center.Open Payments is a public database containing information reported by companies about payments made to US-licensed physicians (Open Payments).Thomas E. StinchcombeThis author is an Associate Editor for Journal of Clinical Oncology. Journal policy recused the author from having any role in the peer review of this manuscript.Consulting or Advisory Role: EMD Serono, Janssen Oncology, Turning Point Therapeutics, Sanofi/Aventis, GlaxoSmithKline, Genentech/Roche, Daiichi Sankyo/Astra Zeneca, Takeda, Eisai/H3 Biomedicine, G1 Therapeutics, Spectrum PharmaceuticalsResearch Funding: AstraZeneca (Inst), Takeda (Inst), Regeneron (Inst), Seattle Genetics (Inst), Mirati Therapeutics (Inst), Genentech/Roche (Inst)No other potential conflicts of interest were reported. Companion Randomized Phase II Trial Comparing Bevacizumab Plus Carboplatin and Paclitaxel With Carboplatin and Paclitaxel Alone in Previously Untreated Locally Advanced or Metastatic Non-Small-Cell Lung Cancer

Extended Page Table switching with VMFUNC is a hardware isolation mechanism available in Intel CPUs. VMFUNC is attractive for low overhead and the possibility to isolate privileged kernel code. However, many careful design decisions are needed to ensure the security of the isolation boundary.