Package Interconnects Research Articles

Exploiting the Spatial Homogeneity of Adlayer Breakdown on Microelectrodes to Develop a Kinetic Model for S-NDR Copper Electrodeposition

Copper electrodeposition is a major component in integrated circuit manufacturing, ranging across lengthscales from nanoscale damascene plating to 100s of microns for thorugh-silicon-vias used in 3D interconnect packaging.1 Critical to this process is electrodeposition of void-free copper structures in high aspect ratio cavities, which is achieved with various additives that enable superconformal bottom-up filling. This physicochemical phenomenon is driven by an S-shaped negative-differential resistance (S-NDR), which promotes spatial bifurcation of the electrode surface into active and passive deposition regions. 2 Electrode bifurcation is dependent on additive adsorption/desorption kinetics, chemical species transport, and electrode geometry. Prior studies have demonstrated that the active/passive bifurcation is dependent on electrode size and that reduced electrode dimensions will permit a homogeneous reaction across the electrode.3 In this work, microelectrodes are used to experimentally probe the critical breakdown behavior in acid copper-sulfate electrolytes in the presence of micromolar concentrations of chloride and a single polymeric additive. In-situ optical microscopy indicates that the entirety of the microelectrode surface (either 12.5 or 25 μm in diameter) is either active or passive during cyclic voltammetry measurements, permitting current to be normalized to the geometric electrode area. Experimental electrolyte parameter sweeps cover chloride concentration, polymer concentration, copper concentration, and polymer adsorption kinetics (i.e. polymer type). These measurements are compared to static macroscopic electrodes and rotating disk electrodes at dimensions known to exhibit active/passive bifurcation. Experimental measurements are fit to finite element method computations using a two-additive model tracking the adsorption and rate-dependent desorption for chloride and polymer species. This work is an extension of previous computational models for describing S-NDR behavior in single additive systems.4-5 Kinetic constants for copper electrodeposition as well as adsorption and desorption dependent rate constants for chloride and polymer are fit to experimental cyclic voltammograms. Electrochemical kinetic constructs using microelectrodes and a 2-additive adsorption/consumption model provide a more accurate representation of critical breakdown phenomenon in S-NDR electrochemical systems. References T.P. Moffat, J.E. Bonevich, W.H. Huber, A. Stanishevsky, D.R. Kelly, G.R. Stafford, and D. Josell, “Superconformal Electrodeposition of Copper in 500-90 nm Features”, J. Electrochem. Soc., 147 (2000) 4524.T.P. Moffat and D. Josell, “Extreme Bottom-Up Superfilling of Through-Silicon-Vias by Damascene Processing: Suppressor Disruption, Positive Feedback and Turing Patterns”, J. Electrochem. Soc., 159 (2012) D208.S. Bozdech, K. Krischer, DA. Crespo-Yapur, E. Savinova, and A. Bonnefont, “1/f2 noise in bistable electrocatalytic reactions on mesoscale electrodes”, Faraday Discuss., 193 (2016) 187.D. Wheeler, T.P. Moffat, and D. Josell, “Spatial-temporal modeling of extreme bottom-up filling of through-silicon vias”, J. Electrochem. Soc., 160 (2013) D3260.D. Josell and T.P. Moffat, “Superconformal bottom-up nickel electrodeposition in high aspect ratio through silicon vias”, J. Electrochem. Soc., 163 (2016) D322.

High Density, Tall Cu Pillars for 3D Packaging

Abstract With demands for shrinking footprints and increasing I/O of electronic components, there is an increasing interest in electrodeposited Cu pillar structures for Package on Package (PoP) interconnects. One example of interest involves a 3D package integration approach with the memory mounted above the processor for mobile applications. This paper will explore the processes required and discuss the challenges for Cu pillar fabrication of PoP interconnects at sub 100um pitches. The test vehicles will include variables such as pillar diameter and pitch for a 200um thick liquid film negative tone plating resist on a 300mm wafer format. The high-density pillar pitch is expected to present challenges to resist material applications, lithography capability, and plating capability. Work for this paper is supported by major material and tool suppliers for resist materials, lithography tools, and plating chemistries & plating tools. JSR Micro, Rudolph Technologies, Atotech

Formation of highly preferred orientation of β-Sn grains in solidified Cu/SnAgCu/Cu micro interconnects under temperature gradient effect

β-Sn grain orientation and configuration are becoming crucial factors to dominate the lifetime of solder interconnects in three-dimensional integrated circuit packaging. In this paper, we found that a temperature gradient during solidification significantly dominated the orientation and configuration of the final β-Sn grains in Cu/SnAgCu/Cu micro interconnects. Being different from the random orientations and growth fronts meeting or cyclic twin boundary forming near the center after homogeneous temperature bonding, the β-Sn grains solidified under a certain temperature gradient were observed to follow a highly preferred orientation with their c-axis departing from the direction of temperature gradient by about 45°–88°. Meanwhile, these preferred oriented β-Sn grains consisted of low angle grain boundary structures with misorientation in the range of 0°–15°. The mechanism was explained in terms of the anisotropy and directional growth of β-Sn grains. The results pave the way for grain orientation control in 3D packaging technology.

Development of Fan Out Package Platform for High Performance and RF Applications

ABSTRACT Over the last few years quite significant and well publicized advancements have been made in the IC industry in the potential adoption of fan out wafer level package platforms for both analog and digital applications. HD-FO platforms are likely to find significant adoption in the mobility, consumer application space as these have the capability to achieve sub-micron package routing density, high processor/memory and interconnect band width, very thin package height and small foot print area. Development of HD-FO package development reported in this work includes:Multiple advanced silicon technology nodesBroad range of package sizesSingle die, multi-die packagesDifferent package configurations that include with substrate, without substrate, organic and inorganic package redistribution layer optionsSystem in Package (SiP) for RF applications An electrical simulation based lateral and vertical interconnect insertion loss comparison is being reported for high density fan out packages and silicon interposer with through silicon via (TSV). Multiple metal layers, interconnect widths, organic and inorganic redistribution layers are modelled. High density fan out package provides orders of magnitude less vertical interconnect loss in comparison to TSV. Least lateral interconnect insertion loss is demonstrated by organic interconnect based HDFO package. For RF applications HDFO package based inductors of 1.1nH and 3.3nH demonstrate ~ 3 X improvements in Qmax when compared to similar CMOS based inductors. In addition to providing differentiating technology value propositions through the advanced HD-FO packaging platform collaborative ecosystem, customer centric business model and flexible supply chains are also being built to meet the business requirements for the integrated circuit customers. Finally, silicon/package co-design environment and RF enablement will ensure that customers realize the benefits of seamless product design, fast yield feedback and reduced time to market.

Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect

The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5-D/3-D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent on the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, whereas excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This article presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die (8 × 11 × 0.780 mm) with 11,343 ultrafine pitch (62 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behavior and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e., cleaning and underfill) as well as product reliability.

Polynomial-Based Surrogate Modeling of RF and Microwave Circuits in Frequency Domain Exploiting the Multinomial Theorem

A general formulation to develop electromagnetic-based polynomial surrogate models in the frequency domain utilizing the multinomial theorem is presented in this paper. Our approach is especially suitable when the number of learning samples is very limited and no physics-based coarse model is available. We compare our methodology against four other surrogate modeling techniques: response surface modeling, support vector machines, generalized regression neural networks, and Kriging. Results confirm that our modeling approach has the best performance among these techniques when using a very small amount of learning base points on relatively small modeling regions. We illustrate our technique by developing a surrogate model for a substrate integrated waveguide interconnect with transitions to microstrip lines, a dual-band T-slot planar inverted-F handset antenna, and a high-speed package interconnect. Examples are simulated on a commercially available 3-D FEM simulator.

Addressing Flux Dip Challenges for 3D Integrated Large Die, Ultra-fine Pitch Interconnect

Abstract The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5D/3D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent upon the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces in order to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, while excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This paper presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die with ultra-fine pitch (60 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behaviour and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e. cleaning and underfill) as well as product reliability.

Preparation of nanoparticle and nanowire mixed pastes and their low temperature sintering

A new mixed nano paste consisting of silver nanoparticles, silver nanowires and copper nanoparticles has been proposed as the active material in an alternative joining approach for interconnection in electronic packaging. The mixed nano paste was optimized by adding different contents of copper nanoparticles into silver nanoparticle and nanowire pastes. Compared with the common silver nanoparticle paste, the electrochemical migration time of this mixed nano paste increased with greater addition of copper nanoparticles. Silver nanowires were also found to decrease the resistance of this mixed nano paste effectively due to their continuity. Although higher additions of copper nanoparticles into the mixed nano paste could facilitate the desired result of anti-electrochemical migration, they also decrease the shear strength of the sintered joints using the mixed pastes. In order to balance anti-electrochemical migration and sintering properties of the mixed nano pastes, when 10% copper nanoparticles were added to the mixed silver nanoparticle and nanowire pastes, the average shear strength of sintered joints at 250–350 °C was above 25 MPa. Based on the comprehensive properties, the mixed silver nanoparticle nanowire with 10% copper nanoparticle pastes were determined to be a better paste for sintered connections in electrical packaging.

Compact photonic crystal integrated circuit for all‐optical logic operation

Photonic integrated circuits (PICs) will be pushed to electronic integrated circuits in the forthcoming decade because of its package density, interconnections, improved functionality and cost effectiveness. In this study, the authors propose a new configuration of photonic crystal (PhC) integrated circuits to realise the operation of all-optical logic AND function that operates at a speed of hundreds of gigabits per second. The integrated circuit comprises of lasers, waveguide couplers, logic gate, amplifier and threshold limiter in a two-dimensional (2D) silicon PhC platform. The behaviour of the proposed structure is qualitatively analysed by the use of 2D finite-difference time-domain method. The results show that the integrated circuit performs the required logic operation. The average area required for the entire device including regenerated circuit is 25 × 10 μm 2 . The overall response time is <;2 ps. This device is one of the promising platforms for future optical computers and optical signal processor.

Numerical Investigation on Atomic Migration Effect on Thermal Conductivity of Al/Cu Interface Structures in Electronic Interconnection Packaging

The thermal conductivity of Al/Cu interface structures in electronic interconnection packaging is studied based on NEMD method by considering the atomic migration under different temperatures in this work. An interesting phenomenon is discovered that the thermal conductivity of Al/Cu interface increases with the increasing of atomic migration and diffusion from 400K to 600K; However, it decreases when the temperature is over 600K. It may be caused by the recrystallization of aluminum atoms, which lead to the interface thermal resistance increasing. It means that the heat transfer efficiency can be artificially controlled by heat treatment in appropriate temperature range. This investigation is helpful for understanding the interface heat transfer mechanism of the interface structures, which also implies a potential method for the analysis of the interface thermal performance and design of the interface in electronic packaging micro/nano-manufacturing.

Dual ICP Si Etching and Vapor Deposition Polymerization Liner for Backside Via-Last TSV Packaging Process Integration

Smart ICT (Information and Communication Technology) such as “Big Data”, “Cloud computing” and Smart Functionalities such as Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. To realize above-mentioned Smart Technologies, high-density, low-power consumption, wide-bandwidth, fast-operation semiconductor devices as well as smart functional devices enabled by integrating functionalities with advanced semiconductor technologies including CMOS technologies are necessary. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and 2.1D PCB packaging are among key technologies to satisfy the requirements from the both smart semiconductor devices and smart functional devices. "Hetero 3D stacked" technologies are gathering the most attention from now on. These technologies can make a high density packaging interconnection by using TSV on the each function devises. Heterogynous 3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the cost of TSV fabrication is not still solved. In particular, the management of barrier metal film deposition on the smooth surface is most important technology for Cu diffuse protection [1]. On the other hand, TSV isolation liner materials with high step coverage and lower temperature deposition on the smooth surface for high frequency devices will be necessary in the future. “Scallop-free” etching process has developed for TSV fabrication [2]. In this paper, our high-density packaging technologies including scallop-free, low-temperature processed TSV solution for via-last packaging scheme and 2.1D packaging solutions on large panel build-up board by semiconductor manufacturer tools will be introduced. Especially, backside Via-last TSV process integration was proposed by “A Novel Dual ICP Plasma” Si etching and low-temperature "Vapor Deposition Polymerization (VDP)" liner (< 200 degree ) for lower-cost and low-stress hetero 3D chip stacked. “A Novel Dual ICP Plasma” is using 2 RF modes mixed ICP plasma. One is high frequency RF mode. And, another is low frequency RF mode. This plasma is able to generate high-density plasma (High etch rate), and also “Scallop-free” smooth etching. This is a kind of “Non-Bosch” process. On the other hand, this dual ICP plasma can carry out “Bosch” process at the same module. This system is very unique etching tool that can use for distinguishing between "Bosch" and "non-Bosch" to TSV cost reduction.

Numerical Investigation on Atomic Migration Effect on Thermal Conductivity of Al/Cu Interface Structures in Electronic Interconnection Packaging

At present, MEMS and micro/nano electronic packaging technology have an exhaustive range of applications in the field of mass-produced commercial products, such as cell phones, computer, automobiles, and pedometers, which cause a strong demand for the reliability of heat transfer in nano or micro scales. Wire bonding process has been widely used in the MEMS or devices packaging approach to create high aspect interconnection structures [1], hence, the thermal analysis, thermal design, and thermal management become more and more important for microelectronic system or microelectronic devices. The interfacial structures of dissimilar materials are suffering the high stress gradients due to the thermal and stiffness mismatches of the different materials [2, 3]. The interface structures of dissimilar materials are very prone to crack initiations under the heat flow effect. The heat transfer across the interface is a critical consideration for the thermal design in the IC or devices manufacturing. Here we reveal the relationship between the atomic migration and thermal conductivity of Al/Cu interface in nanoscale heat transfer by using non-equilibrium molecular dynamics method. To create the Al/Cu interface, the modified Embedded-atom method (EAM) for alloy is used to describe the interatomic interactions between Cu/Cu, and Al/Cu interface. The results show that the interfacial diffusion is enhanced with the increase of the temperature from 400K-600K. The thermal conductivity of the Al/Cu interface, first increases, and then decreases. When the temperature is over 600K, it reaches the recrystallization temperature of Al. which makes to Al atoms recrystallization. The recrystallization of Al atoms may reduce the heat transfer efficiency of the Al/Cu diffusion region. That is to say, it reduces the thermal conductivity of Al/Cu interface when the temperature is over 600K. This means that we can enhance the interfacial heat transfer efficiency of Al/Cu interface and the cooling efficiency of IC by heat treatment in advance on interface structures. This investigation is helpful for understanding the interfacial heat transfer mechanism of the interface structures in the IC, which is helpful for the design of the interface in micro/nano manufacturing and benefit for the estimate the reliability of the IC manufacturing. Figure 1

A review on the humidity reliability of high power white light LEDs

High power white LEDs are replacing current lighting sources, not only for indoor usage, but also for outdoor and harsher environmental applications. This calls for higher reliability with respect to electrical, thermal as well as humidity. In this work, a comprehensive review on the study of humidity reliability of high power LEDs is provided, and the humidity induced degradation mechanisms in packaged high power white LEDs and their failure sites are described. The failure degradation mechanisms are divided into three groups, namely the package level, chip level and interconnect level degradations. Modeling of the moisture degradation is also described, and new test designed for the humidity study is also introduced. The inability of current acceleration model to extrapolate accelerated test results to normal operating conditions for high power LEDs is shown, and this provides a new challenge for the estimation of the lifetime of high power LEDs under normal applications, along with other challenges that need to be addressed.

Nanofiber Anisotropic Conductive Films (ACF) for Ultra-Fine-Pitch Chip-on-Glass (COG) Interconnections

Nanofiber anisotropic conductive films (ACF) were invented, by adapting nanofiber technology to ACF materials, to overcome the limitations of ultra-fine-pitch interconnection packaging, i.e. shorts and open circuits as a result of the narrow space between bumps and electrodes. For nanofiber ACF, poly(vinylidene fluoride) (PVDF) and poly(butylene succinate) (PBS) polymers were used as nanofiber polymer materials. For PVDF and PBS nanofiber ACF, conductive particles of diameter 3.5 μm were incorporated into nanofibers by electrospinning. In ultra-fine-pitch chip-on-glass assembly, insulation was significantly improved by using nanofiber ACF, because nanofibers inside the ACF suppressed the mobility of conductive particles, preventing them from flowing out during the bonding process. Capture of conductive particles was increased from 31% (conventional ACF) to 65%, and stable electrical properties and reliability were achieved by use of nanofiber ACF.

In Situ Stress Measurements Using Cantilever Curvature: The Influence of Additives on Growth Stress

Electrodeposition is commonly used in electronic packaging, magnetic recording, and copper interconnections in printed circuit boards and integrated circuits. The evolution of residual stress during thin film growth is complex, depending on the microstructure, growth conditions, and material parameters. However, based on a large number of studies, a general understanding of the origins and mechanisms of residual stress is beginning to emerge.1 During film deposition, stress is small in the early stages, becoming tensile during the coalescence of nuclei into a continuous film. However, as films become thicker and the height becomes more uniform, the stress often reaches a constant steady-state value. Models have been developed that treat this steady state stress as a dynamic competition between tensile and compressive stress generation mechanisms that are largely governed by atomic mobility, microstructure, and deposition rate.1As a consequence, one can expect that the solution additives and alloying elements needed to achieve desired deposition rates and mechanical properties will contribute significantly to this stress development. In this study, the stress was measured with optical wafer curvature techniques that can be used during deposition to determine the real-time stress evolution.2 The measured curvature is proportional to the product of the average biaxial stress and the film thickness according to the Stoney equation. We refer to this quantity as the stress-thickness product. Figure 1 shows typical stress-thickness curves for Cu electrodeposited onto a Au-coated cantilever electrode from additive free 0.24 mol/L CuSO4 in 1.8 mol/L H2SO4. The reference electrode was saturated mercury - mercurous sulfate. In all cases the stress-thickness was tensile (i.e. > 0) and reached a constant slope after about 200 nm of Cu was deposited. If it can be assumed that the stress in previously deposited Cu does not relax during deposition, then the slope along any point of these curves corresponds to the incremental or instantaneous stress; i.e., the in-plane stress of new Cu being deposited at the surface. We will refer to the linear region where the incremental stress is constant as the steady-state stress (σss ). If we evaluate the slope in the thickness range of 250 nm to 300 nm, the steady state stress values range from 13 MPa to 116 MPa and increase as the deposition potential is made more negative. This is consistent with current stress generating models that predict increasingly tensile growth stress as the growth rate is increased.1Figure 1 also shows the stress-thickness for a 3-minute period following deposition where the Cu deposit is allowed to rest at the open-circuit potential. Little stress relaxation is observed at low to moderate overpotentials whereas relaxation of tensile stress is seen for large overpotentials. Although the relaxation of tensile stress is not extensively discussed in the literature, it is generally attributed to the reduction of coalescence-induced strain energy by surface diffusion. Figure 2 shows typical stress-thickness curves for Cu electrodeposited from the same 0.24 mol/L CuSO4 in 1.8 mol/L H2SO4electrolyte, but with the addition of 1 mmol/L NaCl and 88 mmol/L polyethylene glycol (PEG). The stress response is significantly altered from the additive-free case. For the same deposit thickness, the steady-state stress varies from -68 MPa at low overpotential to +55 MPa at more negative deposition potential. In addition, there is significant relaxation of compressive stress for the low-overpotential deposits following deposition at open circuit. Since compressive stress is generally attributed to the diffusion of atoms into grain boundaries as the film thickens, the addition of PEG-Cl has either reduced the coalescence-induced tensile stress or enhanced the generation of compressive stress by facilitating the mobility of Cu into and out of the grain boundary. This talk will examine the influence of organic additives on stress development, in the context of deposit microstructure and stress generating mechanisms that appear in the literature. 1. (a) E. Chason, Thin Solid Films, 526, 1 (2012); (b) E. Chason, A. Engwal, F. Pei, M. Lafouresse, U. Bertocci, G.R. Stafford, J.A. Murphy, C. Lenihan, D.N. Buckley, J. Electrochem. Soc., 160, D3285 (2013). 2. O. E. Kongstein, U. Bertocci, and G. R. Stafford, J. Electrochem. Soc., 152, C116 (2005). Figure 1

Mechanical and electrical characterisation of Au wire interconnects in electronic packages under the combined vibration and thermal testing conditions

This paper concerns the reliability of thermosonically bonded 25μm Au wires in the combined high temperature with vibration conditions, under which the tests have been carried out on wire-bonded 48-pin Dual-in-Line (DIL) High Temperature Co-fired Ceramic (HTCC) electronic packages. Mechanical, optical and electrical analysis has been undertaken in order to identify the failure mechanisms of bonded wires due to the combined testing. The results indicated a decrease in the electrical resistance after a few hours of testing as a result of the annealing process of the Au wire during testing. In general, ball shear and wire pull strength levels remained high after testing, showing no significant deterioration due to the tests under the combined high temperature and vibration conditions. However, a trend of the variation in the strength values is identified with respect to the combined conditions for all wire-bonded packages, which may be summarised as: (i) increase of the testing temperature has led to a decrease of both the shear and pull strength of the wire bonds; (ii) the mechanical behaviour of the wires is affected due to crystallisation that leads to material softening and consequently the deformation of wire.

Energy-Efficient Photonics in Future High-Connectivity Computing Systems

Energy-efficiency has become a critical parameter in the design of high-performance computing systems. Typically, compute elements consume the most energy in current systems, with memories and interconnect networks close behind. This paper proposes an energy-efficient, high-connectivity, petascale computing system for the year 2020 timeframe by addressing the energy requirements of these three components. We start with projections based on purely evolutionary computer system design trends, then include the impact of breakthroughs in processor design, memory packaging and optical interconnect technologies. Based on these projections, we motivate the development for a 1-pJ/b optical intrasystem interconnect technology that significantly increases system interconnect bandwidth and relieves the distance-based energy dependence of electrical alternatives. We show that improvements in compute, memory, and IO, when simultaneously applied, become a vision for many-chip photonically-interconnected modules that could lead to an order of magnitude improvement in energy efficiency in the 2020 timeframe. The vision hinges on a high-density, energy-efficient optical link that can connect electronic compute and memory elements across short chip-to-chip distances while also capable of kilometer or longer spans across data centers. We discuss the power budget to enable such a link and review experimental progress toward creating an ultra-dense, hybrid-integrated low-power silicon photonic link that will enable this vision.

Novel PCM-based coating for thermal management of high temperature electronic assemblies

The electronic components are exposed nowadays increasingly higher temperatures. On one site the power density is increasing and on the other site the electronic appliances are used in more and more harsh environments with high temperature loads. In worst case the combination of both can quickly lead to exceeding the critical temperature resulting in damage and total failure. There are a lot of investigations to increase the robustness of certain elements, like semiconductor and packaging materials, interconnections and PCB. Another approach for increasing the reliability of power electronic modules is the development of sophisticated thermal management system. Traditional cooling methods are coming up to their limits in high integrated electronic modules. A possible solution is the use of latent heat storage materials (PCM - phase change materials), which can be fully integrated into a compliant selective coating of critical electronic components [1], [2]. During phase change process the temperature peaks can be effectively smoothed by adsorbing and releasing the heat. This results directly in increasing of number of cycles until end of life.

BGA Board Level Reliability Analysis &amp; Optimization

The solder joint reliability of semiconductor package interconnects to printed circuit boards is critical for product durability. A dominant failure mode is solder fatigue due to the CTE mismatch between the BGA component and PCB at thermal cycling. However, it is well known that other factors can impact fatigue behavior and time to failure such as solder joint geometry, die geometry, solder system, etc. Finite element modeling (FEM) and simulation can play an integral role in providing deeper insight into the impact of these package parameters on the overall assembly. However, a major challenge of accurately modeling these systems includes simulation of multiple length scales from the package, substrate, and solder joints. The FEM approach addressing these can lead to reduced cycle time, accurate simulation, and improved package performance. In this work, the finite element modeling and simulation procedure is demonstrated for a BGA package at accelerated temperature cycling conditions. At the component level, key details regarding the properties and constituents of the BGA package mold compound and substrate are established by coupling measured experimental warpage data and finite element modeling. Comparison of simulated &amp; Thermoire measurements shows excellent agreement at the package level, with warpage correlation achieved over the entire temperature range. At the assembly level, the truncated sphere model is used to arrive at precise solder joint profiles for accurate representation to tie the package to the board. The combined validated package-level results and solder joint profiles are employed towards a subsequent thermo-mechanical analysis of the full BGA assembly. The entire simulation procedure is demonstrated for a BGA design, where inelastic creep and reliability test data are compared. High strain regions in the solder joint array are shown to compare closely with regions of failure from experimental reliability test data. The validated FEM model allows for extrapolating to similar package conditions allowing faster design cycle time and less time consuming experimental work.

Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond

Chip packaging interaction (CPI) has drawn great attention to advanced silicon technology nodes due to the introduction of Low-K (LK) and Ultra Low-K (ULK) materials in back end of line (BEOL) and Cu pillar in chip package interconnects. This paper summarizes GLOBALFOUNDRIES's activities in CPI studies for the 20 nm technology node, which includes CPI structure design, BEOL process characterization and optimization, assembly process optimization and reliability tests. The key issues and challenges were identified, analyzed, and overcome through a Design of Experiment (DOE) study in BEOL Q-time and reflow parameters in assembly process. It has been found that 1) BEOL ULK layer Q-time before SiCN capping is critical for moisture diffusion into BEOL materials, which affects both electrical performance and reliability; 2) Reflow temperature plays key role to control the package warpage to avoid non-wet issue. Package level reliability evaluation was performed and the results were reported. Through this study, it has been demonstrated that GLOBALFOUNDRIES's 20 nm technology successfully passed all CPI reliability tests. CPI challenges for future technology nodes and emerging packaging integration solutions are also discussed in the paper.