Package Interconnects Research Articles

High Quality Pt-Pt Metal Bonding for High Temperature Packaging.

Platinum is an ideal material for high-temperature resistant device packaging due to its higher melting point and good electrical properties. In this paper, the thermocompression bonding of Pt–Pt metal electrodes was successfully realized through process exploration, and the package interconnection that meets the requirements was formed. A square bump with a side length of 160 µm and a sealing ring with a width of 80 µm were fabricated by magnetron sputtering. Different pressure parameters were selected for chip-level bonding; the bonding temperature was 350 °C for about 20 min. Analysis of the interface under a scanning electron microscope found that the metal Cr diffused into Pt. It was found that two chips sputtered with 300 nm metal Pt can achieve shear resistance up to 30 MPa by flip-chip bonding at 350 °C and 100 MPa temperature and pressure, respectively. The leakage rate of the sample is less than 2 × 10–3 Pa·cm3/s, the bonding interface is relatively smooth, and the hot-pressed metal bonding of Pt electrodes with good quality is realized. By comparing the failure rates at different temperatures and pressures, the process parameters for Pt–Pt bonding with higher success rates were obtained. We hope to provide new ideas and methods for the packaging of high-temperature resistant devices.

Accelerated Solder Interconnect Testing Under Electromigratory and Mechanical Strain Conditions

Abstract Continuous power density increases and interconnect scaling in electronic packages raises risk of electromigration (EM) induced failures in high current interconnects. Concurrently, thermal cycling fatigue also places interconnects at risk of reliability failure during electronics' operating lifetime. These two differing failure mechanisms are historically treated separately, but in operation, the combination of EM effects and thermal cycling can act synchronously in accelerating failure. Presently, there is no model to predict the complexity of reliability estimation arising from these interacting failure modes but is certainly important for high current density applications. In this work, a novel testing system has been employed to facilitate the estimation of the reliability of solder interconnects under the combined influence of EM and mechanical strain. The system subjects solder interconnects to high current density, elevated ambient temperature, and a constant tensile stress while recording the change in electrical resistance and change in length of the solder over time. The solder samples were created using two copper wires connected by a eutectic Pb/Sn solder ball to imitate flip-chip or BGA packaging interconnects, allowing for controlled testing conditions in order to demonstrate the combined effects of a mechanical load and EM on the lifetime of a solder joint. A significant reduction in lifetime was observed for samples that endured the coupled accelerating factors. Comparing the experimental results of different current densities at different stress levels provided a new outlook on the nature of coupled failure acceleration in solders. This novel test methodology can inform model generation for better anticipating the failure rate of solder interconnects which naturally experience multiple stress inputs during their lifetime.

Enhancement mechanism of Te doping on microstructure, wettability and mechanical properties of Sn–Bi-based solder

Sn–Bi-based solder alloys have sparked tremendous research interest towards the development of low-temperature interconnecting materials in multi-level packaging interconnections electronic devices. Nevertheless, the research speed of solder is elusive to match well with the rapid development of integrated circuit design and manufacturing, which leads to the slow renewal course of electronic products. In the pursue for more effective modification strategies, Te was selected to be doped into Sn58Bi–1Sb (SBS) solder. As expected by the design, Te existed in the solder matrix in the form of solid solution and intermetallic compound simultaneously. To our satisfaction, Te enormously improved both the tensile strength and plasticity of the SBS solder. This largely circumvents the negative correlation between strength and plasticity during the modification process. Additionally, Te element significantly optimized the thermal properties, wettability, and creep resistance of SBS solder. Many tiny Bi particles embedded in Sn phase and strengthened the SBST solder matrix as the second phase. More strikingly, numerous Bi twin crystal structures were observed in the Sn58Bi–1Sb1Te (SBST) solder matrix, which occurred in Sn–Bi-based solder matrixes first time. The Bi phase twin represents preferable deformation ability of Bi phase and the plasticity of the solder matrix. It indicated that the doping of Te comprehensively enhanced the performance of SBS solder and may opened new horizons to the design route of alloying modification for Sn–Bi-based solder.

Numerical simulation of reliability of single-sided/double-sided package interconnect structure under temperature cyclic load

PurposeThe purpose of this paper is to compare the single-sided packaging structure and double-sided packaging structure of high-power module and study the overall heat dissipation performance and reliability of the module.Design/methodology/approachIn this paper, the single-sided packaging structure and double-sided packaging structure of power module are designed based on Wolfspeed products. This paper is analyzed by finite element method. First, the heat dissipation performance of single-sided packaging structure and double-sided packaging structure is analyzed; second, the deformation and stress of single-sided packaging structure and double-sided packaging structure are compared and analyzed; and finally, the cumulative plastic deformation of single-sided packaging and double-sided packaging structures are compared and analyzed, and the fatigue life of the structure is calculated based on the plastic deformation.FindingsIn the heat transfer simulation, under the same power input, the heat dissipation performance of single-sided packaging structure is not as good as that of double-sided packaging structure. Under the reliability simulation of the same temperature cycle standard, the maximum equivalent stress of single-sided packaging structure is lower than that of double-sided packaging structure, but the fatigue life prediction based on plastic strain shows that the fatigue life of double-sided packaging structure is not different from that of single-sided packaging structure.Originality/valueThis paper creatively simulates the thermal characteristics and reliability of single-sided packaging structure and double-sided packaging structure and proves the advantages of double-sided packaging structure compared with single-sided packaging structure from the aspects of heat transfer performance and reliability.

(Keynote) Interconnect Innovations in Next Generation of Heterogenous Packaging Technologies

Heterogenous device integration has become a critical capability need for the next generation of AI, Data Center, Graphics and FPGA devices. Advanced packaging technologies such as EMIB, Foveros & Co-EMIB are now enabling a dramatic increase in interconnect density and bandwidth, enabling integration of multiple types of heterogenous die (Logic, memory, transceiver and multiple nodes) onto a single package. In this talk, we will provide an overview of die-die and on package interconnect capabilities of these advanced packaging technologies. We will review innovations in metallization technologies that are enabling significant advances in on-package and within package interconnects. Finally, we will discuss technical advancements needed to drive the packaging technology roadmap forward.

(Invited) All Electrochemical Synthesis of Nanoporous Cu Films for the Purposes of Fine Pitch and Low Temperature Interconnection in 3D Packaging

Nanoporous Cu (np-Cu) films can be employed in the electronic packaging as materials facilitating chip-to-substrate interconnections, which is realized by Cu-on-Cu bonding. Unlike their bulk counterparts, np metals feature unique interconnected pore-ligament structure with a length scale in the range of single-to-tens of nanometers. This results in a high surface area-to-volume ratio accompanied with a substantially lower melting temperature. Research has been done in the field to experiment with Cu-on-Cu interconnects realized by np-Cu precursor films (1). While the initial results are undoubtedly promising, difficulties haver been met with sufficiently lowering the sintering / soldering temperature below 380-400oC. A way to address these shortcomings is to develop of approaches to sintering at much lower temperatures by introducing Sn into the np-Cu structures either directly or by coating then followed by processing to produce at lower sintering temperature Cu-Sn bonds with low resistivity and a greater current carrying capability than bare np-Cu. The foundation of this study relies on the development of fine structured np-Cu films with an open and uniform interconnected network of ultra-fine ligaments and pores of size preferably in the single digit nanometer range.The present report is focused on the development of a two-step all-electrochemical approach for the synthesis of the targeted np-Cu structures including (i) a controlled electrodeposition of Cu-based precursor alloy with a less-noble counterpart that is then (ii) selectively removed (de-alloyed) by anodization at appropriate potential to leave behind the desired “spongy” np-Cu structure (2). Therefore, the first part of this report introduces and discusses the development of protocols for flat and uniform deposition of Cu-Zn and Cu-Mn alloys that could both serve as precursors of the synthetically targeted np-Cu films. The choice of said alloy systems is motivated by the ability of Zn and Mn to form single-phase alloys or intermetallic compounds with Cu thus ensuring the ultra-fine length scale of the eventually synthesized np Cu structure. The alloy deposition routines included use of a pyrophosphate (P2O7 4-) plating bath for Cu-Zn alloys which were shown to have high stability and optimizable for the plating of smooth and fine-grained brass deposits (3). Also, ammonium sulfate with excess of ammonia as complexing agent, was employed in the optimization activity aimed at the deposition of continuous and relatively smooth Cu-Mn deposits (4). The report discusses the optimization of plating parameters and conditions along with the subsequent structural and compositional characterization of the accordingly deposited precursor alloys with 60 at % and higher representation of the less noble constituent.Next, the electrochemical de-alloying of as-deposited CuxZn(1-x) and CuxMn(1-x) precursor alloys on a gold substrate is introduced and discussed. Alike with the first part of the report, the emphasis is on the optimization routines that looked at the effect of de-alloying scan rate, de-alloying at different constant potentials, de-alloying bath, and precursor alloy composition on the morphology and composition of the resulting np-Cu. A valuable part of the report is the demonstration of how the implementation of best combinations of optimized parameters and conditions leads to the synthesis of interconnected pore-ligament thin film networks of np-Cu structures with average ligament sizes in the range of 15-30 nm. In conclusion, the discussion takes direction towards ideas and perspectives for improvement of the uniformity and further refinement of the pore ligament length scale. Finally, consideration is also given to the intended approaches to introduce Sn on or into the accordingly synthesized np-Cu films and eventually convert them to np-Cu-Sn alloy ready for sintering/soldering at low temperatures.

Relative importance of solder and wire bond defects on the maximum junction temperature of IGBT devices

The wear-out of interconnection packaging materials of Insulated-Gate Bipolar Transistors (IGBTs) during power cycling in Pulse Width Modulation (PWM) mode can induce a local temperature increase on the die surface, resulting in thermal runaway, and ultimately short-circuit failure. In this study, the effect of PWM power cycling on solder and wire bond aging states as well as on the surface temperature distribution and thermal resistance was measured by infrared camera and compared with microstructural analysis. Horizontal cracks in the solder close to the solder-die interface induced the highest thermal resistance increase. Comparatively, the impact of solder voids on the thermal resistance was lower, but this caused significant bow of the die due to solder redistribution. This may contribute to an increased stress intensity factor at the die edges and thus horizontal crack formation. Lift-off bonds can also locally increase the die surface temperature due to Joule heating at imperfect electrical contacts. Analytical expressions validated by measurements and electro-thermal Finite Element Modeling were developed to estimate the relative importance of the different defects for a wider range of module designs and operating conditions.

Enhancing the Paste Release on 55μm pads with Water-Soluble Type 7 SAC305 Solder Paste for High Density SIP Application

Abstract The ultra-fine SAC305 solder is widely used as the lead-free solder composition for interconnection in advanced packaging based on its advantages such as good joint strength, thermo-mechanical fatigue behavior and creep resistance. Stencil printing remains the technology of choice for system-in-package (SiP) assembly because of its benefits such as economy of usage, ease of process control, flexibility of usage and fast and wide range of process window. SiP involves the high-level integration of different components, Copper (Cu) pillar flip-chip dies and chips in one package to achieve multiple functions in one system. The need to accommodate ever increasing demand for reduced footprints requires the technology to constantly invent a range of Cu pillar 55μm diameter and smaller components. Many mobile communications SiP consist of 6 or more flip chips in a single package. Conventional flip-chip attach uses flux & Cu pillar solder cap for solder joint formation as it is challenging for solder paste to be printed on fine geometries below 70μm. Additional benefits of solder paste printing help eliminate non-wet Cu pillar defect rates and improve yield over conventional flux printing. Heraeus solder paste (AP series T7) makes use of ultra-fine spherical shape of solder powder to create strong metal coalesce for bonding during reflow process of Cu pillars mounting to substrates. For example, the smallest passive component in use today is 008004 and Cu pillar diameter of 70um, which has a stencil opening of 125μm and 70μm respectively. Further reduction in Cu pillar flip-chip diameter of 55μm will require further reduction in stencil opening to 55μm, thus testing the limits of current type 7 pastes. Current solder pastes (AP series T7) can meet the consistency of printability when the stencil opening is 70μm or more. With smaller stencil opening, down to 55μm, the printing performance is less than desired. In this paper we describe the stencil printing application on the enhanced version of type 7 paste with a reinvented flux. The application tests were carried out using 55μm stencil opening. This paper will report the results of this application test.

High-density low-loss millimeter-wave package interconnects with the impact of dielectric-material surface roughness

Heterogeneous package integration and chiplet approaches are the key technology to enable next-generation high performance small form-factor packages for emerging applications. Millimeter-wave packaging for fifth-generation and upcoming sixth-generation platforms also need to meet the high-density low signal-loss interconnect specifications utilizing advanced conductor and dielectric materials. This article presents the comparison of the liquid-based photoimageable dielectric (PID) and dry-film dielectric materials in terms of interconnect path losses that are critical in mm-wave frequency bands. The conductor loss being more dominant in the frequency bands and in thinner dielectric structures, we assess daisy chains and microstrip lines on 15-μm dielectric by measuring the S-parameters to quantify the impact of the surface roughness at around 28 GHz. Measured results from the daisy chain and microstrip line structures exhibit that the smooth surface of the liquid-based PID (3 nm) leads to 8%–32% lower signal loss in the dB scale than the 325-nm rough dry-film dielectric. The study provides comprehensive experimental results that the different material forms with various surface roughness largely impact the package-level interconnect loss.

Impact of Measurement Uncertainty on Correlation Quality for High-Speed Interconnects

The ever-increasing demand for higher bandwidth and lower loss makes the predictability of high-speed interconnect performance increasingly challenging. Validating models against measurements of manufactured test structures requires not only accurate methodology but also understanding of the uncertainty impact. S-parameter measurements, characterization of materials, manufacturing processes, and models constructed based on measured inputs all cause uncertainty in the performance metrics of interest. Therefore, it is critical to anticipate the results with the associated uncertainty to assess the correlation quality more objectively. This article investigates the reproducibility of measurements required for high-speed package interconnect validation through rigorous analysis and presents a methodology to quantify the impact of measurement uncertainty on commonly used performance metrics.

Numerical simulation of reliability of 2.5D/3D package interconnect structure under temperature cyclic load

In view of the structural warpage deformation and stress-strain problems of 2.5D and 3D package structures under the temperature cycling environment, the causes of structural warpage deformation and the difference of stress and strain between the two structures are analyzed by combining the results of finite element simulations. The most critical solder joints life of the two structures are calculated. The results show that the thermal mismatch of the package structure under temperature cyclic load leads to periodic warping deformation of the structure. The accumulation of CTE mismatch caused significant difference of the warping deformation. The warpage of the 2.5D package structure is much larger than that of the 3D package. Induced by the package layout and structure different, the stress responses to the temperature loading are different between 2.5D package and 3D package are greatly different. The dangerous solder joints of 2.5D/3D package structure are all at the outer edge of the grid. Some high stress also performed at the triple parts interconnections, i.e. the TSV, solder joints and the die. The life prediction was also conducted according to the accumulated plastic strain of dangerous solder joints, which indicated that with the same size and materials of the package design, 2.5D package structure produce more damage to the interconnection and result to a shorter lifetime. An optimization design should be considered to utilize this type of package.

Additive Manufacturing of a Wideband Capable W-Band Packaging Strategy

In this letter, we demonstrate a fully additively manufactured packaged $W$ -band amplifier with integrated bypass capacitors. This package was fabricated using a chip-first approach and aerosol jet printing (AJP). Package substrates (dielectrics), conductors, and interconnects are printed around a bare die attached to a carrier. This package uses shaped ramp interconnects, allowing for frequency agnostic performance of the interconnect with no impedance discontinuity, within the physical limits of the printer. High dielectric constant thin films of a polymer-matrix nanocomposite for bypass capacitors were printed using multimaterial AJP. The maximum measured packaged gain is 14.9 dB in the $W$ -band compared to the maximum bare die gain of 15.5 dB in the same frequency range. From 75 to 92 GHz, the average package loss is 1.1 dB including 3-mm transmission line, interconnects, and a ground-signal-ground (GSG) launch structure correlating to an average loss of 0.37 dB/mm.

Additive Manufacturing of a W-Band System-on-Package

In this article, we demonstrate the design, fabrication, and characterization of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> -band system-on-package (SoP). This package is fully additively manufactured using a chip-first process and aerosol jet printing. With this method, we implement a transceiver consisting of two bare die amplifiers for transmitted and received signals, a bare die switch, printed bypass capacitors, surface-mount resistors for biasing networks, and a printed patch antenna, operating between 77.1 and 79.0 GHz. The second patch antenna of the same design, fabricated simultaneously, is used to characterize the antenna performance alone and the packaged components. Package substrates (dielectrics), conductors, and interconnects are printed around bare die attached to a carrier. Thin-film bypass capacitor dielectrics were printed using multimaterial aerosol jet printing (MMAJP), where aerosols of barium titanate and polyimide inks are mixed in place to form a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{r}$ </tex-math></inline-formula> polymer matrix nanocomposite film. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> -band interconnect performance is achieved using conformal-shaped ramp interconnects, allowing for frequency agnostic performance of the interconnect with no impedance discontinuity, within the physical limits of the printer. The antenna alone achieves a maximum gain of 6.7 dBi at 78.3 GHz, and the SoP achieves a gain of 16.4 dBi for the package. We estimate the package loss to be 2.8 dB or 0.6 dB/mm, including interconnects.

The Evolution of Microstructure and Resistance in Electroplated Copper Films by Linear Integrated Laser Scanning Annealing

Thermal treatment is an effective way to decrease the resistivity and internal stress by inducing grain growth accompanied with redistribution of embedded impurities. With the narrowing of Cu interconnects in IC packaging, the increased resistance is becoming the main issue that hindering the electrical performance of IC. Herein, a laser annealing method by liner scanning (LALS) to anneal the Cu interconnects were reported which provide a gradient thermal field for the crystallographic/microstructure transition. The impacts of laser annealing on the sheet resistance of the electroplating Cu films were investigated in aspects of microstructure and phase field simulation. Cu films treated by LALS owned larger average grain size, better recrystallization fraction, and significantly higher average grain aspect ratio than conventional annealing, which indicated the increased driving force for grain boundaries evolution by LALS method. This study exhibited the direct evidence on the impacts of laser annealing process on the resistance of electroplated Cu films. The laser annealing process with a local temperature gradient caused a significant decline in Cu electrical resistance compared to the conventional annealing process, indicating its extraordinary potential in improving Cu wire conductivity. This work will provide a scientific basis for selecting the post-treatment process for electrodeposited Cu films to achieve ideal electrical properties and microstructure in electronics industry applications.

Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization

The emerging VLSI technology and simultaneously highly dense packaging of devices and interconnects in nano-scale chips have prosperously enabled realization of system-on-chip designs and advanced high-performance computing applications. Concurrently, these have aggravated inevitable challenges in miniaturized integrated circuits (ICs). One of the main limiters in the performance of high-speed VLSI designs is the on-chip interconnects. The emerging graphene based mixed carbon nanotube bundle (MCNTB) interconnects have been investigated as one of the most suited and physically realizable on-chip structure. The present work focuses on utilization of MCNTB as nano-interconnects in the optimized way. Determining optimized placement of CNTs in MCNTB configuration is tedious, skilful task and meagerly explored till date. This has been innovatively taken-up in the current work. In the present paper, novel and efficient particle swarm optimization (PSO) technique is explored and innovatively incorporated to obtain optimal distribution of CNTs in a given rectangular area. The objective function considered for the design is to maximize the tube density. Several signal integrity analyses have been executed. The proposed optimized mixed CNT bundle structure is compared with other different configurations of CNT bundle structures. It is analyzed that the proposed optimized MCNTB configuration produces highly favorable results and is apt suitable for futuristic nano IC designs. The different modelling and performance analyses are performed using MATLAB, SPICE and ADS EDA tools.

Research on IGBT Bonding Wires Crack Propagation at the Macro and Micro Scales

Under the action of a complex and harsh working environment, the damage of the IGBT power module's packaging interconnection structure is the primary failure mode. The crack propagation and the bonding interface and the bond point shedding in the bonding wires will seriously affect the device's electrical interconnection function and heat dissipation ability, resulting in its performance degradation and failure. In this work, the formulation and application of a multiscale approach combined with a cohesive zone model (CZM) were proposed to investigate IGBT bonding wires' crack propagation. Firstly, the cohesive force model's principle considering fatigue damage accumulation is analyzed, and the degradation multiscale simulation method of the critical structure of the power module is studied. Secondly, further research on IGBT bonding wires' degradation behavior is carried out based on the macro and micro scales. The IGBT power module key package structure's defect evolution model is established to analyze the damage evolution process of the critical package structure. Finally, the accuracy of the model is verified by the experiment analysis. Such a multiscale, mechanism-based cohesive zone model offers a promising approach for modeling and understanding the rate-dependent fracture of IGBT bonding wire crack evolution.

Directly Visualized Mechanical Strain Distribution in Package Interconnect Using Digital Image Correlation

For advanced package interconnects, analyzing strain distribution within the complex three-dimensional structure is important in order to design a mechanically reliable system. Electronic packages frequently undergo various types of deformation including tension, compression, bending, and thermal treatments. Failures under these loading modes can be prevented with accurate information of distribution and degree of the mechanical strains. This information, however, is difficult to obtain using conventional methods due to the small-sized packages with complex internal structures. It is also uncertain to rely on predictive results from analytical solutions because it is hard to theoretically calculate the complex strain mechanics, especially for the heterogeneously integrated structures. Therefore, experimental methods have been recently demanded for direct evaluation of mechanical deformation in the package interconnects.In this study, a novel method that visualizes and accurately measures the internal strain distribution in package interconnects is developed. This method is based on digital image correlation (DIC), which utilizes microscopic images of the internal structure. The DIC method is adopted by taking advantage of non-contact and full-field analysis capability. Images from both optical microscopy and scanning electron microscopy are utilized for the non-contact strain evaluation method for the micro-scale deformation analysis. In order to obtain clear image of the internal structure, mechanical polish is conducted to form cross-section. For image pattern tracking, micro/ nano sized particles are deposited onto the cross-section to serve as speckle pattern of the DIC analysis. After the specimen preparation, the digital images are obtained before and after a mechanical loading at a same position. The consecutive images are then compared to execute image tracking analysis to result in the microscopic deformation contour. The results can be fully adopted in prediction of failure site or failure modes by providing essential data such as weak spot or intensity of deformation. Using the quantitative strain information, predicting the failure cycle could be also possible based on mechanics of fatigue fracture.We demonstrate that this method is effectively utilized for various package interconnects including printed circuit boards (PCBs), flexible chip packages, and through-hole stress analysis in a 3-D stacked structure. Bending strain analysis of flexible packages and composite substrates, thermal strain analysis of the PCB interconnects are shown as applications of the thermo-mechanical reliability evaluation method. We believe that this experimental method will enable to fully understand the internal stress-strain behavior of the advanced package interconnects and flexible devices that require high mechanical reliability for commercialization.

Mechanical properties and microstructural evolution of solder alloys fabricated using laser-assisted bonding

The mass reflow (MR) process is widely used in electronic packaging interconnection. However, the conventional MR process can cause thermal damage to components and requires a long process time. The laser-assisted bonding (LAB) process is considered as an alternative soldering process for overcoming these limitations due to its extremely fast process time and high thermal selectivity. The LAB process causes low thermal damage; hence, it can be used to fabricate flexible and stretchable applications. This study investigates the mechanical properties, microstructural variation, and intermetallic reaction between the SAC 305 solder and Cu electrodes. The mechanical properties are investigated using shear tests, while the microstructure is analyzed using scanning electron microscopy and X-ray scans. Furthermore, the reliability of the LAB- and MR-produced SAC 305 solders is assessed using a high-temperature storage test. As a result, the intermetallic compound layer is found to be considerably thinner, and the volume of voids in the solder matrix is lower in the LAB-produced solder than that in the MR-produced solder. The mechanical properties of the LAB-produced solders are enhanced by these microstructural advantages.

Experimental and numerical simulation of mechanical behavior of micro-scale SAC305 solder joint based on joint height

Lead-free “copper wire/Sn-3.0Ag-0.5Cu (SAC305) solder/copper wire” sandwich-structured micro-scale solder joints with a constant diameter (d = 400 μm) and various heights (125, 225, and 325 μm) were adopted to carried out the mechanical behavior research. Experimentally, quasi-static shear and tensile experiments were conducted by using a precision dynamic mechanics analyzer (DMA Q800). Then, the micro-scale solder joint model was built to simulate shear and tensile behavior of solder joints using the finite element analysis software ABAQUS. The experimental results show that, when the solder joint diameter is fixed, the smaller the joint height is, the stronger the shear strength and tensile strength. Under the same test conditions (225 μm), the shear strength of micro-scale solder joints of the same size is lower than the tensile strength, which indicates that the service environment of electronic packaging interconnection solder joints under shear stress is more severe. In addition, the micro-scale solder joints fracture at the interface of the solder joint and copper wire under shear force, but in the middle of the solder joint under tensile force. Different fracture failure mechanisms are found by observing the cross sections under different stress states.

A Chip-First Microwave Package Using Multimaterial Aerosol Jet Printing

We show in this article two fully additively manufactured microwave packages with integrated active and passive components. Packages were constructed using a chip-first approach where package substrates (dielectrics) and interconnects (conductors) are built up around power amplifier bare die attached to carriers. Bypass capacitor dielectrics were printed using multimaterial aerosol jet printing, where aerosols of barium titanate and polyimide inks are mixed in place to fabricate a high dielectric constant polymer matrix nanocomposite film. The material properties of the film are characterized using three printed capacitors. We present S-parameter measurements to characterize small-signal performance, as well as load-pull measurements at the saturated output power. Finally, we demonstrate package performance after power cycling and temperature cycling to show the effect of aging on the part and the robustness of this packaging strategy. We measured a maximum packaged gain of 21.7 dB and a saturated output power of 21.9 dBm for a commercial-off-the-shelf (COTS) medium power amplifier specified to have a gain of 22 dB and a saturated output power of 22 dBm. The printed package-level performance is compared with the published bare die performance and a measured COTS packaged amplifier.