P-channel MOS Research Articles

Negative bias temperature instability in strained-Si p-MOSFETs

Strained-Si p-channel metal oxide semiconductor field effect transistors (MOSFETs) have become the performance boosters beyond 90 nm technology node. Reliability study of these devices is essential as only a few reports are available on this. In this work, we have explored the degradation mechanisms in these devices due to negative bias temperature instability (NBTI). Device simulation results have been calibrated with reported experimental data and a good agreement is observed. The reliability study of these devices has been performed using the two-stage model for defect creation. Study of the drain current degradation and comparison of threshold voltage shift after stressing between the strained-Si and Si channel p-MOSFETs have been performed. The threshold voltage degradation in strained-Si channel p-MOSFETs is found to be considerably higher than that in the bulk-Si devices due to higher fixed oxide charge and interface trap densities at the strained-Si/SiO2 interface.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 40 nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub20 nA/μm I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = -0.5 V and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 40 nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 40-nm Ge pMOS channel device.

16-Channel biphasic current-mode programmable charge balanced neural stimulation

BackgroundNeural stimulation is an important method used to activate or inhibit action potentials of the neuronal anatomical targets found in the brain, central nerve and peripheral nerve. The neural stimulator system produces biphasic pulses that deliver balanced charge into tissue from single or multichannel electrodes. The timing and amplitude of these biphasic pulses are precisely controlled by the neural stimulator software or imbedded algorithms. Amplitude mismatch between the anodic current and cathodic current of the biphasic pulse will cause permanently damage for the neural tissues. The main goal of our circuit and layout design is to implement a 16-channel biphasic current mode programmable neural stimulator with calibration to minimize the current mismatch caused by inherent complementary metal oxide semiconductor (CMOS) manufacturing processes.MethodsThis paper presents a 16-channel constant current mode neural stimulator chip. Each channel consists of a 7-bit controllable current DAC used as sink and source current driver. To reduce the LSB quantization error and the current mismatch, an automatic calibration circuit and flow diagram is presented in this paper. There are two modes of operation of the stimulator chip—namely, stimulation mode and calibration mode. The chip also includes a digital interface used to control the stimulator parameters and calibration levels specific for each individual channel.ResultsThis stimulator Application Specific Integrated Circuit (ASIC) is designed and fabricated in a 0.18 μm High-Voltage CMOS technology that allows for ±20 V power supply. The full-scale stimulation current was designed to be at 1 mA per channel. The output current was shown to be constant throughout the timing cycles over a wide range of electrode load impedances. The calibration circuit was also designed to reduce the effect of CMOS process variation of the P-channel metal oxide semiconductor (PMOS) and N-channel metal oxide semiconductor (NMOS) devices that will result in charge delivery to have less than 0.13% error.ConclusionsA 16-channel integrated biphasic neural stimulator chip with calibration is presented in this paper. The stimulator circuit design was simulated and the chip layout was completed. The chip layout was verified using design rules check (DRC) and layout versus schematic (LVS) design check using computer aided design (CAD) software. The test results we presented show constant current stimulation with charge balance error within 0.13% least-significant-bit (LSB). This LSB error was consistent throughout a variety stimulation patterns and electrode load impedances.

Effect of Body Bias on NBTI of p-MOSFETs

The effect of the body bias on the stability of the threshold voltage of p+ polysilicon gate p-channel MOS (pMOS) transistors stressed in the on-state is investigated. Special attention is given to pMOS transistors operating at low gate overdrive and non-zero body voltage. A mixed mode of degradation, including the usual negative bias temperature instability (NBTI) and the effect of hot-hole injection (HHI) into the gate oxide at high temperature, is reported. The relative importance of both the electric field in the gate oxide and the concentration of cold holes at the interface is pointed out for devices operating in the near threshold region. A kinetic model for NBTI/HHI is proposed.

Investigation of Threshold Voltage Shift in Gamma Irradiated N-Channel and P-Channel MOS Transistors of CD4007

Investigation of Threshold Voltage Shift in Gamma Irradiated N-Channel and P-Channel MOS Transistors of CD4007

Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors

Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) and effective charge (NEFF) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.

Superior NBTI in High-k SiGe Transistors–Part II: Theory

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained.

A novel high-speed CMOS circuit based on a gang of capacitors

ABSTRACTThere is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Design of a variation‐resilient single‐ended non‐volatile six‐input lookup table circuit with a redundant‐magnetic tunnel junction‐based active load for smart Internet‐of‐things applications

A variation-resilient single-ended six-input lookup table circuit, which makes it possible to implement any arbitrary six-input logic gates, is proposed. Since operating point is optimally tuned by the redundant magnetic tunnel junction devices after chip fabrication, adequate p-channel metal-oxide semiconductor (PMOS) feedback can be performed, which results in variation-resilient, energy-efficient operation. In fact, the energy consumption of the proposed circuit is 66% smaller than that of the conventional single-ended circuit.

Fully Depleted GeOI-Channel Junctionless pMOSFET with a Low-Resistance-Raised NiGe Alloy S/D

We fabricated a Ge junctionless p-channel metal–oxide–semiconductor field-effect transistor (JL pMOSFET) with a raised metal source/drain (S/D) composed of a metal alloy. An ultrathin-body Ge channel was trimmed to 10 nm, which is lower than the maximum depletion width, to completely switch off the device. The fabricated Ge JL pMOSFET containing a raised Ni/NiGe S/D exhibited a high on/off current ratio (Ion/Ioff) value (approximately 105 at VDS = −0.1 V). The S/D series resistance of the full metal S/D structure was exactly lower than the structures of Ge/NiGe and Ge bulk S/D. Synopsys Technology Computer-Aided Design tools were used to confirm the advantages of the full metal S/D structure and demonstrate the enhancement of the S/D resistance in a device with scaled gate length. The proposed scheme is suitable for reducing the series resistance of a device with minimized dimensions.

Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II

BackgroundD Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits.FindingsThe newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this, an optimum fuzzy inference system with fuzzy rules is proposed to enhance the performance and convergence of non-dominated sorting Genetic Algorithm-II by adaptive control of the exploration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types. What is more, the design parameters involving NMOS and PMOS channel widths and power supply voltage and the performance parameters including average power consumption and propagation delay time are linked. To do this, the required mathematical backgrounds are presented in this study.ConclusionThe optimum values for the design parameters of MOSFETs channel widths and power supply are discovered. Based on them the power delay product quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.

Enhancement of mobility in ultra-thin-body GeOI p-channel metal–oxide–semiconductor field effect transistors with Si-passivated back interfaces

Ultra-thin-body (UTB) germanium-on-insulator (GeOI) substrates with Si-passivated back interfaces have been fabricated by using advanced epitaxial-lift-off (ELO) technology. Performance of UTB GeOI p-MOSFETs with body thickness (Tbody) in the 4–16 nm range has also been characterized. Si-passivated back interfaces have been fabricated and found to be effective in mitigating the unpleasant hole-mobility degradation in the UTB GeOI regime owing to the suppression of the back interface scattering.

Hole Transconductance of [100] Long-Channel Si Nanowire Transistor

We examined the hole transport characteristics of Si nanowire (NW) p-channel metal-oxide semiconductor with [100] channel orientation [4.8 nm × 4.7 nm (thickness × width)] having different lengths (2 μm, 5 μm, 10 μm, and 20 μm). The NW devices fabricated by the top-down method using ultra-thin Si on insulator exhibit electrical transport properties appropriate for future high-end applications. Interestingly, various oscillation behaviors were observed in the transconductance characteristics of the device. A comparison with two-dimensional-like nano devices provides useful information for further understanding one-dimensional (1D) transport properties and such oscillation behaviors. Thus, a practical hole transport model for 1D long-channel devices is presented.

A 16-level-cell memory with c-axis-aligned a–b-plane-anchored crystal In–Ga–Zn oxide FET using threshold voltage cancel write method

We demonstrate a 16-level cell using a nonvolatile oxide semiconductor random access memory test chip based on c-axis-aligned a–b-plane-anchored crystal In–Ga–Zn oxide (CAAC-IGZO) FETs. The memory cell consists of a CAAC-IGZO FET, a p-channel metal–oxide–semiconductor Si FET, and a cell capacitor. Data are written using a threshold voltage cancel write method, and a read circuit composed of voltage followers outputs a read voltage. Using a 200 ns write time of the test chip, the obtained maximum read voltage distribution width is 37 mV in the case of 32768 memory cells. The distributions of 16 read voltages are separated from each other without overlapping, with a single voltage follower exhibiting a maximum read voltage distribution width of 25.3 mV. In the −40 to 85 °C temperature range, the voltage distribution range is 0.13 V, and the variation due to varying temperatures is 0.24 mV/°C.

Improvement of the short channel effect in PMOSFETs using cold implantation

In this paper, to suppress transient enhanced dopant diffusion and improve short channel effects, cold implantation (cold-IIP) was applied to contact PLUG implantation in P-channel metal oxide semiconductor field effect transistors (PMOSFETs). A shallow dopant profile was formed by the suppression of transient enhanced diffusion (TED) due to the reduction of end-of-range (EOR) defects. Threshold voltage roll-off and off current (Ioff) increment, which are caused by a reduction in the distance between the gate and contact, were improved compared with room temperature implantation (RT-IIP). Additionally, the drain induced barrier lowering was improved, and the on-current improvement was attributed to reducing the contact resistance through the reduction of EOR defects. The contact resistance was reduced by ∼6% of the RT-IIP. In the DRAM device, the standby current at a short propagation delay time (tPD) was reduced effectively due to the decrease in the Ioff and contact resistance for the cold-IIP case.

Structural and optical properties of silicon metal-oxide-semiconductor light-emitting devices

A silicon p-channel metal oxide semiconductor field-effect transistor (Si-PMOSFET) that is fully compatible with the standard complementary metal oxide semiconductor process is investigated based on the phenomenon of optical radiation observed in the reverse-biased p–n junction in the Si-PMOSFET device. The device can be used either as a two-terminal silicon diode light-emitting device (Si-diode LED) or as a three-terminal silicon gate-controlled diode light-emitting device (Si gate-controlled diode LED). It is seen that the three-terminal operating mode could provide much higher power transfer efficiency than the two-terminal operating mode. A new solution based on the concept of a theoretical quantum efficiency model combined with calculated results is proposed for interpreting the evidence of light intensity reduction at high operating voltages. The Si-LED that can be easily integrated into CMOS fabrication process is an important step toward optical interconnects.

Mobility enhancement of strained GaSb p-channel metal–oxide–semiconductor field-effect transistors with biaxial compressive strain**Project supported by the National Basic Research Program of China (Grant No. 2011CBA00602) and the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2011ZX02708-002).

Various biaxial compressive strained GaSb p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) are experimentally and theoretically investigated. The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V·s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxial compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.

Distribution characteristic of p-channel metal-oxide-semiconductor negative bias temperature instability effect under process variations

Negative bias temperature instability (NBTI) is a p-channel metal-oxide-semiconductor (PMOS) degradation mechanism, which becomes one of the important reliability concerns. The NBTI drastically influences device performance and circuit lifetime. On the other hand, the circuit performance is also affected by the fabrication-induced process variation when the transistor size shrinks to a nanometer-scale. In the presence of the fabrication-induced random variations, the NBTI aging process and its influence on PMOS device become a random process. In this paper, the joint effects of NBTI and process variations on PMOS device are investigated. Firstly, the influence of process variation on NBTI aging is analyzed based on the reaction-diffusion (R-D) mechanism. The NBTI-induced PMOS threshold voltage degradation depends not only on stress time but also on fabrication-determined process parameters, such as the initial threshold voltage and oxide thickness. Then the statistical model is proposed to model NBTI-induced aging under process variation, which captures the threshold voltage variation and oxide thickness variation as random vectors with normal distributions. For 100-times Monte-Carlo simulation based on 65 nm technology, the voltage error and oxide thickness error of the PMOS device are obtained. Applying these process errors to the statistical model, the results show that mean value of threshold voltages is increased along the negative direction with the stress time going on under the process variation and NBTI effect interaction. Meanwhile the standard deviation of threshold voltage is reduced, which represents that the matching between those PMOS devices becomes better. The proposed statistical model accuracy is verified by R-D model theoretical solutions. The maximum relative error of the mean value and of the standard deviations for the threshold voltages degradation of the PMOS device are only 0.058% and 0.91% respectively in 104 s. The distribution characteristic of PMOS NBTI effect is more serious to analog circuit, because analog circuit is more sensitive to device mismatch. For current steering digital-to-analog converter (DAC), PMOS device is always adopted as current source due to its good isolating properties. The PMOS current source requires good matching, and mismatch error could cause circuit failure. To realize aging simulation on DAC circuit in Spectre environment, the above statistical NBTI model is realized by Verilog-ASM language as the subcircuit module to PMOS device. Finally, this module is applied to the current steering DAC. Considering the NBTI effect under process variations, the simulation results show that the DAC gain error is increased with the stress time going on, while its linearity error is gradually reduced.

Double ellipsoid model for conductivity effective mass along [110] orientation in (100) Si-based strained p-channel metal-oxide-semiconductor

The performance of a Si metal-oxide-semiconductor field-effect transistor can be enhanced effectively by the strain technology and the orientation engineering. For example, the [110] direction is usually used as the channel direction in the Si p-channel metal-oxide-semiconductor (PMOS) on 100 oriented substrate. While SunEdison company rotates the channel direction 45 degrees to the [100] direction, its hole mobility is 1.15 times larger than the hole mobility of the former.The orientation engineering is based on the anisotropy of the hole effective mass along different directions. The enhancement of carrier mobility naturally occurs when we choose the direction with the smaller carrier effective mass as the channel direction.However, according to the reported results in the literature, the hole effective mass values along the [110] and [100] orientation are about 0.6m0 and 0.29m0, respectively. The former is twice larger than the latter, which cannot explain that the experimental result increases 1.15 times.We find that the effective mass values along both the long axis and the short axis should be taken into consideration, and the value of 0.6m0 can only represent the long axis term by observing the equivalent energy diagram of the first sub-band in Si PMOS.In view of this, the double ellipsoid model is given for the conductivity effective mass along the [110] direction in (100) Si PMOS, which explains the reason why the hole mobility along the [100] direction is 1.15 times larger than that along the [110] direction in Si PMOS. And then, based on the E-k relation of the inversion layer in Si-based strained PMOS, we study the conductivity effective mass along the [110] direction in (100) Si-based strained PMOS by the above method.The results show that 1) the [110] oriented hole conductivity effective mass of biaxially strained Si PMOS can be calculated directly by its spherical equivalent energy diagram; 2) in the case of biaxially strained Si1-xGex PMOS, its conductivity effective mass needs to be calculated by the double ellipsoid method; 3) the [110] oriented hole conductivity effective mass of uniaxially strained Si PMOS should be solved approximately by two different sizes of ellipsoid.Our valid models can provide the valuable references for studying and designing the Si-based strained PMOS device.

An Efficient High Voltage Level Shifter using Coupling Capacitor for a High Side Buck Converter

We propose an efficient high voltage level shifter for a high side Buck converter driving a light-emitting diode (LED) lamp. The proposed circuit is comprised of a low voltage pulse width modulation (PWM) signal driver, a coupling capacitor, a resistor, and a diode. The proposed method uses a property of a PWM signal. The property is that the signal repeatedly transits between a low and high level at a certain frequency. A low voltage PWM signal is boosted to a high voltage PWM signal through a coupling capacitor using the property of the PWM signal, and the boosted high voltage PWM signal drives a p-channel metal oxide semiconductor (PMOS) transistor on the high side Buck converter. Experimental results show that the proposed level shifter boosts a low voltage (0 to 20 V) PWM signal at 125 kHz to a high voltage (370 to 380 V) PWM signal with a duty ratio of up to 0.9941.