Charge Trapping In Oxide Research Articles

Total dose dependence of hot carrier injection effect in the n-channel metal oxide semiconductor devices

The equipment and devices which are long-time running in space are affected by space radiation effects and hot carrier injection effects at the same time which would reduce their optional times. Normally, the single mechanism test simulation method is used on the ground simulation test but the multi-mechanism effect affects the space equipments and devices, including total irradiation dose effect, hot carrier injection effect, etc. The total dose dependence of hot carrier injection (HCI) effect in the 0.35 m n-channel metal oxide. semiconductor (NMOS) device is studied in this paper. Three samples are tested under different conditions (sample 1# with total irradiation dose (TID) and HCI test, sample 2# with TID, annealing and HCI test, sample 3# only with HCI test). The results show that threshold voltage of NMOS device with 5000 s HCI test after 100 krad (Si) total dose radiation has been negatively shifted then positively during total dose irradiation test and HCI test, and the threshold is higher than that of the device without radiation test. But the threshold voltage shift of NMOS device with 5000 s HCI test and 200 h annealing test after TID test is higher than that of the devices without radiation test and lower than that of the devices without annealing test. That is, the parameters of NMOS device vary faster with the combined effects (including the total dose irradiation effect and HCI effect) than with single mechanism effect. It is indicated that the hot electrons are trapped by the oxide trap charges induced by irradiation effect and then become a recombination centre. And then the oxide trap charges induced by irradiation effect reduce and become negative electronic. The interface trap charges induced by irradiation effect are reduced and then increased it is because the electrons of hole-electron pairs in the Si-SiO2 interface are recombined by oxide traps in the oxide during the forepart of HCI test but then the electrons are trapped by interface traps in the Si-SiO2 interface because the electrons from source area are injected to interface during the HCI test. So the threshold voltage is positively shifted due to the negative oxide trap charges and interface trap charges. The association effect is attributed to the reduction of oxide traps induced by recombination with hot electrons and the increase of the interface traps induced by irradiation trapped hot electrons.

Enhanced channel hot carrier effect of 0.13 m silicon-on-insulator N metal-oxide-semiconductor field-effect transistor induced by total ionizing dose effect

In this paper, a series of hot carriers tests of irradiated 130 nm partially depleted silicon-on-insulator NMOSFETs is carried out in order to explore the HCI influence on the ionizing radiation damage. Some devices are irradiated by up to 3000 Gy before testing the hot carriers, while other devices experience hot carriers test only. All the devices we used in the experiments are fabricated by using a 130 nm partially depleted (PD) SOI technology. The devices each have a 6nm-thick gate oxide, 100 nm-thick silicon film, and 145 nm-thick buried oxide, with using shallow trench isolation (STI) for isolation scheme. The irradiation experiments are carried by 60Co- ray at the Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences, with a dose rate of 0.8~Gy(Si)/s. During irradiation all the samples are biased at 3.3V, i.e., VGS=3.3V and other pins are grounded, and when the devices are irradiated respectively by total doses of 500, 1000, 2000 and 3000Gy(Si), we test the characteristic curves again. Then 168-hour room temperature anneal experiments are carried out for the irradiated devices, using the same biases under irradiation. The HCI stress condition is chosen by searching for the maximum substrate current. The cumulative stress time is 5000s, and the time intervals are 10, 100, 500, 1000 and 5000s respectively. After each stress interval, the device parameters are measured until stress time termination appears. Through the comparison of characteristic between pre-irradiated and unirradiated devices, we find that the total dose damage results in the enhanced effect of hot carriers: the substrate current value which characterizes the hot carrier effect (for SOI device are the body to the ground current) increases with the increase of total dose, as the pre-irradiated and unirradiated device do under the same conditions of hot carrier stress, the degradations of key electrical parameters are more obvious for the pre-irradiated one. In order to analyze the physical mechanism of the experimental phenomena, the wide channel device is tested too, we also analyze the phenomenon of the decrease of the substrate current of the wide channel device. From the contrasts of pre-irradiated and unirradiated devices, and narrow and wide channel device test results, we can obtain the following conclusions: SOI devices (especially the narrow channel device) with additional ionization irradiation field induced by ionizing radiation enhance the rate of injecting electrons into the silicon dioxide, and produce oxide trap charge and interface states, which leads to the fact that the channel carrier scattering becomes stronger, transfer characteristic curve of the device, output characteristic curve, transconductance curves and the related parameters of VT, GMmax, IDSAT degradation degree increase. So, when designing 130nm PD SOI NMOSFETs which are applied to the space environment, one should make a compromise between radiation resistance and HCI reliability.

Synergistic Effect of Ionization and Displacement Defects in NPN Transistors Induced by 40-MeV Si Ion Irradiation With Low Fluence

Based on 3DG110 transistors and special gated NPN (GNPN) transistors, the characteristic of the synergistic effect between ionization and displacement defects induced by 40-MeV silicon (Si) ions with low fluence was investigated in terms of deep-level transient spectroscopy (DLTS). Nonlinear relationship, produced by the synergistic effect, between low fluence and radiation response can be obviously observed in the bipolar junction transistors (BJTs) under the exposure of 40-MeV Si ions. The DLTS signals of displacement defect centers and oxide-trapped charges are detected in the base–collector junction of the 3DG110 transistors. Meanwhile, based on the GNPN transistors, the DLTS signals of interface traps and displacement defects are measured in the base–collector junction. By comparison of the change in electrical parameters and the DLTS signals, it is found that the interface traps induce an enhanced effect to displacement defects in the base–collector junction of NPN BJT, whereas the oxide-trapped charge can suppress the DLTS signals of deep-level centers to a certain extent. Compared with the suppression action, the enhanced effect rising from ionization damage gives more contribution to the displacement damage. Moreover, the bias used during DLTS measurements can influence the characteristics of DLTS signals caused by oxide-trapped charge and interface traps. With increasing bias, both the height and temperature of ionization defect peaks in the DLTS spectra will increase, illustrating that concentration and energy level of these defects are raised.

Drain Current Collapse in 65 nm pMOS Transistors After Exposure to Grad Dose

Total ionizing dose (TID) response of pMOS transistors featuring a commercial 65 nm CMOS technology was studied by X-ray irradiation up to 1 Grad (SiO2), which emulated total dose target in the LHC upgrade. After irradiation, dramatic reduction of drain current was observed, the degradation level showed a strong dependency on gate width. At total doses higher than 208 Mrad(SiO2), the off-state leakage was heightened by more than one order of magnitude, which was attributed to the gate-induced drain leakage (GIDL) due to the positive charge trapping in STI and/or gate oxide. The subthreshold swing (SS) and the threshold voltage remained practical constant even at 1 Grad (SiO2) total dose. The degradation in the drain current can be partially explained by the radiation induced narrow channel effect due to the positive charge trapping in STI. However, from the comparison results under two bias conditions during irradiation, there must be other mechanisms contributing together. Damage of the gate oxide could be another mechanism contributing to the dramatic drain current reduction.

Bias dependence of TID induced single transistor latch for 0.13 μm partially depleted SOI input/output NMOSFETs

In this work, single transistor latch effects induced by total dose irradiation for 0.13μm partially depleted silicon-on-insulator (PDSOI) n-type metal-oxide-semiconductor field effect transistors (NMOSFETs) were investigated. The front gate transfer characteristics under different bias configurations with forward and reverse gate voltage sweep are characterized to evaluate the latch phenomenon. The results indicate that transmission–gate (TG) bias is the worst case bias for total dose induced latch, and the onset drain voltage required for latchup degrades as the irradiation level increased. Experiments and 2D simulations are performed to analyze the positive trapped charge in the buried oxide (BOX) and its impact on the latch effect. It is demonstrated that the irradiation can enhance the impact ionization and thereby make the device more sensitive to latchup, especially at negative gate voltage. Moreover, the radiation induced coupling effect between the front gate and back gate can make the PDSOI devices in our experiments behave like the fully depleted (FD) ones.

Impact of charge trapping on the ferroelectric switching behavior of doped HfO2

In order to analyse the interplay between ferroelectric switching and parasitic charge trapping in ferroelectric doped hafnium oxide, a metal ferroelectric metal capacitor and grain boundary model is implemented in TCAD. In our study, we present how bulk traps inside the ferroelectric material, traps at the interface with the electrodes are impacting the ferroelectric switching behaviour. Switching peak splitting was observed experimentally, and reproduced by TCAD simulation. Furthermore, the influence of DC voltage stress on the switching behaviour is investigated experimentally and compared to the already known AC‐behaviour.DC stress of the FeCAP redistributes the charge within the device influencing the kinetics of the ferroelectric switching and causing the peak split.

Effect of GaN surface treatment on Al2O3/n-GaN MOS capacitors

The surface preparation for depositing Al2O3 for fabricating Au/Ni/Al2O3/n-GaN (0001) metal oxide semiconductor (MOS) capacitors was optimized as a step toward realization of high performance GaN MOSFETs. The GaN surface treatments studied included cleaning with piranha (H2O2:H2SO4 = 1:5), (NH4)2S, and 30% HF etches. By several metrics, the MOS capacitor with the piranha-etched GaN had the best characteristics. It had the lowest capacitance–voltage hysteresis, the smoothest Al2O3 surface as determined by atomic force microscopy (0.2 nm surface roughness), the lowest carbon concentration (∼0.78%) at the Al2O3/n-GaN interface (from x-ray photoelectron spectroscopy), and the lowest oxide-trap charge (QT = 1.6 × 1011 cm−2eV−1). Its interface trap density (Dit = 3.7 × 1012 cm−2eV−1), as measured with photon-assisted capacitance– voltage method, was the lowest from conduction band-edge to midgap.

Activation Energies for Oxide- and Interface-Trap Charge Generation Due to Negative-Bias Temperature Stress of Si-Capped SiGe-pMOSFETs

We investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The measured activation energies for interface-trap charge buildup during negative-bias temperature stress are lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si–H bonds and that Ge–H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2.

Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests

This paper investigates the effects of hot carrier injection on the switching performance of power RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices. In addition, their influences on the dynamic parameters are studied after various accelerated aging tests (thermal and electrical). The response of these parameters and the switching waveform are described. The findings of experimental results are presented and discussed. Measurements show that important variations are obtained on the devices' rise time. After aging tests, the charge trapping in the gate oxide causes the modifications in the Miller capacity level and width resulting in an increase of the rise time and a decrease in the fall time, consequently increasing of the switching losses.

<formula formulatype="inline"><tex Notation="TeX">$1/f$</tex></formula> Noise Model for NPN Bipolar Junction Transistors Based on Radiation Effect

Radiation-induced current gain and $1/f$ noise degradations in NPN bipolar junction transistors are due to accumulation of oxide-trapped charges and interface states at the surface of the device. Based on an available model of base surface current of NPN bipolar junction transistors, a simplified model is presented with some approximations at low total dose level, which can explain the degradation mechanisms of the current gain. Based on the theory of carrier number fluctuation and the simplified model of base surface current, a $1/f$ noise model is developed, which can be used to explain the $1/f$ noise degradation induced by the radiation at low total dose level. The model suggests that the gain and $1/f$ noise degradations can be attributed to the same physical origin, and these two kinds of degradations are the result of accumulation of oxide-trapped charges and interface states. The radiations were performed in a ${\rm Co}^{60}$ source at a dose rate of 10 rad(Si)/s up to a total dose of 70 krad(Si). The degradations of the current gain and $1/f$ noise are compared, and the relationship between $1/f$ noise and the current gain is given, which accords well with the experimental results. Compared to the current gain, the $1/f$ noise parameter is more sensitive, so it may be used to evaluate the radiation resistance capability of bipolar junction transistors.

Experimental and comparative study of gamma radiation effects on Si-IGBT and SiC-JFET

This paper deals with an experimental study and a comparative study of the effects of total ionising dose of 60Co gamma radiation on Si-IGBT and SiC-JFET. The response of the threshold voltage and the turn-on switching parameters are reported for both devices. Charge trapping in the gate oxide causes the decrease of the threshold voltage for Si-IGBT. The decrease of this parameter combined with the behaviour of Miller plateau during irradiation results in a decrease of the collector current rise-time, the collector-emitter voltage fall-time, and the turn-on switching energy and in an increase of the peak of the turn-on switching power and of the turn-on overshoot collector current. No changes in these parameters are observed for SiC-JFETs up to 2900Gy with a dose rate of 2.80Gy/h. This indicates that those SiC-JFETs have extremely high radiation resistance with respect to the TID effects compared to the Si-IGBTs.

Electrical Characterization of 3C-SiC Lateral MOSFETs Fabricated on Heteroepitaxial Films Including High Density of Defects

We have fabricated lateral MOSFETs on heteroepitaxial 3C-SiC films included high density of defects. Electrical characteristics of 3C-SiC MOSFETs and their temperature dependence were measured to discuss effects of defects on the electrical characteristics. A field effect mobility of 156 cm2/Vs was obtained at room temperature. After applying a drain voltage of 10 V or higher, the drain current - gate voltage curve shifted toward the positive gate voltage. This shift was caused mainly by the charge trapping in the gate oxide. The light emission was observed on the surface of the active MOSFET. The spatial distribution of the emission light from MOSFETs indicated that the charge was generated at the source edge of the gate channel.

Separation of Interface Traps and Oxide Charge in Ionization Damaged Silicon Bipolar Transistors Based on Experimental Observation

An experimental concept of separating oxide-trapped charge and interface traps in silicon bipolar junction transistors (BJTs) irradiated by Co60 gamma ray is demonstrated. This concept is based on deep-level transient spectroscopy (DLTS) measurements with various filling pulsewidths. The characteristics of oxide-trapped charge and interface traps in bipolar transistors can be obtained by DLTS. The oxide-trapped charge shows positive and negative signals in the collector of NPN and PNP BJTs in DLTS signals, respectively. Unlike the oxide-trapped charge, the interface traps give positive signals in the same region of NPN and PNP BJTs.

Model of radiation-induced gain degradation of NPN bipolar junction transistor at different dose rates**Project supported by the National Natural Science Foundation of China (Nos. 61076101, 61204092).

Ionizing-radiation-induced current gain degradation in NPN bipolar junction transistors is due to an increase in base current as a result of recombination at the surface of the device. A model is presented which identifies the physical mechanism responsible for current gain degradation. The increase in surface recombination velocity due to interface states results in an increase in base current. Besides, changing the surface potential along the base surface induced by the oxide-trapped charges can also lead to an increased base current. By combining the production mechanisms of oxide-trapped charges and interface states, this model can explain the fact that the current gain degradation is more severe at a low dose rate than at a high dose rate. The radiations were performed in a Co60 source up to a total dose of 70 krad(Si). The low dose rate was 0.1 rad(Si)/s and the high dose rate was 10 rad(Si)/s. The model accords well with the experimental results.

Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application

Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson's equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 $\mu \hbox{m}$ . After presenting the fundamental $C$ – $V$ characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window ( $\vert{V}_{\rm ow}\vert=\hbox{20} \hbox{V} $ ) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge $Q_{\rm ot} $ engineering in TSV oxide liner, neither considerations of the ${V}_{\rm FB} $ shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously.

Electrical characteristics of ALD La2O3 capping layers using different lanthanum precursors in MOS devices with ALD HfO2, HfSiOx, and HfSiON gate dielectrics

We have investigated the electrical characteristics – flat band voltage (VFB) shift, equivalent oxide thickness (EOT) scaling and charge trapping – of atomic layer deposition (ALD) La2O3 capped high-k gate dielectrics (HfO2, HfSiOx, and HfSiON) in the metal-oxide-semiconductor (MOS) device structure, where two different lanthanum precursors – ① lanthanum formamidinate, La(fAMD)3, and ② lanthanum betadiketonate, La(thd)3, – were used for ALD capping layer. Regardless of precursors, La2O3 capping layer on the ALD high-k films leads to negative VFB shift and thinner EOT as increasing capping thickness. However, more shift and further EOT scaling are observed with La2O3 thin film using La(fAMD)3. In addition, La2O3 capping layer using La(fAMD)3 precursor shows lower interface state density (Dit) and stronger immunity against charge trapping than La2O3 capping layer with La(thd)3 precursor. Similar trends are attained with Si containing HfO2 – HfSiOx and HfSiON, but amount of VFB shift and EOT reduction is smaller than that of HfO2-based device, resulting from suppressed La-diffusion due to stronger Si–O bonds as well as nitrogen blocking in the dielectrics.

Research on the Combined Effects of Ionization and Displacement Defects in NPN Transistors Based on Deep Level Transient Spectroscopy

The properties of the combined effect between ionization and displacement defects have been researched on the base-collector junctions of 3DG110 silicon NPN bipolar junction transistors (BJTs) irradiated by 6 MeV carbon (C) ions with different fluence. The Gummel curve is used to characterize the degradation of the current gain at a given fluence. Nonlinear relationship, induced by 6 MeV C ions with lower fluence, between irradiation fluence and BJT radiation response can be observed, which is attributed to the combined effect. Evolution of deep level centers is characterized by the deep level transient spectroscopy (DLTS) with various biases. An unusual discovery is that the deep level centers decrease in the amplitude of DLTS peaks with increasing the biases. Based on the results of DLTS measurement, interface traps caused by 6 MeV C ions produce apparent enhanced effect to displacement defects in the base-collector junction of NPN BJT. Meanwhile, two factors, including bias used in DLTS measurement and irradiation fluence, can influence characteristics of DLTS signals caused by oxide-trapped charge. With increasing the bias or the irradiation fluence, both the height and the temperature of the defect peaks induced by the oxide charge in DLTS spectra will increase, illustrating concentration and energy level of the defects are enhanced.

Flexible low-voltage organic phototransistors based on air-stable dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT)

Photosensitive elements based on organic thin-film transistors readily integrated into flexible, large-area organic circuits open up new scopes in light-sensing applications. In this work, high-performance, low-voltage organic thin-film transistors based on dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) are thoroughly characterized with respect to their optical functionality. The fundamental light-dependent effect, i.e., a large but slow threshold-voltage shift based on charge trapping in the aluminum oxide of the gate dielectric or at the semiconductor–dielectric interface, is analyzed depending on various parameters, such as biasing conditions, integration time, wavelength and power of the incoming light as well as the channel length. An optimized 3-phase operation consisting of reset, integration and read-out is proposed in order to maximize reproducibility, sensitivity and responsivity of the phototransistors. Two distinct regimes, an absorption-limited and a trapping-limited regime, are identified depending on the density of available trappable electrons, which is determined by the optical input power and the integration time. The maximum operation frequency is found to be larger in phototransistors with shorter channel lengths. Based on these results, an organic gesture recognition system with a refresh rate of 1Hz was designed, implemented and successfully tested.

Influence of the Total Ionizing Dose Irradiation on 130 nm Floating-body PDSOI NMOSFETs

This paper investigates the impact of ionizing radiation on floating body effects for the 130 nm PDSOI NMOSFETs. It is shown that the floating body effects are restrained by the irradiation both for the core device and the input/output (I/O) device. For the core device, the second peak of the front gate transconductance which is known as the gate-induced floating body effect degrades with the incremental total dose. The decline of the second g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> peak is ascribed to the impact of the radiation-induced leakage current, but not to the radiation-induced interface traps assisted recombination or the suppression of the electron valence band (EVB) tunneling. For the I/O device, the kink effect and the hysteresis effect in the output characteristic which are observed before irradiation become insignificant after irradiation. These phenomena are due to the fully depleted of the silicon film in the I/O device which is caused by the buried oxide charge trapping. In addition, a radiation-induced latch, which is result from the leakage current-induced impact ionization, is also observed in the I/O device.

Quantitative separation of radiation induced charges for NPN bipolar junction transistors based on 1/f noise model

Ionizing-radiation-induced oxide-trapped charges and interface states cause the current and 1/f noise degradation in bipolar junction transistors. In order to better understand these two degradation mechanisms and develop hardening approaches for a specific process technology, it is necessary to measure the effect of each mechanism separately. In recent years, several techniques have been developed, but no charge-separation approach based on 1/f noise for NPN bipolar junction transistors is available. In this paper, the effects of ionizing-radiation-induced oxide trapped charges and interface states on base current and 1/f noise in NPN bipolar junction transistors are studied in detail. Firstly, a new model of base surface current of NPN bipolar junction transistors is presented with some approximations, based on an available model for the base surface current under certain conditions; this model can identify the physical mechanism responsible for the current degradation. Secondly, combining the theory of carrier number fluctuation and the new model of base surface current another model is developed which can well explain the 1/f noise degradation. This model suggests that the induced oxide-trapped charges would make more carriers, involving the dynamic trapping-detrapping, which leads to the 1/f noise to increase; and the induced oxide-trapped charges and interface states can also bring about an increase in base surface current which can also cause the l/f noise increase. These two models suggest that the current and1/f noise degradations can be attributed to the same physical origin, and these two kinds of degradations are the result of accumulation of oxide-trapped charges and interface states. According to these two models, simple approaches for quantifying the effects of oxide-trapped charges and interface states are proposed. The base surface current can be extracted from the base current using the available method. The oxide-trapped charge density is estimated using the amplitude of 1/f noise (10-100 Hz) and the base surface current. Given the estimated oxide-trapped charge density, the interface state density can be estimated using the base surface current. These methods are simple to implement and can provide insight into the mechanisms and magnitudes of the radiation-induced damage in NPN bipolar junction transistors.