Charge Trapping In Oxide Research Articles

The effect of ZrN antidiffusion capping layer on the electrical and physical properties of metal-gate/ZrN/Zr-graded Dy2O3/Si MIS nanolaminated structures

We report the physical analysis of MG/ZrN/Zr-graded Dy2O3/Si MIS structures.The key process parameters such as postannealing temperature and doping location are examined.Electrical properties such as flatband voltage shift, leakage current, EOT are shown and calculated. Nano-film Dy2O3:Zr and Dy2O3 gate oxide stacks with and without ZrN capping layer were fabricated. The electrical and physical properties were compared in the PMA temperature range of 550-850?C. The flatband voltage shift decreases with increasing the annealing temperature, which indicates the reduction in oxide trap charges especially for the MIS structures with ZrN capping. The dielectric constant is enhanced due to lesser outdiffusion of Ti, O, and Dy atoms from ZrN layer. The atomic percentage was studied by the depth profile of X-ray photoelectron spectra.

Off-state avalanche-breakdown-induced on-resistance degradation in SGO–NLDMOS

In this paper, on-resistance (Ron) degradation induced by off-state avalanche breakdown in a 40V LDMOS with step-shaped gate oxide (SGO–LDMOS) is investigated. Ron unexpectedly decreases at the beginning of stress, which is different from the phenomenon described in works on LDMOS with uniform gate oxide (UGO–LDMOS). Based on the experiment data and TCAD simulation results, two degradation mechanisms are proposed. That is the generation of positive oxide-trapped charges at the bird’s beak region near source and formation of interface state at the bird’s beak region near source and drain respectively.

Power lateral pnp transistor operating with high current density in irradiated voltage regulator

The operation of power lateral pnp transistors in gamma radiation field was examined by detection of the minimum dropout voltage on heavily loaded low-dropout voltage regulators LM2940CT5, clearly demonstrating their low radiation hardness, with unacceptably low values of output voltage and collector-emitter voltage volatility. In conjunction with previous results on base current and forward emitter current gain of serial transistors, it was possible to determine the positive influence of high load current on a slight improvement of voltage regulator LM2940CT5 radiation hardness. The high-current flow through the wide emitter aluminum contact of the serial transistor above the isolation oxide caused intensive annealing of the positive oxide-trapped charge, leading to decrease of the lateral pnp transistor's current gain, but also a more intensive recovery of the small-signal npn transistors in the control circuit. The high current density in the base area of the lateral pnp transistor immediately below the isolation oxide decreased the concentration of negative interface traps. Consequently, the positive influence of the reduced concentration of the oxide-trapped charge on the negative feedback reaction circuit, together with the favourable effect of reduced interface traps concentration, exceeded negative influence of the annealed oxide-trapped charge on the serial pnp transistor's forward emitter current gain.

Total ionizing dose effect on 0.18 μm narrow-channel NMOS transistors

This paper describes the total ionizing dose effect on 0.18 μm narrow-channel NMOS transistors which are exposed to a γ-ray radiation. Electrical parameters such as threshold voltage, leakage current, trans-conductance, drain-source conductance, and subthreshold slope extracted from the I-V curves are analyzed pre-and post-irradiation. Results show that the threshold voltage, the trans-conductance, and the drain-source conductance are sensitive to radiation compared to wide-channel NMOS transistors–the effect we call radiation induced narrow channel effect(RINCE). The amount of oxide-trapped charges and interface states which would degrade the threshold voltage and leakage current is induced in the STI oxide. The gate oxide is insensitive to irradiation. Combining the structure and process of devices, we finally discuss and analyze the above phenomenon in detail.

Analysis of Commercial Punch-Through IGBTs Behavior Under $^{60}$Co Irradiation: Turn-Off Switching Performances Evolution

This paper deals with the effects of <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> Co gamma irradiation on punch-through commercial insulated gate bipolar transistors turn-off switching behavior. The response of the threshold voltage, the gate-emitter leakage current, the collector leakage current, the collector-emitter breakdown voltage and the turn-off switching parameters under three different in situ gate biases are described. Charge trapping in the gate oxide causes the decrease of the threshold voltage. It is shown that the decrease of this parameter and the modifications in the Miller plateau level and width result in an increase of the turn-off delay time, the collector current fall-time, the collector-emitter voltage rise-time, and consequently an increase of the turn-off switching losses and a decrease of the turn-off overshoot collector-emitter voltage.

Comprehensive study on the TID effects of 0.13 μm partially depleted SOI NMOSFETs

Total ionizing dose (TID) effects of 0.13μm partially depleted (PD) SOI NMOSFETs are overviewed in this paper. For core devices with floating body, the 2nd peak of the front-gate transconductance (gm) degrades with incremental TID. Moreover, the 1st and 2nd peak of the drain current (Ids) hysteresis also declines due to the increased recombination current at the back-gate interface after irradiation. The front-gate subthreshold hump effect is more obvious under the OFF (off-state) and TG (transmission gate) bias conditions. By contrast, the back-gate subthreshold hump exhibits a maximum negative shift under the ON (on-state) bias condition and causes the most significant hump effect owing to the largest charge accumulation at the bottom of the shallow trench isolation (STI) oxide. The maximum negative shift of the back-gate threshold voltage is observed under the TG bias condition, leading to the coupling effect. Finally, for narrow-channel devices, it is found that the radiation-induced positive trapped charge in the STI oxide will degrade the electron mobility in the front-gate channel region, leading to a gm decrease because of the increased surface roughness scattering.

Proton Irradiation-Induced Electrostatic Modulation in ZnO Nanowire Field-Effect Transistors With Bilayer Gate Dielectric

We report an efficient method to predictably control the conductance and operation voltage of ZnO nanowire field-effect transistors (FETs) with bilayer polyimide (PI)-SiO2 gate dielectric by selectively generating oxide-trapped charges via proton beam irradiation. The bilayer gate dielectrics was made by polyimide and thermally grown SiO2 , which prevents negatively charged interface states between the gate dielectric and the ZnO nanowire after proton irradiation. The proton beam-induced charges trapped in the SiO2 dielectric layer can effectively enhance the electric field toward the n-channel ZnO nanowire, which allows for more accumulation of electrons in the conduction channel of the ZnO nanowire. As a result, the conductance increased and the threshold voltages shifted toward the negative gate bias direction after irradiation. Furthermore, selective modulation of the electrostatic characteristics of the ZnO nanowire FETs was possible by varying the proton irradiation time, which is important for practical application of these devices.

Suppression of Gate Oxide Degradation for MOS Devices Using Deuterium Ion Implantation Method

This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of <TEX>$1{\times}10^{12}-1{\times}10^{14}/cm^2$</TEX> at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

Two-Way Tunneling Model of Oxide Trap Charging and Discharging in SiC MOSFETs

A two-way tunneling model describing simultaneous oxide trap charging and discharging in SiC MOSFETs is presented, along with a comparison with experimental results. This model can successfully account for the variation in threshold-voltage instability observed as a function of bias-stress time, bias-stress magnitude, and measurement time.

Are Interface State Generation and Positive Oxide Charge Trapping Under Negative-Bias Temperature Stressing Correlated or Coupled?

Studies have suggested that interface state generation under negative-bias temperature (NBT) stress results in positive oxide charge trapping. The latter is ascribed to the trapping of hydrogen species, from Si-H bond dissociation, in the oxide bulk. In this paper, we present evidence from dynamic NBT instability showing no apparent relationship between the two degradation mechanisms. The level of positive oxide trapped charge is shown to remain constant despite a nonnegligible increase of threshold voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> shift due to interface state generation. This observation implies that Si-H bond dissociation did not result in any significant positive oxide trapped charge, and that the latter is due to a different mechanism (e.g., hole trapping at oxygen vacancies). The inference is supported by results from channel hot-hole stress, which is known to dissociate Si-H bonds but did not increase the level of positive oxide trapped charge. Possible reasons for the difference between previous and current studies are discussed. We also examine the observation on the “universal scalability” of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> drift curves from different stress conditions, as explained by <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">'</sup> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> coupling, i.e., Si-H bond dissociation is driven by hole trapping at nearby oxygen vacancies. We revisit an earlier observation that shows that such scalability only holds in the initial stage when positive oxide charge trapping is dominant, and that the scaled <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> drift curves eventually diverge in the later stage. Further evidence shows that the divergence is caused by interface state generation proceeding at a faster rate compared to positive oxide charge trapping. The result confirms that a part of interface degradation proceeds independently of positive oxide charge trapping.

Effects of heavy-ion irradiation on the electrical properties of rf-sputtered HfO2 thin films for advanced CMOS devices

HfO2-based metal-oxide semiconductor (MOS) capacitors were irradiated with high-energy ion beam to study the irradiation effects in these films. HfO2 thin films deposited by radio frequency (rf)-sputtering were irradiated with 80 MeV O6+ ions. The samples were irradiated and characterized at room temperature. Devices were characterized via 1 MHz capacitance–voltage (C‒V) measurements using the midgap method. The irradiation induced dispersion in accumulation and depletion regions with increasing fluence is observed. After irradiation, the midgap voltage shift (Δ V mg) of−0.61 to−1.92 V, flat band voltage shift (Δ V fb) of−0.48 to−2.88 V and threshold voltage shift (Δ V th) of−0.966 to−1.96 V were observed. The change in interface trap charge and oxide trap charge densities after 80 MeV O6+ ions irradiation with fluences were determined from the midgap to flat band stretch out of C‒V curves. The results are reported and explained in terms of changes in microstructure and dielectric properties of the HfO2 thin films after irradiation.

A radiation degradation model of metal-oxide-semiconductor field effect transistor

Based on the production kinetics of oxide-trapped charge and interface-trapped charge and the microscopic mechanism of radiation damage, a model of post-irradiation threshold voltage drift due to oxide trap and interface trap as a function of radiation dose is proposed. This model predicts that the post-irradiation threshold voltage drift due to oxide trap and interface trap would be linear in dose at low dose levels. At high dose levels, the post-irradiation threshold voltage drift due to oxide trap tend to be saturated, its peak value has no correlation with radiation dose, and the post-irradiation threshold voltage drift due to interface trap has an exponential relationship with radiation dose. In addition, the model indicates that the oxide-trapped charge and the interface-trapped charge start a saturation phenomenon at different radiation doses, and the saturation phenomenon of oxide-trapped charge appears earlier than interface-trapped charge. Finally, the experimental results accord well with the model. This model provides a more accurate prediction for radiation damage in metal-oxide-semiconductor field effect transistor.

Total dose irradiation and hot-carrier effects of sub-micro NMOSFETs

Total dose irradiation and the hot-carrier effects of sub-micro NMOSFETs are studied. The results show that the manifestations of damage caused by these two effects are quite different, though the principles of damage formation are somewhat similar. For the total dose irradiation effect, the most notable damage lies in the great increase of the off-state leakage current. As to the hot-carrier effect, most changes come from the decrease of the output characteristics curves as well as the decrease of trans-conductance. It is considered that the oxide-trapped and interface-trapped charges related to STI increase the current during irradiation, while the negative charges generated in the gate oxide, as well as the interface-trapped charges at the gate interface, cause the degradation of the hot-carrier effect. Different aspects should be considered when the device is generally hardened against these two effects.

Enhanced Radiation-Induced Narrow Channel Effects in Commercial &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\hbox {0.18}}~\mu$&lt;/tex&gt; &lt;/formula&gt;m Bulk Technology

Total ionizing dose effects are investigated in input/output transistors that are fabricated by using a commercial 0.18 μm bulk process. An enhanced radiation-induced narrow channel effect is demonstrated in N-type metal-oxide semiconductor (NMOS) and P-type metal-oxide semiconductor (PMOS) transistors, leading to a significant threshold voltage shift which may compromise circuit operations. Calculations using a code dedicated to radiation-induced charge trapping in oxides show that the radiation-induced positive charge trapping in trench oxides leads to the modifications of the electrical characteristics experimentally evidenced. Radiation hardening issues are finally discussed as a function of the device geometry and design.

Edge Effects in Self-Heating-Related Instabilities in p-Channel Polycrystalline-Silicon Thin-Film Transistors

Self-heating-related instabilities have been investigated in p-channel polycrystalline-silicon thin-fllm transistor, showing an anomalous transconductance (gm) increase. The gm increase is a fingerprint of edge effects, resulting from a buildup of positive trapped charge in the gate oxide at the channel edges. This was confirmed by the annihilation of such positive charges obtained by sequential hot-carrier bias-stress experiments. From the analysis of the edge effects in devices with different channel lengths, we were able, using 2-D numerical simulations, to deter mine the size of the defected edge regions to be 400 nm.

Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities

Charge trapping at oxide defects fundamentally affects the reliability of MOS transistors. In particular, charge trapping has long been made responsible for random telegraph and 1/ f noise. Recently, it has been identified as a significant contributor to bias temperature instabilities. Conventional defect models assume that the defect has two states, one of them neutral and the other charged. The transition rates between the two states are calculated using some extended Shockley–Read–Hall theory, which neglects the configurational changes occurring at the defect site following a charge trapping or emission event. In order to capture these changes, multiphonon models have been in use for many decades but have not found their way into the mainstream of reliability modeling yet. Furthermore, recent experimental results demonstrate that defects have more states than the two assumed in the conventional model. These additional states together with multiphonon charge transfer mechanisms are essential for the understanding of the complex defect dynamics. The present review summarizes the basic principles of how to model stochastic defect transitions with a particular focus on multi-state defects. After discussing the limitations of Shockley–Read–Hall theory, the relatively simple semiclassical approximation of multiphonon theory is introduced which already provides a much better description. Finally, the transition rates for multi-state defects are estimated using multiphonon theory, which gives a very accurate description of the latest experimental data.

Charge trapping characteristics of Au nanocrystals embedded in remote plasma atomic layer-deposited Al2O3 film as the tunnel and blocking oxides for nonvolatile memory applications

Remote plasma atomic layer deposited (RPALD) Al2O3 films were investigated to apply as tunnel and blocking layers in the metal-oxide-semiconductor capacitor memory utilizing Au nanocrystals (NCs) for nonvolatile memory applications. The interface stability of an Al2O3 film deposited by RPALD was studied to observe the effects of remote plasma on the interface. The interface formed during RPALD process has high oxidation states such as Si+3 and Si+4, indicating that RPALD process can grow more stable interface which has a small amount of fixed oxide trap charge. The significant memory characteristics were also observed in this memory device through the electrical measurement. The memory device exhibited a relatively large memory window of 5.6 V under a 10/−10 V program/erase voltage and also showed the relatively fast programming/erasing speed and a competitive retention characteristic after 104 s. These results indicate that Al2O3 films deposited via RPALD can be applied as the tunnel and blocking oxides for next-generation flash memory devices.

Tunneling discharge of positive trapped oxide charge in p-channel field effect transistors

Negative bias temperature instability has been studied in 130 nm and 90 nm channel length, SiO2 gate insulator field effect transistors at room temperature. Pulsed voltage stressing and subsequent recovery using times starting in the tens of microsecond regime were employed together with a single point data acquisition time ∼4 μs. Threshold voltage shifts were characteristic of oxide charge trapping as opposed to interface state generation. Recovery of the threshold voltage was modeled assuming quantum mechanical tunneling of trapped charges from the dielectric to the Si substrate.

Effect of sputtering time on physical and electrical properties of ZrOx thin film on Si

PurposeThe purpose of this paper is to report the effect of sputtering time on the electrical and physical properties of ZrOx. ZrOx (measured thickness is ranging from 20.5 to 51.3 nm) thin films as gate oxide materials are formed by metal deposition at different sputtering time and thermal oxidation techniques.Design/methodology/approachZirconium is deposited on silicon substrate at three different sputtering time; 30‐, 60‐ and 120‐s continued with an oxidation process conducted at 500°C for 15 min to form ZrOx thin films. High‐resolution X‐ray diffraction (HR‐XRD), Fourier transform infrared (FTIR) spectroscopy and electrical characterizations were used to examine the properties of the thin film.FindingsA broad ZrOx peak lies in between 26° and 31° from HR‐XRD is presumed as the effect of small thickness of ZrOx and or the ZrOx is still partially crystalline. FTIR spectroscopy results suggested that besides ZrOx, SiOx interfacial layer (IL) has also formed in all of the investigated samples. As the sputtering time increases, hysteresis between the forward and reverse bias of capacitance‐voltage curve has reduced. The lowest leakage current density and the highest oxide breakdown voltage have been demonstrated by 60‐s sputtered sample. These may be attributed to a lower effective oxide charge and interface trap density. The extracted dielectric constant (κ) of these oxides is ranging from 9.4 to 18, in which the κ value increases with the increase in sputtering time.Originality/valueZrOx thin film which was fabricated by sputtering method at different sputtering time and thermal oxidation techniques showed distinctive electrical results. SiOx IL formed in the samples.

Total ionising dose effects on punch-through insulated gate bipolar transistors turn-on switching behaviour

This paper deals with the effects of 60Co gamma irradiation on punch-through commercial insulated gate bipolar transistor turn-on switching behaviour. The response of the threshold voltage and the turn-on switching parameters under three different in situ gate biases are described. Charge trapping in the gate oxide causes the decrease of the threshold voltage. It is shown that the decrease of this parameter and the decrease of the Miller plateau level result in a decrease of the collector current rise-time, the collector–emitter voltage fall-time, the turn-on switching energy and in an increase of the peak of the turn-on switching instantaneous power and of the turn-on overshoot collector current.