Encroachment Of Oxide Research Articles

Suppression of Oxide Encroachment into Floating Gate by Shallow Trench Isolation Recess in an Electrically Erasable Programmable Read Only Memory Cell

In this paper, we investigate the effects of the oxide recess in shallow trench isolation (STI) on the characteristics of electrically erasable programmable read only memory (EEPROM) cell with in situ-doped floating gate. It is found that the distribution of the program threshold voltage is improved with increasing of the oxide recess in STI. Transmission electron microscopy analysis shows that the oxide recess in STI results in the decrease of oxide thickness at the edge of STI and in the center of tunnel oxide. Also, it is observed that erase cell current is increased about 11% with oxide recess of and 21% with oxide recess of , respectively. Endurance measurements in the EERPROM cell reveal that both electron and charge generation increase with increasing recess depth when the cycling time exceeds about .

Improved Gate-Edge Profile of Metal/High-k Gate Stack Using an NH[sub 3] Ashing Process in Gate-First CMOSFETs

This study analyzed an alternative ashing technology for removing photoresist in the production of gate-first complementary metal oxide semiconductor field effect transistors (CMOSFETs) with a high-k metal gate stack. NH 3 ashing is proposed as an alternative to O 2 ashing to improve the gate-edge profile. It was found that NH 3 ashing suppresses bottom oxide growth below the thin HfO 2 layer, reducing Si recesses in the source/drain active area, and eliminating bottom oxide encroachment into the gate edge. The NH 3 ashing process also makes the HfO 2 film more resistant to the wet chemistry, which reduces the high-k undercut beneath the metal gate during the high-k removal process.

A Novel Shallow Trench Isolation Technique

Shallow-trench isolation processes which involve refilling using deposition of oxide and polysilicon were investigated. Our results show that the oxide-filled shallow-trench isolation technology based on chemical-mechanical polishing (CMP) is difficult to control and results in poor uniformity. Use of this technology also involves in the dishing effect in wide field regions. However, shallow-trench isolation technology using a masking nitride layer, polysilicon refill, the CMP process with high etch selectivity, and local oxidation of polysilicon is easily implemented and absolutely field oxide encroachment (bird's beak) free. Although the CMP process results in the dishing effect in wide field regions, the local oxidation of polysilicon can reduce the amount of dishing. The polysilicon-filled shallow-trench isolation process can also achieve excellent uniformity across 6-inch diameter silicon wafers due to the high etching selectivity of polysilicon to chemical-vapor-deposited (CVD) oxide and SiN. Moreover, the n+/p junction leakage current of polysilicon-filled shallow trenches is comparable to that of oxide-filled shallow trenches. This simple and easily controllable process is a very promising candidate for shallow trench isolation.

New approach to manufacturing field emitter arrays with sub-half-micron gate apertures

As an attempt to develop a field emitter array with sub-half-micron gate openings for low voltage operation, a new fabrication method has been proposed and demonstrated. The key element of the new process is forming the gate insulator by local oxidation of silicon (LOCOS), resulting in the reduction of the gate hole size due to the lateral encroachment of oxide, ultimately compared with the nitride disc size formed by a conventional contact printer. Feasibility of scaling down the gate hole size of a field emitter to sub-half-micron has been proved successfully, and the field emitter with a 450 nm diam gate opening has been fabricated and characterized. For a 2500-tip array with 450 nm diam gate openings, the anode current of 115 μA(∼50 nA/tip) was measured at the gate voltage of 41 V, while the gate current was less than 0.3% of the anode current. Considering the cathode current level required for flat panel display applications and the measured emission characteristics, the fabricated emitter array is expected to operate at a column drive voltage of about 16 V peak-to-peak.

A new fabrication process of field emitter arrays with submicron gate apertures using local oxidation of silicon

The field emitter arrays with submicron gate apertures for low voltage operation have been successfully fabricated by modifying the conventional Spindt process. The key element of the new process is forming the gate insulator by local oxidation of silicon, resulting in the reduction of the gate hole size due to the lateral encroachment of oxide. The gate hole diameter of 0.55 μm has been obtained from the original mask pattern size of 1.55 μm. An anode current of 0.1 μA per emitter is measured at the gate voltage of about 53 V, while the gate current is less than 0.3% of the anode current. To obtain the same current level from a Spindt-type emitter with the same gate hole diameter as the mask pattern size, a gate bias of about 82 V is needed.

Characterization of polysilicon-encapsulated local oxidation

Device isolation has been most commonly achieved through the use of local oxidation of silicon (LOCOS) or LOCOS derivatives. LOCOS is a highly dependable, low-defect isolation technique, which explains its continued extensive use. Unfortunately, the inherently large oxide encroachment associated with LOCOS is not compatible with 0.8- mu m design rules. Many alternative isolation techniques designed to reduce oxide encroachment have been proposed. These alternatives often result in an increase in defectivity and/or process complexity. Polysilicon-encapsulated local oxidation (PELOX) utilizes a polysilicon-filled cavity self-aligned to the nitride edge to achieve oxide encroachment reduction. The physical (scanning electron and transmission electron micrographs) and electrical (electrical channel width, diode leakage, and gate oxide integrity) characterization of PELOX isolation are reported. >

Recessed polysilicon encapsulated local oxidation

Local oxidation of silicon (LOCOS) is the most commonly used isolation technology in silicon integrated circuits. The inherently large field oxide encroachment associated with LOCOS severely limits scalability. Recessed polysilicon encapsulated local oxidation (recessed PELOX) is demonstrated to achieve both low encroachment and increased field oxide recess. These benefits are obtained without sacrificing process simplicity or defectivity as evidenced by excellent gate oxide and diode quality. >

A high-performance half-micrometer generation CMOS technology for fast SRAMs

An advanced, high-performance, half-micrometer generation technology has been developed for fast CMOS SRAM circuits. This process features an aggressive interwell isolation module which allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m and an advanced framed-mask poly-buffered LOCOS isolation (FMPBL) which reduces field oxide encroachment and the transistor narrow-width effect and provides a 1.2- mu m active pitch. Transistors are fabricated with a 125-A gate oxide and a dual n/sup +//p/sup +/ source/drain implanted polysilicon gates to provide excellent short-channel behavior down to 0.3- mu m effective channel length. Transistor design is optimized to reduce the polysilicon gate bird's beak and lightly doped drain (LDD) underdiffusion. For PMOS transistors, boron diffusion through the gate oxide is minimized by replacing BF/sub 2/ with B/sup 11/ for the p/sup +/ S/D implant. A titanium salicide process provides strapping between n/sup +//p/sup +/ polysilicon gates and lower sheet and contact resistances. The back-end features three levels of metallization and polysilicon contact plugs. Discrete transistor lifetimes for DC hot-carrier degradation are in excess of 10 years at 3.3-V operation. A 16 K* 4 SRAM displayed no parametric shifts after hot-carrier stressing for 1000 h at 7-V and 0 degrees C. This is consistent with a lifetime of greater than 10 years at 3.3-V operation. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Characterization of Poly‐Buffered LOCOS in Manufacturing Environment

Poly‐buffered LOCOS (1–4) is an advanced, electrical isolation scheme developed as an alternative to conventional LOCOS (5–7) to minimize field oxide encroachment into active regions while maintaining satisfactory field thresholds with designs employing 1.0 μm active regions and 1.2 μm isolation spacings. Poly‐buffered LOCOS, or PBL, facilitates design rule shrinking and smaller cell size required for future technologies such as EPIC‐2 (1). This isolation scheme utilizes an oxide/poly/nitride sandwich to block field oxidation in active regions instead of the oxide/nitride sandwich used in standard LOCOS isolation. The presence of the intermediate poly layer allows the oxide to be thinned and nitride thickened without generating undue stress in active regions in order to reduce encroachment during field oxidation. Lateral encroachment is reduced to approximately 0.1 μm/side for PBL, compared to 0.5 μm/side for standard LOCOS. The effectiveness of this polysilicon cushion layer was proven by defect etching as well as by electrical measurements of gate oxide integrity (GOI) breakdown voltage and other critical device parameters such as diode leakage, transistor Vt and subthreshold slope, and parasitic field oxide threshold. Process details and electrical characterizations obtained during the implementation of poly‐buffered LOCOS are reported. Considerable process latitude exists in buffer layer thickness and dry or wet removal techniques, demonstrating the production tolerance of PBL.

A new self-aligned VLSI Isolation process using thin-metal lift-off

A new Self-Aligned Isolation process using thin-metal Lift-off (SAIL) has been developed for NMOS VLSI circuits. In this process, a field oxide is grown first, followed by a channel-stop implant that is self-aligned to the active area. The self-alignment is achieved through a lift-off process that utilizes only thin metal. The self-alignment of channel-stop implant to active area is shown to improve the breakdown voltage of MOSFET devices. Direct window isolation is used to eliminate oxide encroachment and reduce outdiffusion of boron channel-stop implant into the active area. As a result, the narrow width effect is minimal. Since thin-metal lift-off can be performed reproducibly with high yield, this makes SAIL a viable process for VLSI fabrication.