Oxide Capacitance Research Articles

Optimization of thermal oxidation for 4H-SiC and fabricate/characterize MOS capacitor

On the 4H-SiC substrate, C-face and Si-face oxide layers have been grown by thermal oxidation process and sputtering. The thermal oxidation temperature dependence of 4H-silicon carbide (SiC) is systematically investigated using capacitance-voltage (C–V) measurements. The oxidation quality and thickness vary according to the temperature and time duration of the thermal oxidation. The layers’ thicknesses are determined by atomic force microscopy (AFM), and the temperature range is between 800°C and 1110 °C. The primary reason to fabricate the Metal-Oxide-Silicon (MOS) capacitor is to know the thermal oxidation process and a working principle. In this paper, we optimize a thermal oxidation process and fabricate the MOS structure. Then we determine the various parameters such as flat band voltage (Vf b), Inversion threshold voltage (Vt), Surface depletion capacitance (Cdep), Oxide capacitance (Cox), the total capacitance of the device (Co), doping concentration (Nd), Depletion width (Xd), Maximum depletion width (Xdt) and Interface trap density (Dit). Finally, we analyze and discuss the MOS capacitance.

Effect of Schottky barrier height lowering on resistance degradation of Fe-doped SrTiO3 thin-film capacitor

It is generally believed that the resistance degradation behavior of bulk and thin-film oxide capacitors arises from the oxygen vacancy migration within the oxide and/or the charge injection at the oxide/electrode interface. The magnitude of the degradation in the resistance has been theoretically studied in the literature by solving the electrochemical transport equations while assuming constant Schottky barrier height. The treatment of constant Schottky barrier height in existing models has led to significant underestimation of the resistance degradation. In this work, I incorporated the dependence of Schottky barrier height on the oxygen vacancy concentration at the interface into the existing model to simulate the degradation process in thin-film oxide capacitors. With the consideration of Schottky barrier height lowering from the interface dipole arising from the accumulation of oxygen vacancies at the cathode interface, I found that the leakage current can be increased by more than one order of magnitude, which is more consistent with experimental observations in comparison to the prediction from existing models.

Determination of Power MOSFET’s Gate Oxide Degradation Under Different Electrical Stress Levels Based on Stress-Induced Oxide Capacitance Changes

In this article, we aim to investigate the gate oxide degradation of power MOSFETs through oxide capacitance. We focus on modeling the oxide capacitance variation as a function of several stress levels and time intervals. The experimental procedure is carried out by means of commercial n-channel vertical double-diffused metal-oxide semiconductor field-effect transistors (VDMOSFETs) that have maximum voltage and current ratings as 200 V and 5.2A, respectively. We calculate the oxide capacitance using measurable reverse capacitance that is equal to gate–drain capacitance. The turn-around point is determined at each stress level. We observe that the oxide capacitance shows a nonlinear variation due to the stress time and level. The variation is divided into two regions for the model. The modeling procedure starts with the mathematical fitting. The equations are obtained by using curve fitting methods. The circuit model is designed via SPICE Simulation by using these equations. We also consider the turn-around points for the circuit design. The simulation and experimental results have good compatibility. We achieve 92.3% and 90.8% similarity on average for first and second region of the variation, respectively.

CMOS RF Switch With Fast Discharge Feature

A radio-frequency (RF) switch featuring a circuit for fast discharge of the gate oxide capacitance is presented in this letter. Two auxiliary transistors are added between the gate and source/drain terminals of the main switch. They are brought into the ON state for a short time at the beginning of the switching transient, discharging the gate of the main transistor, and speeding up the switching process. An integrated circuit implementing the proposed concept based on a large shunt switch has been designed and fabricated in Infineon 130-nm bulk-CMOS RF-switch technology. The measurements have demonstrated improvement in switching time (defined as the time between the control signal trigger edge and 90% of the target RF amplitude) of above 50% with no penalty in RF performance comparing to the conventional switch without discharge feature. The measured OFF-state insertion loss and ON-state isolation at 824 MHz were 0.12 and 27.2 dB, respectively.

Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor

The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

CPE Analysis from Cyclic Voltammetry and Electrochemical Impedance Spectroscopy

The electric properties of an electrode can be evaluated by the determination of the capacitance of the interface. However, the literature reports a large panel of experimental protocols for capacitance determination, which involve either cyclic voltammetry (CV) or electrochemical impedance spectroscopy (EIS). On the one hand, CV is a routine electrochemical technique widely used for the determination of electric properties of super capacitors or energy storage devices. The capacitive charge is determined through the variation of the scan rate in a non-faradaic current domain and is often used to estimate the performances of these electrodes. On the other hand, EIS is used for the determination of interfacial processes and also provides precise information on the double layer capacitance and the oxide capacitance in the case of more complex systems. However, substantial discrepancies in the assumptions are made between both techniques as in CV, the system is usually considered as ideal (and the current-scan rate relationship is assumed to remain linear at all frequencies), whereas in EIS, the system is usually considered as non-ideal and a CPE element is introduced. Although both techniques are used to provide similar information on the capacitive characteristics of electrochemical interfaces, a clear correlation between the results obtained with each technique is not straightforward. In fact, recent work from Allagui et al. [1]revealed that the time-voltage relationship cannot be used when the system is considered as ideal.In this work, electrochemical impedance spectroscopy and cyclic voltammetry were performed on well-known systems showing capacitive behaviours on a wide frequency domain and over a wide potential range: a blocking electrode (Au) and an electrode with a thin oxide film (Al). The capacitive charge was determined using cyclic voltammetry from the analysis of the conventional current to scan rate linear relationship and EIS measurement. In CV measurements, the calculated capacitance predominantly stems from the double layer capacitance for the considered scan rate ranges (low frequency range). Additionally, it was shown that the value of the determined capacitance is scan-rate dependent. Such experimental results highlight the arbitrary character of the scan rate ranges used in the literature as they usually remain in low frequency range. In fact, careful selection of scan rate is critical and should be adapted to the electrode considered, particularly for systems involving a thin oxide film as the Cdl or the Cox response depends on the frequency range. Similarly, the EIS response shows that the capacitance determination cannot be performed without a large error when a non-ideal behaviour is experimentally obtained. From a physical point of view, such outcome in this frequency domain is the results of observations made in the selected time domain [2].

Graphene Mobility Dependence on the Resistivity of Si Wafer

Graphene field effect transistors (GFETs) are typically benchmarked based on their field effect mobility. Constant mobility model proposed by Kim1 et.al is extensively used to derive this mobility parameter by directly fitting the transfer curves of graphene devices. Various methodologies were suggested to supplant and improve this existing mobility model. Among them Zhang2 et.al suggested the need for using measured gate oxide capacitance in order to extract mobility for top-gated GFETs. One of the commonly overlooked features, in the case of back gated GEFTs is the dopant concentration or the resistivity of Si substrate used. Herein, we explore the dependence of graphene carrier mobility on the induced carrier concentration and depletion capacitance of underlying Si substrate. Si with resistivities 0.01-0.02 Ω-cm and 0.001-0.005 Ω-cm were used to grow 10 nm thermal SiO2. GFETs were fabricated using CVD graphene on top of this thermal oxide substrate and the corresponding transfer curves are co-related with the capacitance density measured from corresponding MOSCAP structure. Detailed carrier mobility extraction and results are presented.(1) Kim, S.; Nah, J.; Jo, I.; Shahrjerdi, D.; Colombo, L.; Yao, Z.; Tutuc, E.; Banerjee, S. K. Realization of a High Mobility Dual-Gated Graphene Field-Effect Transistor with Al2O3 Dielectric. Appl. Phys. Lett. 2009, 94 (6). https://doi.org/10.1063/1.3077021.(2) Zhang, Z.; Xu, H.; Zhong, H.; Peng, L. M. Direct Extraction of Carrier Mobility in Graphene Field-Effect Transistor Using Current-Voltage and Capacitance-Voltage Measurements. Appl. Phys. Lett. 2012, 101 (21). https://doi.org/10.1063/1.4768690.

Extraction Technique for Flat Band Voltage Using Multi-Frequency C – V Characteristics in Amorphous InGaZnO Thin-Film-Transistors

An extraction technique for flat band voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> ) in an amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) using the frequency-independent C - V relationship which is taken from the measured multi-frequency C - V characteristics, is proposed. The proposed method comprises the consideration of multiple physical parameters for accurate VFB extraction, including the sub-gap density of states, doping concentration, gate oxide capacitance, and series resistance. The method was verified by comparing both the measured current-voltage characteristics and the extracted V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> value with the technology computer-aided design simulation results. Moreover, we confirmed the versatility of the method by extracting VFB from devices with different oxygen contents. The proposed physical-based technique showed better accuracy and compatibility with amorphous oxide semiconductor (AOS) TFTs compared with classical empirically based methods. We believe that our technique is useful for the experimental design and optimization of the gate metal-dielectric-AOS stack for highperformance AOS TFTs.

Temperature Dependent Leakage Current Characteristics of an IrO &lt;sub&gt;2&lt;/sub&gt;/TiO &lt;sub&gt;2&lt;/sub&gt;/IrO &lt;sub&gt;2&lt;/sub&gt; Redox Based Memristor and the Role of Aqueous Oxygen Evolution

Among materials that exhibit so-called memristive effects, high permittivity oxide-based capacitors are in the main focus in electronics research, as they tend to show a resistance that is dependent on the electrical history of the material. Since memristive effects were discovered in TiO2 thin films in the early 2000s there has been much effort to integrate memristive materials into next-generation resistive switching based random-access memories. In this study, we investigate the leakage current behaviour of high-k IrO2/TiO2/IrO2 capacitors with temperature dependent static current/voltage measurements and time dependent long-term leakage current measurements. We explain the highly complex leakage current characteristics of such high-k oxide capacitors with an existing leakage current model that incorporates redox processes between insulator and electrode. We conclude that due to the highly asymmetric leakage current behaviour of our symmetric IrO2/TiO2/IrO2 capacitors the oxygen vacancy density in the insulating TiO2 is most decisive and is dominated by the oxygen storage capacity of the electrode. There is strong evidence for an aqueous oxygen evolution of water incorporated in the IrO2 top electrode, which provides the oxygen that changes the vacancy density with temperature and bias condition. Finally, we expand the existing model with a qualitative description of how the redox processes influence the electrical performance of the capacitors as a function of time.

A novel low line regulation CMOS voltage reference without BJTs and resistors

A novel CMOS-only low line regulation voltage reference is presented in this paper. An output subcircuit composed of MOSFETs operating in the subthreshold region and saturation region is utilized to eliminate the temperature dependence of mobility and oxide capacitance, and produces a temperature-insensitive voltage reference. No bipolar junction transistors (BJTs) or resistors are used which can decrease the area greatly. By using most of the transistors operating in the subthreshold region, the power dissipation and the supply voltage are reduced. The proposed voltage reference is designed in the standard 0.18 μm CMOS process. The simulation results show that the output voltage is 958.971 mV at TT process corners, a temperature coefficient of 18.6096 ppm/°C range from20 °C to 110 °C is achieved, the line regulator (LR) of the proposed circuit is 0.037 mV/V from 1.5 V to 2.5 V supply voltage, and the power supply rejection ratio (PSRR) is75.77 dB at 100 Hz. The active area of the presented voltage reference is 0.0038 mm 2 .

Insight into Threshold Voltage and Drain Induced Barrier Lowering in Negative Capacitance Field Effect Transistor

In this paper, we have discussed threshold voltage and drain induced barrier lowering in NCFET. Threshold voltage in NCFET is lower as compared to MOSFET which is mainly because of negative equivalent oxide capacitance in NCFET. Further, we have discussed drain induced barrier lowering in NCFET and MOSFET. An increase in drain bias in MOSFET leads to decrease in threshold voltage and an increase in leakage current whereas in NCFET increase in drain bias leads to increase in threshold voltage and decrease in leakage current. We have obtained a positive value of DIBL factor for MOSFET and negative value for NCFET.

Development of Co-doped MnFe2O4 nanoparticles for electrochemical supercapacitors

Transition metal ferrites are the essential components utilized in the latest modern-day technology and these include greater elements whose oxidation states and ionic radii are important for exploring their magnetic, optical, structural, and electrochemical properties. The present investigation was targeted on the preparation, physical and electrochemical characterizations of Co-doped MnFe2O4 nanomaterials such as 2 wt% Co-doped MnFe2O4, 4 Wt.% Co-doped MnFe2O4, and 8 Wt.% Co-doped MnFe2O4. More specifically, the study will focus on the techniques which have been employed to raise the specific capacitance of the metal oxides. Electrochemical properties such as cyclic voltammetry (CV), potentiostatic and impedance were used to analyse the super capacitive performance of Co-doped MnFe2O4 electrodes. Based on the outcomes, it is determined that 2 wt% of Co-doped MnFe2O4 has higher super capacitive behaviour than different samples. Precise capacitance for this nanocomposite from GCD was determined to be 551.39 F/g at a current density of 1 mA/cm2. Accordingly, Co-doped MnFe2O4 may be utilized as a promising electrode for energy storage applications. It could be believed that this form of composites indicates excellent capability as electrochemical supercapacitors.

Semiconducting properties of passive films and corrosion layers on weathering steel

Anodic films were grown on Weathering Steel by potentiostatic polarization in slightly alkaline solution. The photoelectrochemical results reveal that they are n-type iron oxide with Eg = 2.0 eV. Rust layer grown by atmospheric corrosion are n-type semiconductors with a band gap higher than that estimated for the anodic film attributed to the formation of γ-lepidocrocite. The electrochemical impedance spectra allow to evidence that rust layers have a higher conductivity with respect to anodic films due to the presence of highly doped iron oxide layers. The use of Mott-Schottky theory to model the dependence of oxide capacitance as function of potential is critically discussed.

Enhanced performance of Fe-doped manganese oxide films as supercapacitor electrodes

This paper reports enhancement in the specific capacitance of iron-doped manganese oxide ( $$\hbox {MnO}_{\mathrm {2}})$$ films, potentiostatically deposited on stainless-steel substrates. The properties of deposited films were investigated through cyclic voltammetry and galvanostatic charge/discharge characteristics. The specific capacitance, as determined through cyclic voltammetry and galvanostatic charge/discharge characteristics, respectively, was found to be 248.79 and 277.5 F $$\hbox {g}^{\mathrm {-1}}$$ for undoped films, whereas it exhibited an increase with doping and was found to be 449.61 and 487.5 F $$\hbox {g}^{\mathrm {-1}}$$ , respectively, corresponding to a dopant concentration of 4 atomic percentage. The electrochemical impedance data were fitted with a modified Randles equivalent circuit to find series resistance, charge-transfer resistance, double-layer capacitance and ion diffusion. According to electrochemical impedance spectroscopy, the enhancement of ion diffusion was found to be the major cause for enhancement in capacitive performance of the films.

Characterization of Subgap Density-of-States by Sub-Bandgap Optical Charge Pumping in In0.53Ga0.47As Metal-Oxide-Semiconductor Field-Effect Transistors

We report an experimental characterization of the interface states (Dit(E)) by using the subthreshold drain current with optical charge pumping effect in In0.53Ga0.47As metal-oxide-semiconductor fieldeffect transistors (MOSFETs). The interface states are derived from the difference between the dark and photo states of the current-voltage characteristics. We used a sub-bandgap photon (i.e., with the photon energy lower than the bandgap energy, Eph < Eg) to optically excite trapped carriers over the bandgap in In0.53Ga0.47As MOSFETs. We combined a gate bias-dependent capacitance model to determine the channel length-independent oxide capacitance. Then, we estimated the channel length-independent interface states in In0.53Ga0.47As MOSFETs having different channel lengths (Lch = 5, 10, and 25 [μm]) for a fixed overlap length (Lov = 5 [μm]).

Frequency-Agile Low-Temperature Solution-Processed Alumina Dielectrics for Inorganic and Organic Electronics Enhanced by Fluoride Doping.

The frequency-dependent capacitance of low-temperature solution-processed metal oxide (MO) dielectrics typically yields unreliable and unstable thin-film transistor (TFT) performance metrics, which hinders the development of next-generation roll-to-roll MO electronics and obscures intercomparisons between processing methodologies. Here, capacitance values stable over a wide frequency range are achieved in low-temperature combustion-synthesized aluminum oxide (AlOx) dielectric films by fluoride doping. For an optimal F incorporation of ∼3.7 atomic % F, the F:AlOx film capacitance of 166 ± 11 nF/cm2 is stable over a 10-1-104 Hz frequency range, far more stable than that of neat AlOx films (capacitance = 336 ± 201 nF/cm2) which falls from 781 ± 85 nF/cm2 to 104 ± 4 nF/cm2 over this frequency range. Importantly, both n-type/inorganic and p-type/organic TFTs exhibit reliable electrical characteristics with minimum hysteresis when employing the F:AlOx dielectric with ∼3.7 atomic % F. Systematic characterization of film microstructural/compositional and electronic/dielectric properties by X-ray photoelectron spectroscopy, time-of-fight secondary ion mass spectrometry, cross-section transmission electron microscopy, solid-state nuclear magnetic resonance, and UV-vis absorption spectroscopy reveal that fluoride doping generates AlOF, which strongly reduces the mobile hydrogen content, suppressing polarization mechanisms at low frequencies. Thus, this work provides a broadly applicable anion doping strategy for the realization of high-performance solution-processed metal oxide dielectrics for both organic and inorganic electronics applications.

High-k HfxZr1-xO₂ Ferroelectric Insulator by Utilizing High Pressure Anneal

In this article, we report the fabrication of Zr-rich high-k ferroelectric hafnium zirconium oxide (HZO) capacitor with TiN as the top and bottom electrodes demonstrating an equivalent oxide thickness (EOT) of 5.7 Å and remanent polarization (Pr) of ~16 μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . High-k-value and low EOT was achieved by utilizing multiphase region of HZO as well as high pressure post metallization annealing (HPPMA). Despite the high-k value of Zr-rich HZO films, the emergence of multiphase region at higher physical-thickness when annealed using rapid thermal annealing (RTA) limits its EOT value. On the contrary, multiphase emerges at a smaller physical thickness in HPPMA due to the formation of more o-phase as revealed by grazing incidence X-ray diffractometer (GIXRD). The smaller physical thickness of HPPMA together with the demonstration of significantly higher dielectric constant (>50) by HZO in the vicinity of multiphase, was therefore, found to be very effective in reducing the EOT.

Uniformity of Gate Dielectric for I/O and Core HK/MG pMOSFETs with Nitridation Treatments

Uniformity consideration in integrated-circuit manufacturing is an impressive task, especially in the field of nano-node semiconductors. The use of high-dielectric-constant (high-K) materials to promote drive current in deep nano-node devices is also increasing. One solution involves enhancing the quality of the high-K dielectric layer as a gate dielectric with nitridation treatment. This study combines the aforementioned concerns in deep nano-node manufacturing and demonstrates their relationship. Given the electrical measurement of the wafers treated with decoupled plasma nitridation (DPN), a few desired key parameters, including drive current (IDS), threshold voltage (Vth), gate oxide capacitance per area (Cox), subthreshold swing (SS), and interface state density, in the design of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) are observed. A uniformity comparison with different DPN processes is also performed, and the uniformity of the gate dielectric in input/output and core zones is discussed. Based on the uniformity distribution, lower SS values are obtained by adopting the low-temperature nitridation treatment after high-K dielectric deposition. The increased nitrogen concentration decreases the deviation, thereby indicating improved uniformity of SS values.

An Extended-Gate Ion-Sensitive Field-Effect Transistor with CMOS Technology-Intrinsic TiN Sensing Layer

The extended-gate ion-sensitive field-effect transistor (EGISFET) has promising potentials in chemical and biological sensing due to flexibility for array arrangement, less light-sensitivity, and compatibility with CMOS standard fabrication process [1-2]. An EGISFET is consisted of a MOSFET and a floating-gate structure separated from analyte solutions by a sensing layer. Because charges adjacent to the sensing layer change the floating-gate potential, the channel current of the EGISFET can be modulated through the electrical field effect. In a general CMOS process, the EGISFET can be achieved by using metal/VIA/polysilicon layers as the extended gate material and the passivation nitride layer on top of the metal as the sensing layer. For the EGISFET operation, a solution gate voltage is provided in the analyte solution and a capacitive voltage divider can be obtained based on a series connection of the electrical double layer capacitance (CEDL), the sensing layer capacitance (CS) and the gate oxide capacitance (COX). Due to the capacitive coupling nature, a higher CS/(CS+COX) ratio can have a larger part of solution gate voltage transferred to COX, and thus can have a higher EGISFET transconductance [3], which promises a better sensing response, e.g. channel-current change for a given charge change. However, CS is decreasing because of scaling down for realizing high spatial resolution sensing array. Then EGISFETs become less sensitive due to a weaker capacitive coupling.In order to ameliorate this scaling effect, we developed a TiN-EGISFET based on a CMOS 0.35 μm standard fabrication process. Instead of using the 1-2 μm thick passivation/intermediate dielectric layer as the sensing layer, we took advantage of an intrinsic extra-thin TiN layer within the VIA structure as the sensing layer. To expose the TiN layer, the metal/VIA layout was placed in a special manner to form a hanging micro-structure after a one-step wet etching. Followed by sonication, the micro-structure was broken at a mechanical weak point, e.g. the metal/VIA interface, and the ultra-thin TiN was successfully exposed. To have a control group, a traditional EGISFET was also implemented on the same chip. In the EGISFET measurement, a Ag/AgCl electrode was used to provide solution gate voltage, and the electric characteristic curve for each device was measured in pH solutions with different values.Compared to the traditional EGISFET occupying the same chip area, transconductance for the TiN-exposed EGISFET was improved up to 240%. This enhancement is possibly attributed to the conductivity and chemical stability of TiN, which make CS in the TiN-exposed region disappeared, only left CEDL and COX in series. As a result, a larger portion of solution gate voltage is dropped across COX because CEDL>>COX. Furthermore, the pH sensitivity of TiN-exposed EGISFET reaches 51 mV/pH without obvious hysteresis and drift (Figure 1). This is also supported by the previous literatures [4-5]. At 0.5V overdrive voltage, the current variation of TiN-exposed EGISFET is -9.12 mA/pH, which is 275% as high as that of the traditional EGISFET (Figure 2). These results suggest that a TiN-exposed EGISFET with a smaller footprint can possess the same sensitivity of a traditional EGISFET with a larger footprint.In conclusion, we developed a method to fabricate EGISFETs with TiN sensing layers in a commercialized CMOS process. This is the first time to have the in-situ TiN EGISFET in the CMOS process without extrinsic TiN deposition. This method can be employed to realize EGISFETs with higher density in a given area without sacrificing sensitivity, thus potentially beneficial to the development of high performance and high spatial resolution ISFET sensing array.

A Comparative Study of Electrochemical Capacitance of Graphene Oxide Affected by Oligomers of p-phenylenediamine and Hydrazine Hydrate in Solvothermal Condition

A systematic investigation of the graphene oxide composite reduced by either p-phenylenediamine oligomers or hydrazine hydrate was performed with field emission scanning electron microscopy, high resolution transmission electron microscopy, X-ray diffraction, fourier transform infrared, and X-ray photoelectron spectroscopy analyses. The electrical capacitance of the composite was evaluated by a cyclic voltammetry technique, while the properties of these prototype supercapacitors were measured by a chronopotentiometry technique. It was found that, under the solvothermal condition, the graphene oxide reduced by p-phenylenediamine oligomers was observed to have higher electrical capacitance than that reduced by hydrazine. The improved electrical capacitance can be attributed to that p-phenylenediamine oligomers are the more effective spacers for graphene layers; and they could also provide some pseudo-capacitance to the graphene oxide composite based on their conjugate structure. The results imply that graphene oxide modified by diamine oligomers has a good potential in energy storage devices.