Output Data Rate Research Articles

Region Based Cluster Aided Routing Protocol for Environment Monitoring in Heterogeneous Wireless Sensor Networks

Heterogeneous wireless sensing networks (HWSNs) that are limited by their batteries' power consumption might benefit greatly from more efficient routing algorithms. It is essential that routing accounts for the diversity of network nodes to achieve optimal performance. This letter considers sensor nodes with random initial energies and random disparities in data output rate (traffic) to build a realistic clustering-based WSN suitable for heterogeneous sensing applications. The protocol divides the space into numerous zones with different distance thresholds to deal with the hotspot problem that the multi-hop method creates. The advantages of region-divided routing ensure that only qualified nodes compete for the role of cluster's head during the choice phase and that the cluster heads with the greatest remaining energy in the extremely energetic area are selected as the relay node throughout the inter-cluster routing that includes several hops phase. The simulation findings demonstrate that the protocol may efficiently equalize energy consumption throughout the network, eliminate the issue of "hot spots," be used in an energy-diverse system, and lengthen the service life of the network.

An Enhanced Indoor Three-Dimensional Localization System with Sensor Fusion Based on Ultra-Wideband Ranging and Dual Barometer Altimetry.

Accurate three-dimensional (3D) localization within indoor environments is crucial for enhancing item-based application services, yet current systems often struggle with localization accuracy and height estimation. This study introduces an advanced 3D localization system that integrates updated ultra-wideband (UWB) sensors and dual barometric pressure (BMP) sensors. Utilizing three fixed UWB anchors, the system employs geometric modeling and Kalman filtering for precise tag 3D spatial localization. Building on our previous research on indoor height measurement with dual BMP sensors, the proposed system demonstrates significant improvements in data processing speed and stability. Our enhancements include a new geometric localization model and an optimized Kalman filtering algorithm, which are validated by a high-precision motion capture system. The results show that the localization error is significantly reduced, with height accuracy of approximately ±0.05 m, and the Root Mean Square Error (RMSE) of the 3D localization system reaches 0.0740 m. The system offers expanded locatable space and faster data output rates, delivering reliable performance that supports advanced applications requiring detailed 3D indoor localization.

A 1024-Channel 268 nW/pixel 36×36 μm2/channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.

This paper presents a data-compressive neural recording IC for single-cell resolution high-bandwidth brain-computer interfaces. The IC features wired-OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146× on average while allowing the reconstruction of spike samples. The recording array consists of pulse position modulation-based active digital pixels with a global single-slope analog-to-digital conversion scheme, which enables a low-power and compact pixel design with significantly simple routing and low array readout energy. Fabricated in a 28-nm CMOS process, the neural recording IC features 1024 channels (i.e., 32 × 32 array) with a pixel pitch of 36 μm that can be directly matched to a high-density microelectrode array. The pixel achieves 7.4 μVrms input-referred noise with a -3 dB bandwidth of 300-Hz to 5-kHz while consuming only 268 nW from a single 1-V supply. The IC achieves the smallest area per channel (36 × 36 μm2) and the highest energy efficiency among the state-of-the-art neural recording ICs published to date.

Optimized design and characterization of HYLITE, a charge-integration readout chip of XFEL

HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel readout chip designed for SHINE (Shanghai HIgh repetition rate XFEL aNd Extreme light facility). The target specifications for the full-size HYLITE chip include a pixel matrix of 128 × 128 pixels and a frame rate of 10 kHz. In order to meet these specifications, two small-scale chips, designated HYLITE0.1 and HYLITE0.2, were fabricated and underwent comprehensive testing. Some issues were discovered during tests including the noise performance and the error of output ADU (Analog Digital Units) codes.The HYLITE200S represents the third prototype chip developed to address the above issues. The CDS (Correlated Double Sampling) circuits and glitch-clear clock structures are integrated in pixels. Furthermore, to meet the data output rate requirements of the full-size chip, a high-speed data interface has been designed. Test results show that the signal-to-noise ratio is improved to 9.31 for a 12 keV single photon, and the ADU error is fixed. By integrating a phase-locked loop and a balanced encoding logic, the data interface can work steadily at a speed of 3.125 Gbps.

Concepts for the data flow control on the XIDer readout ASIC

XIDer is a 2D pixelated hybrid X-ray detector that is supposed to act as a multi-purpose platform for diffraction experiments at fourth-generation high-energy synchrotron light sources like the Extremely Brilliant Source of the European Synchrotron Radiation Facility (ESRF-EBS). As such it needs to tackle a wide variety of requirements. These include x-ray energies of 30keV to 100keV imposing the utilisation of high-Z sensors, a wide dynamic range from single photons to fluxes of 1 × 109photonspixel−1s−1 and expected raw data rates up to the order of TBs−1 in the final detector design.As a result, XIDer’s readout ASIC has to provide smart and flexible ways for on-chip data pre-processing to reduce the output data rate to manageable sizes. This article focusses on introducing the ASIC’s novel and unique data-handling concepts like the custom-designed telegram protocol followed by the presentation of exemplary configurations and use cases.

A 17.6-Bit 800-SPS Energy-Efficient Read-Out IC With Input Impedance Boosting

A 17.6-bit, 800-sample-per-second (SPS) read-out integrated circuit has been implemented for a bridge sensor. The read-out integrated circuit has a capacitively-coupled instrumentation amplifier (CCIA) with a sensor offset voltage compensation circuit, an amplifier offset voltage compensation circuit, and an input impedance boosting loop (IBL). Followed by the CCIA, a programmable-gain third-order discrete-time incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an output data-rate of 12.8 kHz shortens the sensing time to reduce the static power consumption of the resistive bridge sensor and the read-out IC. To boost the input impedance of the CCIA, the system-level input and output choppers operate at a frequency of 12.8 kHz. The ΔΣ modulator converts the modulated signal to digital with a sampling clock of 4 MHz. The system-level chopping reduces the residual offset and the low-frequency noise with an on-chip cascade of integrators (CoI) filter. Implemented in a 0.13 μm CMOS process, the read-out circuit achieves an input impedance of 22 MΩ at a data-rate of 800 SPS, a sensor offset compensation range of ± 350 mV, a maximum effective resolution of 17.6 bits, and an input-referred noise of 1.72 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> at a gain of 128. It draws an average current of 106.3 μA from a 3 V supply and 1.3 μA from a 1.5 V supply.

Optimization and commissioning of the EPIC commensal radio transient imager for the long wavelength array

ABSTRACT Next-generation aperture arrays are expected to consist of hundreds to thousands of antenna elements with substantial digital signal processing to handle large operating bandwidths of a few tens to hundreds of MHz. Conventionally, FX correlators are used as the primary signal processing unit of the interferometer. These correlators have computational costs that scale as $\mathcal {O}(N^2)$ for large arrays. An alternative imaging approach is implemented in the E-field Parallel Imaging Correlator (EPIC) that was recently deployed on the Long Wavelength Array station at the Sevilleta National Wildlife Refuge (LWA-SV) in New Mexico. EPIC uses a novel architecture that produces electric field or intensity images of the sky at the angular resolution of the array with full or partial polarization and the full spectral resolution of the channelizer. By eliminating the intermediate cross-correlation data products, the computational costs can be significantly lowered in comparison to a conventional FX or XF correlator from $\mathcal {O}(N^2)$ to $\mathcal {O}(N \log N)$ for dense (but otherwise arbitrary) array layouts. EPIC can also lower the output data rates by directly yielding polarimetric image products for science analysis. We have optimized EPIC and have now commissioned it at LWA-SV as a commensal all-sky imaging back-end that can potentially detect and localize sources of impulsive radio emission on millisecond timescales. In this article, we review the architecture of EPIC, describe code optimizations that improve performance, and present initial validations from commissioning observations. Comparisons between EPIC measurements and simultaneous beam-formed observations of bright sources show spectral-temporal structures in good agreement.

Design of High-Precision Micro-Capacitance Detection System

The focus of this paper is on the development of micro-displacement measurement system of Beam Steering Mechanism (BSM) and Fast Sweeping Mirror (FSM) using in space remote sensor. The main objective is to design a micro-capacitance measuring technology based on Pcap01. In the proposed approach, first, the principle of capacitance measurement and the design of hardware and software of the system are introduced; then, the system is implemented to high-precision results below 3.5nF. The experiment results show that under the 1KHz output data rate, the system can achieve a resolution of 1.4fF in the range of 1pF~30pF, which can meet the system requirements of range and accuracy ratio of 20000.

Silicon vertex detector with timing for the Upgrade II of LHCb

LHCb has recently submitted a physics case for an Upgrade II detector to begin operation in 2031. The upcoming upgrade is designed to run at instantaneous luminosities of 1.5×1034cm−2s−1, to accumulate a data sample with a corresponding integrated luminosity of over 300fb−1. The LHCb physics programme relies on an efficient and precise vertex detector (VELO). Compared to Upgrade I, the data output rates, radiation levels and occupancies will be about ten times higher. To cope with the pile-up increase, new techniques to assign b-quark–hadrons to their primary vertex, and to perform the real-time pattern recognition are needed. To solve these problems, a new 4D hybrid pixel detector with enhanced rate and timing capabilities in the ASIC and sensor will be developed. This report will discuss the most promising technologies to be used in the future upgrade for the HL-LHC, with emphasis on the timing precision as a tool for vertexing in the next generation detectors. An initial simulation effort has been made to investigate what would be the required temporal resolution sufficient to mitigate pile-up and identify secondary vertices, which points to at least 20 ps per track. The most recent results from beam tests motivated by time measurements will be presented together with the R&D scenarios for the future upgrade. Improvements in the mechanical design of the Upgrade II VELO will also be needed to allow for periodic module replacement. The design will be further optimised to minimise the material before the first measured point on a track and to achieve a fully integrated module design with thinned sensors and ASICs combined with a lightweight cooling solution.

A transmitting circuit with adaptive calibration of output impedance for high speed interface

A transmitting circuit for high-speed interface is proposed in this paper. Optimized 10-bit parallel to serial conversion and embedded output impedance calibration are used for enhancing the performance of this transmitting circuit. Designed with 0.18 μm CMOS, this transmitting circuit can achieve an output data rate of 1.5625 Gbps with 10-bit 156.25 MHz parallel input. The output amplitude of the current mode logic (CML) driver is 1.28 Vpp with a jitter of 24.3 ps. After adaptive calibration, the mismatch between output impedance and its expected value is within 0.5%. The active area of this entire transmitting circuit is 220.1 μm × 197.5 μm. With 1.8 V power supply, the power consumption of this transmitting circuit is 41.2 mW at 1.5625 Gbps data rate.

Multi-scale asynchronous fusion algorithm for multi-sensor integrated navigation system

The asynchronous fusion method is the key technology of multi-sensor integrated navigation system which is independently observed by multiple auxiliary navigation sensors with different data output rates. The multi-scale asynchronous fusion can effectively increase the accuracy of integrated navigation system, but the existing multi-scale asynchronous fusion algorithm has the characteristic of heavy computational burden and requires the data output rates of auxiliary navigation sensors to meet unrealistic special requirements. To solve this problem, a multi-scale asynchronous fusion algorithm for the multi-sensor integrated navigation system is presented based on state block vector and wavelet transform. This algorithm first converts the system’s original state equation into the relationship between the state block vector and the state point vector to obtain the state equation of the multi-scale dynamic system, and expresses the original measurement equation as the relationship with the state block vector to obtain the measurement equation of the multi-scale dynamic system. Then, the special implementation process of this algorithm is studied and expressed in details, on the basis of the matrix operator with scale and wavelet property. Finally, a multi-sensor integrated navigation system composed of strapdown inertial navigation system, celestial navigation system, global navigation satellite system, and air data system is designed and experimented validation analysis. Experiment results show that this algorithm can significantly reduce the average root mean square error and improve the accuracy of navigation parameters, compared with asynchronous preprocessing Kalman filter and asynchronous direct Kalman filter. It would have a wide prospect in multi-sensor integrated navigation systems.

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

An 8 gigabits per second (Gbps), low-jitter, four-channel transmitter with fractional-spaced feed-forward equalizer (FFE) is designed to meet the demand for broad transmission bandwidth in serial data communications. A novel frequency divider chain (FDC) architecture is developed, to satisfy the time requirements for high-speed data serialization. Moreover, a reconfigurable output driver circuit is employed to ensure compatibility with different protocols. In addition, a three-tap fractional-spaced FFE, which can enhance signal bandwidth significantly, is proposed, to compensate for channel loss. The transmitter was simulated and validated based on the Semiconductor Manufacturing International Corporation (SMIC) 55-nm process. The post-layout simulation results show the following: The tuning range of the phase-locked loop (PLL) can cover 1.6 to 4.6 GHz. At an output frequency of 4 GHz, the root-mean-square jitter (RJ) of the PLL after integration from phase noise was 1.93 ps. With an 8 Gbps output data rate, using the pseudo-random binary sequence (PRBS)-31 as a data source to simulate the whole transmitter, the power consumption values of the PLL and drive circuit were 27.0 and 29.2 mW, respectively, and the eye width and the valid eye height of output data were 0.76 unit interval (UI) and 0.68.

Low-Power Detection and Classification for In-Sensor Predictive Maintenance Based on Vibration Monitoring

In this work, a new custom design of an anomaly detection and classification system is proposed. It is composed of a convolutional Auto-Encoder (AE) hardware design to perform anomaly detection which cooperates with a mixed HW/SW Convolutional Neural Network (CNN) to perform the classification of detected anomalies. The AE features a partial binarization, so that the weights are binarized while the activations, associated to some selected layers, are non-binarized. This has been necessary to meet the severe area and energy constraints that allow it to be integrated on the same die as the MEMS sensors for which it serves as a neural accelerator. The CNN shares the feature extraction module with the AE, whereas a SW classifier is triggered by the AE when a fault is detected, working asynchronously to it. The AE has been mapped on a Xilinx Artix-7 FPGA, featuring an Output Data Rate (ODR) of 365 kHz and achieving a power dissipation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$333 \boldsymbol {\mu } $ </tex-math></inline-formula> W/MHz. Logic synthesis has targeted TSMC CMOS 65 nm, 90 nm, and 130 nm standard cells. Best results achieved highlight a power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$138 \boldsymbol {\mu } $ </tex-math></inline-formula> W/MHz with an area occupation of 0.49 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when real-time operations are set. These results enable the integration of the complete neural accelerator in the CMOS circuitry that typically sits with the inertial MEMS on the same silicon die. Comparisons with the related works suggest that the proposed system is capable of state-of-the-art performances and accuracy.

Comparative analysis of model‐based and traditional systems engineering approaches for simulating a robotic space system architecture through automatic knowledge processing

AbstractModel‐based Systems Engineering (MBSE) case studies in the literature assert that there are benefits to MBSE when applied to modeling and simulating space systems. This research evaluates the benefits of an MBSE modeling and simulation approach over a traditional, non‐MBSE approach through modeling and simulation of an orbiting sample Capture and Orient Module (COM) architecture for potential Mars Sample Return (MSR). The COM architecture was modeled, simulated, and evaluated against nominal load power and output data rate requirements to compare the two approaches. A new modeling and simulation‐centric V‐model was synthesized from existing V‐model and modeling and simulation process models to map out the modeling and simulation activities within the context of the system development lifecycle and used as a tool to compare the non‐MBSE and MBSE approaches. A three‐phase modeling and simulation process consisting of an analysis and modeling phase, computer programming and implementation phase, and experimentation phase was used to model and simulate the COM. The total number of manual and automatic knowledge processed was calculated for both approaches and used to quantify the benefits of the MBSE approach relative to the non‐MBSE approach. In the non‐MBSE approach, all knowledge elements were manually processed during the modeling and simulation process. In the MBSE approach, 49% of total knowledge processing was automated. The MBSE approach showed user experience benefits with modeling and simulating the COM robotic space system through providing a higher level of support for automation, reducing the burden of systems engineering tasks, and reducing effort.

A hierarchical congestion control method in clustered internet of things

Internet of things (IoT) is a modern technology where data can be transmitted to any things (human, animal, or object) over communications networks, whether internet or intranet. Congestion occurs when the input data rate to the node was higher than the output data rate of node. Congestion control in computer network modulates traffic entry into a network in order to avoid congestive. This paper suggests a method for congestion control in the internet of things in two phases. The first phase is intra-cluster congestion control, which uses two parameters, congestion score (CS) and buffer empty space (BES), to congestion avoidance. In this phase based on these two parameters, nine states are defined to determine the congestion status of each node, and based on these 9 states the appropriate decision is made to the node. The second phase is inter-cluster congestion control. In this phase, after determining cluster head priority, the parameters of back-off timer (BFT), waiting time to receive acknowledgment \(({\text {WTTR}}_{\text {ACK}})\), sequence number (SEQ) and retransmission counter (RC) are used for congestion control. The proposed congestion control method is simulated by NS-2 software. A comparison between the performance of proposed method and conventional methods shows that applying proposed method results in a significant improvement in average congestion score (CS), packet lost rate, energy consumption and end-to-end delay.

Antenna System for Trilateral Drone Precise Vertical Landing

This paper presents a radio frequency system that can be used to perform precise vertical landings of drones. The system is based on the three-way phase shift detection of a signal transmitted from the landing point. The antenna system is designed by taking into account parameters such as landing tracking area, analog to digital converter (ADC) resolution, phase detector output range, antenna polarization and the effect of antenna axial ratio. The fabricated prototype consists of a landing point antenna that transmits a signal at 2.46 GHz, as well as a drone tri-antenna system that includes a phase shift detection circuitry, ADC and a simple control program that provides the correction instructions for landing. The prototype provides an averaged output data rate (ODR) suitable for landing maneuvers (&#x003E;300 Hz). A simple system calibration procedure (detector output zeroing) is performed by aligning the antenna system. The measurements performed at different altitudes demonstrate both the correct operation of the proposed solution and its viability as an instrument for precision vertical landings.

The LHCb vertex locator upgrade — the detector calibration overview

The Vertex Locator (VELO) is a silicon tracking detector in the spectrometer of the Large Hadron Collider beauty (LHCb) experiment. LHCb explores and investigates CP violation phenomena in b- and c- hadron decays and is one of the experiments operating on the Large Hadron Collider (LHC) at CERN. After run 1 and run 2 of LHC data taking (2011–2018), the LHCb detectors are being modernized within the LHCb upgrade I program. The upgrade aims to adjust the spectrometer to readout at full LHC 40 MHz frequency, which requires radical changes to the technologies currently used in LHCb. The hardware trigger is removed, and some of the detectors replaced. The VELO changes its tracking technology and silicon strips are replaced by 55 μm pitch silicon pixels. The readout chip for the VELO upgrade is the VeloPix ASIC. The number of readout channels increases to over 40 million, and the hottest ASIC is expected to produce the output data rate of 15 Gbit/s. New conditions challenge the software and the hardware side of the readout system and put special attention on the detector monitoring. This paper presents the upgraded VELO design and outlines the software aspects of the detector calibration in the upgrade I. An overview of the challenges foreseen for the upgrade II is given.

A 2/3-in. 9.5-Mpixel CMOS Imager With High Frame Rate and HDR Capabilities

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">This study explains the architecture and readout schemes used to achieve a 2/3-in. 9.5-Mpixel complementary metal oxide semiconductor (CMOS) imager, with 3.6 Gpixels/s enabling high frame-rate operation in native UHD-1/4K ultrahigh-definition (UHD) resolution and full high-dynamic range (HDR) support. The presented imager demonstrates an architecture that supports high spatial and temporal resolutions and a high output data rate. To fulfill the transfer time requirements, an innovative row addressing scheme has been developed to toggle between the different rows</i> .

A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

A custom HW design of a Fully Convolutional Neural Network (FCN) is presented in this paper to implement an embeddable Human Posture Recognition (HPR) system capable of very high accuracy both for laying and sitting posture recognition. The FCN exploits a new base-2 quantization scheme for weight and binarized activations to meet the optimal trade-off between low power dissipation, a very reduced set of instantiated physical resources and state-of-the-art accuracy to classify human postures. By using a limited number of pressure sensors only, the optimized HW implementation allows keeping the computation close to the data sources according to the edge computing paradigm and enables the design of embedded HP systems. The FCN can be simply reconfigured to be used for laying and sitting posture recognition. Tested on a public dataset for in-bed posture classification, the proposed FCN obtains a mean accuracy value of 96.77% to recognize 17 different postures, while a small custom dataset has been used for training and testing for sitting posture recognition, where the FCN achieves 98.88% accuracy to recognize eight positions. The FCN has been prototyped on a Xilinx Artix 7 FPGA where it exhibits a dynamic power dissipation lower than 11 mW and 7 mW for laying and sitting posture recognition, respectively, and a maximum operation frequency of 47.64 MHz and 26.6 MHz, corresponding to an Output Data Rate (ODR) of the sensors of 16.50 kHz and 9.13 kHz, respectively. Furthermore, synthesis results with a CMOS 130 nm technology have been reported, to give an estimation about the possibility of an in-sensor circuital implementation.

Design and comparative analysis of on-chip sigma delta ADC for signal processing applications

Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital signal processing applications. Various signal processing applications incorporated sigma delta ADC among different analog to digital converters because of its digital dominant architecture. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture with a very few passive components connected externally to FPGA suitable for signal processing applications, wireless application, sonar and radar beamforming. Schematic level architecture of high speed comparator working at a differential swing which is not allowed by FPGA standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed as on-chip continuous-time sigma-delta analog to digital converter architecture. SPICE simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using h-Spice and questasim simulations. schematic level architecture of a high speed comparator at a differential swing of 1.65 ± 1.5 V which is not allowed by standard differential pads is designed. Analysis illustrates that proposed on-chip continuous-time sigma-delta analog to digital converter exhibits a sampling rate of 400 MHz designed with high speed comparator with varied differential swing. Power analysis resulted with 1.86 mW for an input signal of 1 MHz. Optimal filtering is achieved with total decimation of 400, out of which the decimation of 100 is achieved by CIC filter and PFIR filter achieves remaining decimation factor of 4. Output data rate of 1 MHz with a dynamic range of 72 dB is achieved with less bill of material that suites for signal processing applications.