Abstract In a multi-party fair coin-flipping protocol, the parties output a common (close to) unbiased bit, even when some adversarial parties try to bias the output. In this work, we focus on the case of an arbitrary number of corrupted parties. Cleve [20] [STOC 1986] has shown that in any such m -round coin-flipping protocol, the corrupted parties can bias the honest parties’ common output bit by $$\Theta (1/m)$$ Θ ( 1 / m ) . For more than two decades, however, the best-known coin-flipping protocol was the one of Awerbuch, Blum, Chor, Goldwasser, and Micali [10] [Manuscript 1985], who presented a t -party, m -round protocol with bias $$\Theta (t/\sqrt{m})$$ Θ ( t / m ) . This was changed by the breakthrough result of Moran, Naor, and Segev [51] [Journal of Cryptology 2016], who constructed an m -round, two -party coin-flipping protocol with optimal bias $$\Theta (1/m)$$ Θ ( 1 / m ) . More recently, Haitner and Tsfadia [37] [SIAM Journal on Computing 2017] constructed an m -round, three -party coin-flipping protocol with bias $$O(\log ^3m / m)$$ O ( log 3 m / m ) . Still for the case of more than three parties, the best-known protocol remained the $$\Theta (t/\sqrt{m})$$ Θ ( t / m ) -bias protocol of [10]. We make a step toward eliminating the above gap, presenting a t -party, m -round coin-flipping protocol, with bias $$O\left( \frac{t^4 \cdot 2^t \cdot \sqrt{\log m}}{m^{1/2+1/(2^{t-1}-2)}}\right) $$ O t 4 · 2 t · log m m 1 / 2 + 1 / ( 2 t - 1 - 2 ) for any $$t\le \tfrac{1}{2} \cdot \operatorname {loglog}m$$ t ≤ 1 2 · loglog m . This improves upon the $$\Theta (t/\sqrt{m})$$ Θ ( t / m ) -bias protocol of [10], and in particular, for $$t\in O(1)$$ t ∈ O ( 1 ) it is an $$1/m^{\frac{1}{2} + \Theta (1)}$$ 1 / m 1 2 + Θ ( 1 ) -bias protocol. For the three-party case, it is an $$O(\sqrt{\log m}/m)$$ O ( log m / m ) -bias protocol, improving over the $$O(\log ^3m / m)$$ O ( log 3 m / m ) -bias protocol of [37]. Our protocol generalizes that of [37], by presenting an appropriate “recovery protocol” for the remaining parties to interact in, in the case that some parties abort or are caught cheating ([37] only presented a two-party recovery protocol, which limits their final protocol to handle three parties). We prove the fairness of the new protocol by presenting a new paradigm for analyzing fairness of coin-flipping protocols; the claimed fairness is proved by mapping the set of adversarial strategies that try to bias the honest parties’ outcome in the protocol to the set of the feasible solutions of a linear program. The gain each strategy achieves is the value of the corresponding solution. We then bound the optimal value of the linear program by constructing a feasible solution to its dual.

Exploiting output bits and the $$\chi $$ operation in MitM preimage attacks on Keccak

Self-attention mechanism (SAM) is good at capturing the intrinsic connection between features to dramatically boost the performance of machine learning models. Nevertheless, the capability of SAM is not equipped with many current quantum machine learning (QML) models, thus confining their expansion on massive high-dimensional quantum data. To address the above problems, a quantum SAM (QSAM) consisting of a quantum logic similarity (QLS)-based quantum bit self-attention score matrix (QBSASM) is introduced to augment the data representation of SAM exponentially. According to QSAM, the framework and quantum circuits of a one-step achievable quantum self-attention network (QSAN) are designed to consider measurement times compression fully. Moreover, a prototype of quantum coordinates is presented during the design process to describe the mathematical relationship between the output bits and the control bits to facilitate the programming. Ultimately, MNIST binary classification experiments on the PennyLane platform and comparisons with cutting-edge QML models demonstrate QSAN converges about $1.7\times $ and $2.3\times $ faster than hardware-efficient ansatz and quantum approximate optimization algorithm (QAOA) ansatz, respectively, with similar parameter configurations and 100% prediction accuracy, which indicates that it has a better learning capability. In the CIFAR-10 classification experiments, QSAN achieves high prediction accuracy at a small scale relative to classical machine learning models. Predictably, QSAN elevates the efficiency of QML models and lays the foundation for future quantum computers to perform machine learning on massive amounts of data while promoting the advancement of quantum computer vision and other fields.

Sensor arrays are important signal processing tools for improving Signal-to-Noise Ratio (SNR) and enabling direction finding. Underwater arrays are used in a variety of applications, such as communications, environmental monitoring, and SONAR. Unfortunately, student access to underwater arrays is often limited by the need for expensive specialized hardware. This talk presents a flexible, low-cost underwater acoustic array testbed built with consumer off the shelf components. The system costs approximately $2200. The transmitter consists of an amplifier driven by a standard laptop audio output and a Lubell Labs UW30 transducer. The receiver consists of an array of four Aquarian Audio A5 hydrophones connected to a USB audio interface for data acquisition by a second laptop. The talk describes the system design and characterizes the transmitter and receiver frequency responses. An experiment illustrates how the testbed can facilitate the study of arrays in underwater communications. The transducer and array are deployed in shallow water environments, i.e., a competition pool and a lake. The experiment measures output SNR and bit error rate using several communication protocols, including on-off keying and frequency-shift keying.

представлена архитектура декодера, которая характеризуется высокой производительностью, низкой сложностью и высокой скоростью работы для сверхдлинных квазициклических LDPC-кодов. Описывается архитектура и работа LDPC-декодера, реализованного на программируемой логической интегральной схеме (ПЛИС). Особое внимание уделяется структуре считывания и записи данных в процессе итеративного декодирования, где для адресации памяти PCM (Phase Change Materials, фазопереходные материалы) используется простой счетчик, а параллельный ввод-вывод управляется таблицей поиска. Подробно рассмотрен механизм чтения и записи, с акцентом на их переупорядочивание перед обработкой в NPU (Node Processing Units). Описан модуль принятия решения, проверяющий успешность декодирования путем сравнения рассчитанного синдрома с полученным, а также модуль, генерирующий выходные биты на основе знаковых. Приведены результаты моделирования, демонстрирующие производительность декодера через параметры битовой ошибки (BER), среднее количество итераций, пропускную способность и потребление ресурсов. Показано, что производительность алгоритма суммы-произведения (SPA) превосходит алгоритм минимальной суммы (MSA), хотя MSA имеет меньшую сложность. Отмечена зависимость среднего количества итераций от отношения сигнал/шум (SNR), а также незначительное влияние числовых схем с фиксированной запятой на этот параметр. Результаты показывают достижение низких значений SNR для успешного декодирования за счет сверхдлинной длины кода и низкой скорости кодирования. Представленная архитектура декодера обладает хорошей производительностью при отношении сигнал/шум (SNR), достигающем -0,6 дБ the decoder architecture is presented, which is characterized by high performance, low complexity and high speed for ultra-long quasi-cyclic LDPC codes. The architecture and operation of an LDPC decoder implemented on an FPGA are described. Special attention is paid to the structure of reading and writing data in the process of iterative decoding, where a simple counter is used to address PCM memory (Phase Change Materials, phase transition materials), and parallel I/O is controlled by a lookup table. The mechanism of reading and writing is considered in detail, with an emphasis on their reordering before processing in NPU (Node Processing Units). A decision-making module is described that checks the success of decoding by comparing the calculated syndrome with the received one, as well as a module that generates output bits based on signed ones. Simulation results are presented demonstrating decoder performance through bit error (BER) parameters, average number of iterations, bandwidth and resource consumption. It is shown that the performance of the sum-product algorithm (SPA) is superior to that of the minimum sum algorithm (MSA), although MSA has less complexity. The dependence of the average number of iterations on the signal-to-noise ratio (SNR) is noted, as well as the insignificant influence of fixed-point numerical schemes on this parameter. The results show the achievement of low SNR values for successful decoding due to the extremely long code length and low encoding speed. The presented decoder architecture has good performance with a signal-to-noise ratio (SNR) reaching -0.6 dB

This paper presents a reconfigurable ADC that converts more than one analog signal into digital output bits with reconfigurable resolution. The proposed reconfigurable ADC uses successive approximation register technique (SAR) that provides low power consumption and small chip area. The proposed technique is applied on multiplexed sensor fusion that has many applications in biosensors, automotive sensors and sensors of weather stations. The main idea of this work is to apply the reconfigurability concept of a SAR ADC. The advantage of this design is converting three analog signals (as a case study) to 4, 8 and 12 digital output bits by using only one modular reconfigurable ADC. By applying the reconfigurability concept we can save area and power consumption. This idea is achieved by enabling and disabling of one or more stages of the ADC according to the required analog signal to be converted. In this paper three analog signals used in a weather station are converted into digital output as a case study. These signals are temperature, pressure and humidity and are sensed using BME-280 Bosch sensor. The proposed ADC uses the coarse-fine conversion technique for its high accuracy and low power consumption. Simulation is carried out using Cadence Virtuoso with hardware-calibrated TSMC 65 nm CMOS technology. All metrics of the ADC are measured such as ENOB, SNR, Power consumption, INL, DNL, FOM and Chip area for each reconfigured number of bits (4, 8, and 12-bits in this case study) using a supply voltage of 1.0 V and a sampling frequency of 100 kHz. The 12-bit resolution consumes 6.13 µW, ENOB is 11.13 bits, SNR equals 70.74 dB, SFDR equals 73.22 dB and FOM 0.45 fJ. mm2/conversion. The 8-bit resolution consumes 4.95 µW, ENOB is 7.37 bits, SNR equals 48.10 dB, SFDR equals 56.92 dB and FOM 5.72 fJ.mm2/conversion. The 4-bit resolution consumes 1.91 µW, ENOB is 3.67 bits, SNR equals 23.78 dB, SFDR equals 30.25 dB and FOM 29.03 fJ.mm2/conversion. The total chip area is 0.02 mm2. It has been shown that the proposed reconfigurable ADC can be used with different sensors with different resolutions given its modular architecture using the coarse-fine methodology.

This paper presents a reconfigurable ADC that converts more than one analogue signal into digital output bits with reconfigurable resolution. The proposed reconfigurable ADC uses successive approximation register technique (SAR) that provides low power consumption and small chip area. The proposed technique is applied on multiplexed sensor fusion that has many applications in biosensors, automotive sensors and sensors of weather stations. The main idea of this work is to apply the reconfigurability concept of a SAR ADC. The advantage of this design is converting three analogue signals (as a case study) to 4, 8 and 12 digital output bits by using only one modular reconfigurable ADC. By applying the reconfigurability concept we can save area and power consumption. This idea is achieved by enabling and disabling of one or more stages of the ADC according to the required analogue signal to be converted. In this paper three analogue signals used in a weather station are converted into digital output as a case study. These signals are temperature, pressure and humidity and are sensed using BME-280 Bosch sensor. The proposed ADC uses the coarse-fine conversion technique for its high accuracy and low power consumption. Simulation is carried out using Cadence Virtuoso with hardware-calibrated TSMC 65 nm CMOS technology. All metrics of the ADC are measured such as ENOB, SNR, Power consumption, INL, DNL, FOM and Chip area for each reconfigured number of bits (4, 8 and 12-bits in this case study) using a supply voltage of 1.0 V and a sampling frequency of 100 kHz. The 12-bit resolution consumes 6.13 µW, ENOB is 11.13 bits, SNR equals 70.74 dB, SFDR equals 73.22 dB and FOM 0.45 fJ. mm2/conversion. The 8-bit resolution consumes 4.95 µW, ENOB is 7.37 bits, SNR equals 48.10 dB, SFDR equals 56.92 dB and FOM 5.72 fJ.mm2/conversion. The 4-bit resolution consumes 1.91 µW, ENOB is 3.67 bits, SNR equals 23.78 dB, SFDR equals 30.25 dB and FOM 29.03 fJ.mm2/conversion. The total chip area is 0.02 mm2. It has been shown that the proposed reconfigurable ADC can be used with different sensors with different resolutions given its modular architecture using the coarse-fine methodology.

Many leading technology companies currently offer Machine Learning as a Service Platform, enabling developers and organizations to access the inference capabilities of pre-trained models via API calls. However, due to concerns over user data privacy, inter-enterprise competition, and legal and regulatory constraints, directly utilizing pre-trained models in the cloud for inference faces security challenges. In this paper, we propose communication-efficient secure three-party protocols for recurrent neural network (RNN) inference. First, we design novel three-party secret-sharing protocols for digit decomposition, B2A conversion, enabling efficient transformation of secret shares between Boolean and arithmetic rings. Then, we propose the lookup table-based secure three-party protocol. Unlike the intuitive way of directly looking up tables to obtain results, we compute the results by utilizing the inherent mathematical properties of binary lookup tables, and the communication complexity of the lookup table protocol is only related to the output bit width. We also design secure three-party protocols for key functions in the RNN, including matrix multiplication, sigmoid function, and Tanh function. Our protocol divides the computation into online and offline phase, and places most of the computations locally. The theoretical analysis shows that the communication round of our work was reduced from four rounds to one round. The experiment results show that compared with the current SOTA-SIRNN, the online communication overhead of sigmoid and tanh functions decreased by 80.39% and 79.94%, respectively.

The generation of pseudorandom binary sequences is of great importance in numerous applications, ranging from simulation and gambling to cryptography. Pseudorandom bit generators (PRBGs) can be divided into two categories based on their claimed security. The first category includes PRBGs that are provably secure, such as the Blum–Blum–Shub generator. The security of the second category relies on heuristic arguments. Unfortunately, PRBGs from the first category are inherently inefficient, and some are vulnerable to quantum attacks. In contrast, those in the second category are highly efficient, though their security depends on their resistance to known cryptographic attacks. This work presents a construction of a PRBG based on the asymmetric numeral system (ANS) compression algorithm. We define a family of PRBGs for 2R ANS states and prove that it is indistinguishable from a truly random generator for sufficiently large R. To enhance efficiency, we explore PRBGs with smaller values of R=7,8,9 and demonstrate methods for removing local correlations in the output stream. We permute output bits using rotation and Keccak transformations, showing that the permuted bits pass all NIST tests. Our PRBG design is provably secure for large values of R and heuristically secure for smaller values. Additionally, we claim that our PRBG is secure against quantum adversaries.

Pseudo‐random number generator (PRNG) is a type of algorithm that generates a sequence of random numbers using a mathematical formula, which is widely used in computer science, such as simulation, modeling applications, data encryption, et cetera. The efficiency and security of PRNG are closely related to its output bits at each iteration. Especially, we have recently found that linear congruential generator (LCG) is commonly used as the underlying PRNG in short message service (SMS) app, fast knapsack generator (FKG), and programming languages such as Python, while the quadratic generator plays an important role in Monte Carlo method. Therefore, in this paper, we revisit the security of these two number‐theoretic pseudo‐random generators and obtain the best results for attacking these two kinds of PRNGs up to now. More precisely, we prove that when the mapping function of LCG and the quadratic generator is unknown, if during each iteration, generators only output the most significant bits of vi, one can also recover the seed of PRNG when enough consecutive or nonconsecutive outputs are obtained. The primary tool of our attack is the Coppersmith method which can find small roots on polynomial equations. Our advantage lies in applying the local linearization technique to the polynomial equations to make them simple and easy to solve and applying the analytic combinatorics method to simplify the calculation of solution conditions in the Coppersmith method. Experimental data validate the effectiveness of our work.

The paper presents a method for extracting provably random bit sequences from several independent trajectories of circuits Markov, each of which has an arbitrary finite order. The combined use of several trajectories makes it possible in practice, when implementing quantum randomnumber generators, to significantly increase the speed of generating output bit sequences.

This paper presents an analysis of random distortions in the elements of the basic cell for an analog-digital pipelined converter. Pipelined converters are popular for their high sampling rates and resolution ranges. Each basic cell has a few-bit digital-analog converter connected to its output with a digital-to-analog converter to compare the input signal. This study aims to analyze the effects of random variations in the converters' elements. The proposed system is designed, with experiments conducted to observe the effects of distortions. The results of simulated architecture and distortion tests are presented, and the reached conclusions are presented in the fourth section. The basic cell used to build the converter is described in Equation 1, which describes the cell's operation. Six cells cascade-connected were used to construct the converter, with the input of the first block being the input and its output connected to the input of the second station. The true output of the converter is constructed by each of the output bits of each cell, with the bit of the first station being the most significant bit until reaching the output bit in the last cell.

In this paper, we propose a method to enhance the performance of a random number generator (RNG) that exploits ring oscillators (ROs). Our approach employs additional phase detectors to extract more entropy; thus, RNG uses fewer resources to produce bit sequences that pass all statistical tests proposed by National Institute of Standards and Technology (NIST). Generating a specified number of bits is on-demand, eliminating the need for continuous RNG operation. This feature enhances the security of the produced sequences, as eavesdroppers are unable to observe the continuous random bit generation process, such as through monitoring power lines. Furthermore, our research demonstrates that the proposed RNG's perfect properties remain unaffected by the manufacturer of the field-programmable gate arrays (FPGAs) used for implementation. This independence ensures the RNG's reliability and consistency across various FPGA manufacturers. Additionally, we highlight that the tests recommended by the NIST may prove insufficient in assessing the randomness of the output bit streams produced by RO-based RNGs.

In cryptography, techniques and tools developed in the subfield of linear cryptanalysis have previously successfully been used to allow attackers to break many sophisticated cryptographic ciphers. Since these linear cryptanalytic techniques require exploitable linear approximations to relate the input and output of vectorial Boolean functions, e.g., the plaintext, ciphertext, and key of the cryptographic function, finding these approximations is essential. For this purpose, the Correlation Extraction Algorithm (CEA), which leverages the emerging field of quantum computing, appears promising. However, there has been no comprehensive analysis of the CEA regarding finding an exploitable linear approximation for linear cryptanalysis. In this paper, we conduct a thorough theoretical analysis of the CEA. We aim to investigate its potential in finding a linear approximation with prescribed statistical characteristics. To support our theoretical work, we also present the results of a small empirical study based on a computer simulation. The analysis in this paper shows that an approach that uses the CEA to find exploitable linear approximations has an asymptotic advantage, reducing a linear factor to a logarithmic one in terms of time complexity, and an exponential advantage in terms of space complexity compared to a classical approach that uses the fast Walsh transform. Furthermore, we show that in specific scenarios, CEA can exponentially reduce the search space for exploitable linear approximations in terms of the number of input bits of the cipher. Neglecting the unresolved issue of efficiently checking the property of linear approximations measured by the CEA, our results indicate that the CEA can support the linear cryptanalysis of vectorial Boolean functions with relatively few (e.g., n≤32) output bits.

<span>Multiple-input multiple-output (MIMO) and orthogonal frequency division multiplexing (OFDM) are widely utilized in wireless systems and maximum data rate communications. The MIMO-OFDM technology increases the efficiency of spectrum utilization. The peak-to-average-power ratio (PAPR) minimization in MIMO-OFDM is a complex task in wireless communications systems. In this research, an adaptive tunicate swarm optimization with partial transmit sequence (ATSO-PTS) algorithm is proposed for a reduction of PAPR in MIMO-OFDM. The nonsquare-matrix-based differential space time coding (N-DSTC) scheme is used for the encoding and decoding process of MIMO-OFDM. The N-DSTC encoding and decoding are linear error-correcting codes that are utilized for message transmission over noisy channels. The pre-specified quadrate phase shift keying (QPSK) symbol is deployed for the modulation and demodulation scheme. On the receiver side, the serial to parallel (S/P) conversion, and fast Fourier transform (FFT) are accomplished, alongside the received data bits being demodulated to obtain the output bits. The proposed ATSO-PTS method achieves better results according to performance metrices PAPR, bit error rate (BER) and signal-to-noise-ratio (SNR), with values of about 2.9, 0.01 and 0.025, respectively. This ensures superior results when compared to the existing methods of twin symbol hybrid optimization applied to partial transmit sequence (TSHO-PTS), selective level mapping and PTS (SLM-PTS), and particle swarm and grey wolf (PS-GW) with PTS, respectively.</span>

This research plans a random number generation method using the Linear Feedback Shift Register (LFSR) method with the A5/1 scheme which involves three feedback functions. XOR is used to determine the new output bit value in the next iteration in the feedback mechanism. The test material produces random output for an input using Run Test, Mono Bit, and Block bit. Tests using three feedback functions were carried out to compare with previous research which generated random numbers. Testing of plaintext and ciphertext encryption shows a very small level of correlation with an average value close to 0. The use of LFSR with the A5/1 scheme which involves three XOR functions, creates random output and can be used against Stream Chipers.

Existing research shows that asynchronous FIFO has been widely used in a variety of complex system designs, such as FPGA-based image processing systems, USB communication systems, and so on. To make the designed asynchronous FIFO more programmable and flexible, so that it can adapt to various application scenarios more quickly, this paper studies and designs an asynchronous FIFO with adjustable input and output bit width. In this study, according to the relationship between 24-bit input data and 32-bit storage space, four 24-bit data are selected to fill three RAM storage spaces at one time. According to the multiple relationships between 32-bit storage space and 128-bit output data, the reading pointer is enlarged by 4 times to realize the function of reading four 32-bit data at one time. This whole process realizes the conversion of data bit width through data splicing. Finally, the 24-bit RGB888 image data is successfully converted into 128-bit data and transmitted to the bus, which successfully solves the problem of data width mismatch.

ABSTRACT This paper presents a jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is useful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL), and various time-based circuits whose performance is severely degraded by jitter accumulation, an inherent property of VCRO. In the proposed technique, a 1-bit time-to-digital converter (TDC) is used to extract information about jitter with a sensitivity of 4ps/bit. The rise in phase detector output bit leads VCRO to work in Progressive Phase Multi-Injection Locking (PPM-IL) mode until VCRO gets jitter-free. The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. After enabling the proposed technique, the RMS jitter reduces from 7.436 ps to 1.198ps for VCRO running at 63 MHz and consumes a total power of 1.112 mW.

Modular addition is often the most complex component of typical Addition- Rotation-XOR (ARX) ciphers, and the division property is the most effective tool for detecting integral distinguishers. Thus, having a precise division property model for modular addition is crucial in the search for integral distinguishers in ARX ciphers. Current division property models for modular addition either (a) express the operation as a Boolean circuit and apply standard propagation rules for basic operations (COPY, XOR, AND), or (b) treat it as a sequence of smaller functions with carry bits, modeling each function individually. Both approaches were originally proposed for the twosubset bit-based division property (2BDP), which is theoretically imprecise and may overlook some balanced bits.Recently, more precise versions of the division property, such as parity sets, threesubset bit-based division property without unknown subsets (3BDPwoU) or monomial prediction (MP), and algebraic transition matrices have been proposed. However, little attention has been given to modular addition within these precise models.The propagation rule for the precise division property of a vectorial Boolean function f requires that u can propagate to v if and only if the monomial πu(x) appears in πv(f). Braeken and Semaev (FSE 2005) studied the algebraic structure of modular addition and showed that for x ⊞ y = z, the monomial πu(x)πv(y) appears in πw(z) if and only if u + v = w. Their theorem directly leads to a precise division property model for modular addition. Surprisingly, this model has not been applied in division property searches, to the best of our knowledge.In this paper, we apply Braeken and Semaev’s theorem to search for integral distinguishers in ARX ciphers, leading to several new results. First, we improve the state-of-the-art integral distinguishers for all variants of the Speck family, significantly enhancing search efficiency for Speck-32/48/64/96 and detecting new integral distinguishers for Speck-48/64/96/128. Second, we determine the exact degrees of output bits for 7-round Speck-32 and all/16/2 output bits for 2/3/4-round Alzette for the first time. Third, we revisit the choice of rotation parameters in Speck instances, providing a criterion that enhances resistance against integral distinguishers. Additionally, we offer a simpler proof for Braeken and Semaev’s theorem using monomial prediction, demonstrating the potential of division property methods in the study of Boolean functions.We hope that the proposed methods will be valuable in the future design of ARX ciphers.

Considering that cryptographic algorithms are among the most reliable methods for protecting information in information systems, assessing their cryptographic strength plays a significant role. For this purpose, comprehensive studies are conducted, and one of the primary characteristics of such an assessment is the statistical security of the obtained ciphertexts. This article investigates the statistical security of the block cipher algorithm AL04, developed in the Information Security Laboratory. The algorithm was implemented in software, and the resulting ciphertexts were analyzed using the test sets of D. Knuth and NIST, as well as checked against the avalanche effect criterion (average number of output bits, degree of completeness, degree of avalanche effect, degree of strict avalanche criterion). The statistical tests used are the main tests in the works of many researchers and determine the properties of sequence randomness with high accuracy. The study found that AL04 does not have deviations in the sequences obtained using the algorithm. Thus, it was established that the algorithm possesses high statistical security.