Order Continuous-time Sigma-delta Research Articles

A Review on Higher Order Continuous-Time Sigma-Delta Modulators for ADC Design

Abstract—In this paper, the concept of adaptive filtering has been proposed. It has been shown that signals often undergo variation in the noise environment encountered. Hence it becomes mandatory to design filters based on noise shaping and adaptive noise cancellation. Such filters are called adaptive filters and are used for applications requiring real time noise cancellation such as speech processing, live video broadcasting etc. The paper presents the structure of Sigma Delta or MASH ADCs which employ recursive encoding. SDM ADCs are also used to convert high bit-count, low- frequency digital signals into lower bit-count, higher-frequency digital signals as part of the process to convert digital signals into analog as part of a digital-to-analog converter (DAC). The paper focuses on the various approaches used thus far for the purpose, citing the pros and cons of each approach. Keywords— Adaptive Filter Design, Noise Filtering, Sigma Delta Modulator (SDM), MASH, Signal to Noise Ratio.

Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD

This paper presents a step-by-step design approach of a 3rd order continuous-time sigma-delta modulator with a 4-tap FIR feedback DAC achieving 107 dB DR (A-weighted), −110 dB THD and an SNDR of 101.8 dB. The THD is achieved through a fully differential feed-forward compensated op-amp that maintains high linearity with the aid of a class AB output stage and an optimum bias current through a CMFB loop. The modulator consumes 322.5uW of power while taking an area of 0.2925 mm2.

A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp

This paper proposes a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order continuous-time delta-sigma modulator (CTDSM) with a single amplifier biquad (SAB) and excess loop delay (ELD) merged integrator. The integrator enables a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order noise-shaping together with ELD compensation with just a single Opamp and feedback DAC. A three-stage Opamp with a hybrid frequency-compensation scheme is presented, which achieves high gain and large unity-gain bandwidth (UGBW) with low power. The circuit secures an extra order noise-shaping through a passive noise-shaping SAR (NS-SAR) quantizer (QTZ) while further incorporating a preliminary sampling and quantization (PSQ) technique, the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> order NS QTZ can run at 1.5 GHz with 6b. The design, implemented in 28 nm, obtains 74.4 dB SNDR with 50 MHz bandwidth while consuming 10.4 mW from 1.5 V and 1 V power supplies. The prototype attains a dynamic range of 80.6 dB with a Schreier FOM of 171.2 dB. With the presented integrator and Opamp, the loop filter only consumes 14 % of the total DSM power consumption.

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy

A CMOS gas sensor array platform with digital read-out containing 27 sensor pixels and a reference pixel is presented. A signal conditioning circuit at each pixel includes digitally programmable gain stages for sensor signal amplification followed by a second order continuous time delta sigma modulator for digitization. Each sensor pixel can be functionalized with a distinct sensing material that facilitates transduction based on impedance change. Impedance spectrum (up to 10 KHz) of the sensor is obtained off-chip by computing the fast Fourier transform of sensor and reference pixel outputs. The reference pixel also compensates for the phase shift introduced by the signal processing circuits. The chip also contains a temperature sensor with digital readout for ambient temperature measurement. A sensor pixel is functionalized with polycarbazole conducting polymer for sensing volatile organic gases and measurement results are presented. The chip is fabricated in a 0.35 μm CMOS technology and requires a single step post processing for functionalization. It consumes 57 mW from a 3.3 V supply.