Phase Change Memory Operation Research Articles

Subthreshold read operations in 3D PCM: 1S1R device modeling and memory array analysis

3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (VBL-max), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (σvar), and bias voltages (VBias). Our results reveal that the RWM increases as the VBL approaches the VBL-max. Larger arrays lead to an increased leakage current difference, while larger σvar values result in decreased cell current difference and VBL-max. The decrease in VBL-max further deteriorates the RWM. Additionally, we analyze the optimal VBias for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal VBias depends on OTS devices and array sizes.

Implementation of a new coding scheme for improving the SET operations in Phase Change Memory (PCM)

Among Non-Volatile Memories (NVMs), PCMs are considered the best alternative to DRAM (dynamic random-access memories). As a result of its superior performance and scalability, there are several advantages over DRAM, including lower leakage and energy consumption, higher cell number, and smaller cells. This kind of memory does, however, suffer from a long write latency. In this article, we present a technique to reduce write latency by reducing the number of SET operations. The proposed method is an improved Write Time Speed-up (WTS) code scheme. In the proposed scheme, a new code based on hamming weight is given, and an appropriate algorithm is written to reduce the number of SET operations. Compared with current methods, the proposed scheme decreased SET and RESET operations by 3.9 percent, SET operations by 3.3 percent, and power consumption by 2.6 percent. Visual Basic 6 and GEM 5 simulations are used to simulate the suggested method

Spatially inhomogeneous operation of phase-change memory

Rapid changes in the electrical resistance depending on the phases (amorphous and crystal) are one of the most promising bases for universal memory. Phase-change region is spatially inhomogeneous during memory operation in a unit cell because Joule heat for the phase-change is generated at the interface between the metal and compounds. However, delicate optimization of the electrical and thermal properties at the interface is underexplored compared to the bulk. In this study, we modulate the electrical and thermal conductivities by incorporating oxygen in Ag-In-Sb-Te, superior memory compounds where oxygen is chosen for high accessibility and efficiency for the modulation of conductivity. We further analyze the oxidation and crystallization process at the atomic level. Based on the results, we successfully improve the memory performances such as speed, energy, signal ratio, and reliability simultaneously by inserting the oxygenated layer as an interfacial layer. Our study proves that there is considerable room to optimize memory performance at the interface.

TA-CLOCK: Tendency-Aware Page Replacement Policy for Hybrid Main Memory in High-Performance Embedded Systems

Recently, high-performance embedded systems have adopted phase change memory (PCM) as their main memory because PCMs have attractive advantages, such as non-volatility, byte-addressability, high density, and low power consumption. However, PCMs have disadvantages, such as limited write endurance in each cell and high write latency compared to DRAMs. Therefore, researchers have investigated methods for enhancing the limitations of PCMs. In this paper, we propose a page replacement policy called tendency-aware CLOCK (TA-CLOCK) for the hybrid main memory of embedded systems. To improve the limited write endurance of PCMs, TA-CLOCK classifies the page access tendency of the victim page through access pattern analysis and determines the migration location of the victim page. Through the classification of the page access tendency, TA-CLOCK reduces unnecessary page migrations from DRAMs to PCMs. Unnecessary migrations cause an increase in write operations in PCMs and the energy consumption of the hybrid main memory in embedded systems. Thus, our proposed policy improves the limited write endurance of PCMs and enhances the access latency of the hybrid main memory of embedded systems by classifying the page access tendency. We compared the TA-CLOCK with existing page replacement policies to evaluate its performance. In our experiments, TA-CLOCK reduced the number of write operations in PCMs by 71.5% on average, and it enhanced the energy delay product by 38.3% on average compared with other page replacement policies.

Thermal conductivity of amorphous and crystalline GeTe thin film at high temperature: Experimental and theoretical study

Thermal transport properties bear a pivotal role in influencing the performance of phase change memory (PCM) devices, in which the PCM operation involves fast and reversible phase change between amorphous and crystalline phases. In this paper, we present a systematic experimental and theoretical study on the thermal conductivity of GeTe at high temperatures involving fast change from amorphous to crystalline phase upon heating. Modulated photothermal radiometry (MPTR) is used to experimentally determine thermal conductivity of GeTe at high temperatures in both amorphous and crystalline phases. Thermal boundary resistances are accurately taken into account for experimental consideration. To develop a concrete understanding of the underlying physical mechanism, rigorous and in-depth theoretical exercises are carried out. For this, first-principles density functional methods and linearized Boltzmann transport equations (LBTE) are employed using both direct and relaxation time based approach (RTA) and compared with that of the phenomenological Slack model. The amorphous phase experimental data has been described using the minimal thermal conductivity model with sufficient precision. The theoretical estimation involving direct solution and RTA method are found to retrieve well the trend of the experimental thermal conductivity for crystalline GeTe at high temperatures despite being slightly overestimated and underestimated, respectively, compared to the experimental data. A rough estimate of vacancy contribution has been found to modify the direct solution in such a way that it agrees excellently with the experiment. Umklapp scattering has been determined as the significant phonon-phonon scattering process. Umklapp scattering parameter has been identified for GeTe for the whole temperature range which can uniquely determine and compare Umklapp scattering processes for different materials

PRO: A periodical reset optimized page migration scheme for hybrid memory system

Due to its attractive characteristics, phase change memory (PCM) has emerged as a promising candidate to be used in main memory of embedded systems in the future. However, the write endurance problem has restricted its application in practical. Discussions regarding on hybrid memory page replacement mechanism have dominated research in recent years. Most existing schemes lack the detection for the locality regulations of memory access and do not take migration efficiency into consideration. In this paper, we rethink data access features and conduct further research on inter-reference distance to exploit the locality regulations of workloads in embedded systems. Then, propose a novel page migration scheme, Periodical Reset Optimized Page Migration Scheme (PRO), which is a hardware-software coordination algorithm. PRO largely reduces the number of write operations in PCM with limited swap operations. Meanwhile, it reduces the write operations by an average of 88.75% and decreases the average access time by an average 11.47% compared with the typical migration schemes.

Atomistic Simulations of Phase Change Materials for Electronic Memories

We review our results on large-scale atomistic simulations of the phase change compound GeTe of interest for applications in nonvolatile electronic memories. The simulations are based on an interatomic potential with an accuracy close to that of the density functional theory (DFT). The potential was generated by fitting a DFT database by means of an artificial neural network method. This methodological advance allowed us to perform molecular dynamics simulations with several thousand atoms for several ns that provided useful insights on several properties of interest for the operation of phase change memories, including the crystallization kinetics, the dynamics of the supercooled liquid, the structural relaxation in the glass and the properties of nanowires.

DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance

A major challenge for the widespread adoption of phase change memory (PCM) as main memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation (i.e., an operation that writes “1”) is 2–5 times longer than the latency of a RESET operation (i.e., an operation that writes “0”). For this reason, the average write latency of a PCM system is limited by the high-latency SET operations. This paper presents a novel PCM architecture called DyPhase , which uses partial-SET operations instead of the conventional SET operations to introduce a symmetry in write latency, thereby increasing write performance and throughput. However, use of partial-SET decreases data retention time. As a remedy to this problem, DyPhase employs novel distributed refresh operations in PCM that leverage the available power budget to periodically rewrite the stored data with minimal performance overhead. Unfortunately, the use of periodic refresh operations increases the write rate of the memory, which in turn accelerates memory degradation and decreases its lifetime. DyPhase overcomes this shortcoming by utilizing a proactive in-situ self-annealing (PISA) technique that periodically heals degraded memory cells, resulting in decelerated degradation and increased memory lifetime. Experiments with PARSEC benchmarks indicate that our DyPhase architecture-based hybrid dynamic random access memory (DRAM)–PCM memory system, when enabled with PISA, yields orders of magnitude higher lifetime, 8.3% less CPI, and 44.3% less EDP on average over other hybrid DRAM–PCM memory systems that utilize PCM architectures from prior works.

Investigation of bias polarity dependence of set operation in GeCu 2 Te 3 phase change memory

We measured the impact of the thermoelectric effect, especially the Peltier effect, upon the operation of phase change memory (PCM) in which the contact resistance between the phase change material and the electrode dominates the total resistance. A PCM device having a pillar structure of diameter 500 nm was fabricated using GeCu2Te3 (GCT) material. During read operation, the set state (with crystalline PCM) showed ohmic contact between the PCM and the electrode, whereas the reset state (with amorphous PCM) showed Schottky contact. The Schottky contact between the amorphous GCT and the electrode showed a bias polarity dependence of set operation owing to the Peltier effect, which is one of the thermoelectric effects. As PCM devices scale down to the nanometre scale, research on contact resistance and various related effects will become more important.

Adaptive-Classification CLOCK: Page replacement policy based on read/write access pattern for hybrid DRAM and PCM main memory

Phase change memory (PCM) has emerged as a new main memory in embedded systems because of its attractive characteristics, which include a lower static power, higher density, byte-addressability, and non-volatility. Although PCM has various advantages, it has a longer write latency than dynamic random access memory (DRAM) and limits the write endurance in each cell. Recently, a hybrid main memory was designed that combined DRAM and PCM. In particular, the page replacement policy in this hybrid main memory has been one of the major areas of study. The previous page replacement policies had three problems when used in embedded systems: the allocation policy, read/write access pattern identification, and migration policy. This paper proposes the adaptive-classification CLOCK (AC-CLOCK) page replacement policy for the hybrid main memory of an embedded system. AC-CLOCK measures the read/write access patterns of application programs and reduces the number of write operations in PCM by tracing these patterns. In addition, it reduces the number of unnecessary page migrations from PCM to DRAM by tracking the detailed access patterns such as write intensive pages or read intensive pages. In our experiments, AC-CLOCK reduced the number of write operations in PCM by 57.87% on average and outperformed the hit ratio of write operations in the DRAM by 9.47% on average, compared with CLOCK, CLOCK-Pro, and CLOCK-DWF. Moreover, AC-CLOCK reduced the energy delay product (EDP) by 23.25% on average, compared with the previous techniques.

Set/reset reference and parasitic matching scheme to speed up PCM read operation

Three kinds of parameters are considered to speed up the read operation of phase change memory: bit line parasitic parameters, read transmission gate parasitic parameters and current mirror parasitic parameters. A set reference cell and a reset reference cell are used in the reference circuit. Simulated in 130 nm process, the read access time of 1-Mb phase change memory (PCM) is 6.7 ns. In Monte Carlo simulations, the worst read access time is 13.8 ns compared to conventional 85 ns.

Odd/Even Invert coding for phase change memory with thermal crosstalk

Cloud based services demand a colossal amount of memory in order to satisfy their objectives. Phase-change memory (PCM) has emerged as one of the most promising memory technologies to feature in next generation memory systems. One of the key challenges of PCM is the limited number of writes that can be performed on memory cells also known as “write endurance”. In this paper we present a cost model which captures the asymmetry as well as disturb characteristics associated with write operations in PCMs. Moreover, we present an encoding architecture based on the proposed cost metric to allow the write operation to be performed using minimum cost. The proposed approach called “Odd/Even Invert” re-codes data based on selective inversion of even and/or odd bits to find minimum cost write operation that shall enhance cells lifetime. The proposed approach inquires a cost of only two extra bits regardless of the size of data word used, hence provides a cost effective approach to the problem. Experimental results and comparison with existing techniques on random data, real data, and memory traces from PERSEC benchmark suite, show the effectiveness and scalability of the proposed scheme.

Bipolar switching in chalcogenide phase change memory.

Phase change materials based on chalcogenides are key enabling technologies for optical storage, such as rewritable CD and DVD, and recently also electrical nonvolatile memory, named phase change memory (PCM). In a PCM, the amorphous or crystalline phase affects the material band structure, hence the device resistance. Although phase transformation is extremely fast and repeatable, the amorphous phase suffers structural relaxation and crystallization at relatively low temperatures, which may affect the temperature stability of PCM state. To improve the time/temperature stability of the PCM, novel operation modes of the device should be identified. Here, we present bipolar switching operation of PCM, which is interpreted by ion migration in the solid state induced by elevated temperature and electric field similar to the bipolar switching in metal oxides. The temperature stability of the high resistance state is demonstrated and explained based on the local depletion of chemical species from the electrode region.

Flexible one diode-one phase change memory array enabled by block copolymer self-assembly.

Flexible memory is the fundamental component for data processing, storage, and radio frequency communication in flexible electronic systems. Among several emerging memory technologies, phase-change random-access memory (PRAM) is one of the strongest candidate for next-generation nonvolatile memories due to its remarkable merits of large cycling endurance, high speed, and excellent scalability. Although there are a few approaches for flexible phase-change memory (PCM), high reset current is the biggest obstacle for the practical operation of flexible PCM devices. In this paper, we report a flexible PCM realized by incorporating nanoinsulators derived from a Si-containing block copolymer (BCP) to significantly lower the operating current of the flexible memory formed on plastic substrate. The reduction of thermal stress by BCP nanostructures enables the reliable operation of flexible PCM devices integrated with ultrathin flexible diodes during more than 100 switching cycles and 1000 bending cycles.

Effect of Tilted Angle in Trench Structure on Phase Change Memory Operation Using TCAD Simulation

As the devices have faced limit of shrinking, a lot of candidates rise to lead the next generation of device technology. One of the well-known candidates is a phase change memory (PCM) which is based on a chalcogenide material, called Ge2Sb2Te5 (GST). Principle of PCM operation is decided by changing the phase of GST thermodynamically. Thus, structures of PCM cell such as keyhole and μ-trench are mainly used for Joule heating. However, in the process of making a trench, it has inevitably difference between top and bottom aperture of the trench, and affects electrical properties of PCM. In this study, we build a PCM cell structure using technology computer-aided design (TCAD) and analyze effect of tilted angle of trench on phase change memory operation.

Effect of Trench Depth Variation on Phase Change Memory Operation using Tcad

As one of non-volatile memory devices, the flash memory is widely used in various areas of applications, especially for mobile application. However, it has problems such as physical nano-scale limitation and reliability. Thus, researchers investigated next-generation memory device candidates which can overcome these problems. The phase change memory (PCM) is one of the attractive next-generation non-volatile memory candidates. As a phase change memory device, both keyhole and μ-trench structures are widely used. Thus, it is crucial to examine the electrical characteristic variation by structure modification. So, in this paper, we analyze the electrical effect of upper side trench depth variation on phase change memory operation.

Te-based chalcogenide films with high thermal stability for phase change memory

This study reports on the synthesis of tellurium-based chalcogenide films that have high thermal stability for phase change memory application. Several Te-based chalcogenide alloys of In-Bi-Te, Ag-Bi-Te, In-Sb-Te, Sn-Sb-Te, Zn-Ge-Te, and Ga-Ge-Te are reported. Their thermal, optical, and electrical properties are investigated. The results show that Bi-Te-based films have a higher crystallization temperature and greater activation energy compared with the other Sb-Te-based and Ge-Te-based films. Especially, In2.8Bi36.6Te60.6 film exhibits high crystallization temperature (252 °C) and great activation energy (5.16 eV), showing much improved amorphous thermal stability. A relatively wider optical band gap (0.674 eV) of thermal annealed In2.8Bi36.6Te60.6 film is obtained. In addition, it also has a higher amorphous/crystalline resistance ratio of about 105, implying that current consumption could be low in the phase-change memory operation.

Phase change materials

Abstract

Threshold voltage drift in phase change memories: scaling and modeling

ABSTRACTThe phase-change-memory (PCM) relies on the ability of a chalcogenide material, usually Ge2Sb2Te5 (GST), to switch from the amorphous phase with a high electrical resistance (~MΩ) to a crystalline phase with a low electrical resistance (∼kΩ). The structural stability of the amorphous phase is critically affected by temperature-activated crystallization and resistance drift due to structural relaxation (SR) [1]. While amorphous chalcogenides are relatively stable with respect to crystallization, thanks to a high activation energy above 2 eV [2], the lower activation energy of SR can strongly affect the PCM electrical properties of the amorphous phase, including resistance, activation energy for conduction and, most importantly, the threshold voltage VT. The latter marks the boundary between read and programming operations in PCM, thus VT instability must be carefully predicted to minimize read disturbs within the array. To this purpose, understanding the switching mechanisms and modeling of VT is of utmost importance for PCM device development and scaling.

In Situ Transmission Electron Microscopy Observation of Nanostructural Changes in Phase-Change Memory

Phase-change memory (PCM) has been researched extensively as a promising alternative to flash memory. Important studies have focused on its scalability, switching speed, endurance, and new materials. Still, reliability issues and inconsistent switching in PCM devices motivate the need to further study its fundamental properties. However, many investigations treat PCM cells as black boxes; nanostructural changes inside the devices remain hidden. Here, using in situ transmission electron microscopy, we observe real-time nanostructural changes in lateral Ge(2)Sb(2)Te(5) (GST) PCM bridges during switching. We find that PCM devices with similar resistances can exhibit distinct threshold switching behaviors due to the different initial distribution of nanocrystalline and amorphous domains, explaining variability of switching behaviors of PCM cells in the literature. Our findings show a direct correlation between nanostructure and switching behavior, providing important guidelines in the design and operation of future PCM devices with improved endurance and lower variability.