One-time Programmable Research Articles

Origin of Initial Rapid Cell Current Reduction in Non-Volatile One-Time Programming Memory

The fast bit cell current (BCC) reduction in a one-time programming (OTP) device during high-temperature annealing will severely decrease the data retention (DR) capability. It is found that negative bias temperature instability-like degradation is responsible for this fast BCC shift, which is different from the well-known DR mechanism. The rapid floating gate charge diminution at the initial stage can be attributed to the recombination by hydrogen species as a result of the depassivation of Si–H bonds at the Si/SiO2 interface. Our experiments show that the BCC reduction rate follows a power-law time dependence $t^{-0.73}$ , which is in agreement with a simple analytical model based on interface state ( $N_{{\mathrm{it}}}$ ) generation and floating-gate voltage shift. These observations pave the way for further OTP DR reliability improvement.

High-Density FinFET One-Time Programmable Memory Cell With Intra-Fin-Cell-Isolation Technology

The one-time programmable (OTP) cell with intra-Fin-cell-isolation (IFCI) on the FinFET high-k metal gate (HKMG) CMOS process is proposed and demonstrated. The field-enhanced dielectric breakdown at Fin corners enables this OTP cell to be operated at low program voltage with fast program speed. The new intra-Fin cell-to-cell isolation eliminates the required wide spacing in the conventional isolation schemes, which successfully shields the neighboring cells from program and read disturbs. Without introducing extra masks or process steps, the CMOS compatible IFCI OTP cell achieves an ultrasmall cell size of 0.076 $\mu \text{m}^{2}$ . More than six orders of ON-/OFF-read window is achieved under 4 V programming within 20 $\mu \text{s}$ .

Reliable Antifuse One-Time-Programmable Scheme With Charge Pump for Postpackage Repair of DRAM

A reliable antifuse (AF) one-time-programmable (OTP) cell and its sensing plus programming circuits for postpackage repair of dynamic random access memory (DRAM) are presented. The OTP cell was fabricated without any process modifications by utilizing destructive breakdown of thin gate oxide of nMOS capacitor as storage. The measurement results of OTP array fabricated by 0.13- $\mu $ m CMOS process show a tight read current distribution after programming. For pin compatibility with standard DRAM specifications, an internal charge pump is designed to provide high program voltage without any additional pin. Based on the AF cells, a programmable decoder is proposed to store the address of failed bit, decode the input address, and decide whether to access normal bit or redundant one of DRAM. The whole bit-repair scheme uses static latches as redundant cells. By avoiding the uses of address comparator and multiplexer, the proposed scheme shows less access penalty compared with prior scheme.

PMIC용 저면적 Dual Port eFuse OTP 메모리 IP 설계

In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to and due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is (), which is confirmed to be a small-area implementation.

Silicon Carbide (SiC) Nanoelectromechanical Antifuse for Ultralow-Power One-Time-Programmable (OTP) FPGA Interconnects

We report a new nanoscale antifuse featuring low-power and high-programming speed, by employing silicon carbide (SiC) nanoelectromechanical systems (NEMS). We show that the SiC NEMS antifuses can enable ultralow-power one-time-programmable (OTP) field-programmable gate arrays (FPGAs) with characteristics promising for security-sensitive and harsh-environment applications. The SiC NEMS antifuses offer minimal leakage, low-programming voltage (down to $\sim 1.5$ V), ideally abrupt transient, high on/off ratios ( $>10^{7}$ ) and high-current carrying ability ( $>10^{6}$ A/cm $^{2}$ ), and very small footprints ( $\sim 1~\mu \text{m}^{2}$ to $\sim 0.1~\mu \text{m}^{2}$ per device). We further describe new designs of antifuses, simulate FPGA benchmarking circuits based on experimentally demonstrated practical NEMS antifuses, and compare their advantageous performance with state-of-the-art conventional antifuse FPGAs. We also demonstrate a SiC NEMS antifuse-based OTP memory cell with a read margin of $>10^{6}$ .

A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process

A new and compact high-k dielectric breakdown one-time programmable (OTP) cell in pure 28-nm high-k metal gate (HKMG) process is proposed. By adopting a self-aligned twin-gate isolation (TGI) made by merged gate spacer, the new OTP cell can operate independently with a very small cell area. Fabricated by a pure 28-nm HKMG CMOS logic process, this OTP cell successfully achieves an ultrasmall cell size of 0.0441 μm 2 on 28-nm HKMG CMOS logic platform. Using high-k dielectric breakdown as its program mechanism, the antifuse TGI OTP memory has more than three orders of ON/OFF read window with a low program voltage of 4 V in 20 μs. Furthermore, a highly density 64-kbit TGI OTP array has been fabricated and successfully demonstrates the new superior isolation and reliability performances.

A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory.

This work demonstrates a feasible single poly-Si gate-all-around (GAA) junctionless fin field-effect transistor (JL-FinFET) for use in one-time programming (OTP) nonvolatile memory (NVM) applications. The advantages of this device include the simplicity of its use and the ease with which it can be embedded in Si wafer, glass, and flexible substrates. This device exhibits excellent retention, with a memory window maintained 2 V after 104 s. By extrapolation, 95% of the original charge can be stored for 10 years. In the future, this device will be applied to multi-layer Si ICs in fully functional systems on panels, active-matrix liquid-crystal displays, and three-dimensional (3D) stacked flash memory.

A Fully Integrated EPC Gen-2 UHF-Band Passive Tag IC Using an Efficient Power Management Technique

We present a system-on-chip passive tag integrated circuit (IC) for secure near-field RF identification applications. The design of the RF transceiver and the digital control of the tag IC are based on the EPCglobal ultrahigh-frequency Gen-2 protocol. A new design technique for the power management of the tag IC is presented, which includes a low-voltage bandgap, a low-dropout regulator with a bias-boosted gain stage, and an adaptive dc limiter. With the proposed design technique, we achieve a high power conversion efficiency of 47% at a low input power of -12 dBm. To support data security, we use one-time programmable (OTP) memory for nonvolatile data storage. The 4-kb (256 × 16 b) OTP memory array is based on a two-transistor (2-T) gate-oxide antifuse that can be programmed with a voltage of less than 6 V. The tag chip was fabricated in a 1-poly 6-metal standard 0.13- μm CMOS process. The power consumption levels of the tag IC are 29.2 and 71.2 μW for the read and programming modes, respectively. The size of the tag chip is 1.1×1 mm2.

A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications

A 4-kbit low-cost one-time programmable (OTP) memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor (1.5T) OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch (HVSW) circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification (RFID) tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm2. The 4-kbit OTP macro only consumes 200 × 260 μm2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.

A new 28 nm high-k metal gate CMOS logic one-time programmable memory cell

This work presents a high density high-k metal gate (HKMG) one-time programmable (OTP) cell. Without additional processes and steps, this OTP cell is fully compatible to 28 nm HKMG CMOS process. The OTP cell adopts high-k dielectric breakdown as programming mechanism to obtain more than 105 times of on/off read window. Moreover, it features low power and fast program speed by 4.5 V program voltage in 100 µs. In addition to the ultrasmall cell area of 0.0425 µm2, the superior performance of disturb immunities and data retention further support the new logic OTP cell to be a very promising solution in advanced logic non-volatile memory (NVM) applications.

One-Time Programmable Memory Based on ${\rm ZrTiO}_{x}$ Antifuse for Crossbar Memory Application Featuring High Speed Operation and Low Power Consumption

TaN/ZrTiOx/Pt metal-insulator-metal structure was employed as the platform to evaluate the eligibility for antifuse one-time programmable (OTP) memory applications, and the impact of O2 plasma on device performance was also discussed. Owing to the oxygen radicals that enhance the dielectric integrity, the voltage for state switching increases with O2 plasma treatment. Memory cells without plasma treatment demonstrate promising characteristics for OTP memory applications in terms of a low dc switching voltage of 2 V, high programming speed of 60 ns, high read endurance up to 106 reading cycles, and desirable retention time and low switching power density of 6.4 mW/cm2. The memory cell technology not only exhibits the prominent performance which is advantageous over other dielectrics reported in the literature, but it also possesses the capability to from stackable 3-D architecture.

Tantalum-Nitride Antifuse Electromechanical OTP for Embedded Memory Applications

Embedded nonvolatile memory (NVM) integrated in the back-end of line processes are of high interest, particularly for rugged environments (high temperature/radiation or vibration). This letter demonstrates the use of tantalum nitride microbeams as antifuse one-time programmable (OTP) NVM. It needs a single mask process and can be integrated above an integrated circuit. Typical fusing current is 1 mA, operating voltage is 4 V, and the measured contact resistance is <;2 kQ. A hybrid one-transistor/one microbeam/bit memory array is proposed for back-end compatible and low-cost OTP NVM integration.

A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 $\mu$m CMOS Process

We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively.

Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array

A differential paired eFuse OTP (one-time programmable) memory cell which can be configured into a 2D (two-dimensional) eFuse cell array was proposed. The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage. With this 2D array of differential paired eFuse OTP memory cells, we design a 32-bit eFuse OTP memory IP. We use a sense amplifier based D F/F circuit as the BL (bit-line) SA (sense amplifier) and design a sensing margin test circuit with a variable pull-up load. It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.

Design of 32 kbit one-time programmable memory for microcontroller units

A 32 kbit OTP (one-time programmable) memory for MCUs (micro-controller units) used in remote controllers was designed. This OTP memory is used for program and data storage. It is required to apply 5.5 V to BL (bit-line) and 11 V to WL (word-line) for a OTP cell of 0.35 μm ETOX (EEPROM tunnel oxide) type by MagnaChip. We use 5 V transistors on column data paths to reduce the area of column data paths since they require small areas. In addition, we secure device reliability by using HV (high-voltage) transistors in the WL driver. Furthermore, we change from a static logic to a dynamic logic used for the WL driver in the core circuit. Also, we optimize the WD (write data) switch circuit. Thus, we can implement them with a small-area design. In addition, we implement the address predecoder with a small-area logic circuit. The area of the designed 32 kbit OTP with 5 V and HV devices is 674.725 μm×258.75 μm (=0.1745 mm2) and is 56.3% smaller than that using 3.3 V devices.

Improved current filament control during Zener diode zapping

The filament-based failure is investigated in this work by experiment and 3D TCAD simulations in Zener diodes used as one-time-programmable (OTP) memories. Different zapping mechanisms with their inherent electrical and physical signatures are identified and elucidated. Moreover, a new trenched Zener structure is fabricated and tested in order to provide static current filaments as well as to minimize the power to generate them.

Embedded I/O PAD Circuit Design for OTP Memory Power-Switch Functionality

An additional high-voltage pad is generally applied for one-time-programming (OTP) memory product applications. This may increase the complexity of input/output (I/O) pad arrangement and the area penalty. In this paper, a novel approach of I/O circuit embedded with the power-switch function is proposed for multifunction integrations in one I/O pad. The capabilities of high-voltage programming, I/O signal handling, electrostatic discharge protection and latch-up prevention for this novel circuit are well examined from silicon verifications.

One-Time-Programmable Memory in LTPS TFT Technology With Metal-Induced Lateral Crystallization

A simple and reliable one-time-programmable (OTP) memory for low-temperature polysilicon thin-film-transistor technology with metal-induced lateral crystallization (MILC) is developed. The antifuse memory element is based on the breakdown of thin silicon dioxide deposited on smooth surface achieved by MILC. The effects of crystallization process and electrode configurations on the memory characteristics, including statistical variations, are studied. A read current margin of 106 is achieved for the fresh and programmed memory element. Functional OTP memory array with compact layout and high disturb immunity using a split supply configuration is also demonstrated.

A Novel Test Flow for One-Time-Programming Applications of NROM Technology

The NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package test instead of in its wafer test, and hence creates a chance for reusing the bit cells originally identified as a defect to represent the value in the OTP application. Thus, the proposed test flow can reduce the number of bit cells to be repaired and further improve the yield. Also, we propose an efficient and effective estimation scheme to predict the probability of a part being successfully repaired before packaged. This estimation can be used to determine whether a part should be packaged, such that the total profit of the proposed test flow can be optimized. A series of experiments are conducted to demonstrate the effectiveness, efficiency, and feasibility of the proposed test flow.

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

This letter describes the formation of one-time-programmable (OTP) memory using standard contact fuse and polysilicon diode in a standard CMOS technology. Programming of the contact fuse is achieved by applying a high current pulse to destroy the contact. Compared with other existing OTP technologies, the proposed approach has the advantage of zero additional mask, no additional processing step, compact structure, and low programming voltage. The described OTP has been demonstrated in a 0.18-μm CMOS technology from TSMC with a cell size of 2.33 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The contact fuse can be programmed with a voltage of 3 V and a current of 2.4 mA.