One-time Programmable Memory Research Articles

PMIC용 저면적 Dual Port eFuse OTP 메모리 IP 설계

In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to and due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is (), which is confirmed to be a small-area implementation.

Silicon Carbide (SiC) Nanoelectromechanical Antifuse for Ultralow-Power One-Time-Programmable (OTP) FPGA Interconnects

We report a new nanoscale antifuse featuring low-power and high-programming speed, by employing silicon carbide (SiC) nanoelectromechanical systems (NEMS). We show that the SiC NEMS antifuses can enable ultralow-power one-time-programmable (OTP) field-programmable gate arrays (FPGAs) with characteristics promising for security-sensitive and harsh-environment applications. The SiC NEMS antifuses offer minimal leakage, low-programming voltage (down to $\sim 1.5$ V), ideally abrupt transient, high on/off ratios ( $>10^{7}$ ) and high-current carrying ability ( $>10^{6}$ A/cm $^{2}$ ), and very small footprints ( $\sim 1~\mu \text{m}^{2}$ to $\sim 0.1~\mu \text{m}^{2}$ per device). We further describe new designs of antifuses, simulate FPGA benchmarking circuits based on experimentally demonstrated practical NEMS antifuses, and compare their advantageous performance with state-of-the-art conventional antifuse FPGAs. We also demonstrate a SiC NEMS antifuse-based OTP memory cell with a read margin of $>10^{6}$ .

A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process

A new and compact high-k dielectric breakdown one-time programmable (OTP) cell in pure 28-nm high-k metal gate (HKMG) process is proposed. By adopting a self-aligned twin-gate isolation (TGI) made by merged gate spacer, the new OTP cell can operate independently with a very small cell area. Fabricated by a pure 28-nm HKMG CMOS logic process, this OTP cell successfully achieves an ultrasmall cell size of 0.0441 μm 2 on 28-nm HKMG CMOS logic platform. Using high-k dielectric breakdown as its program mechanism, the antifuse TGI OTP memory has more than three orders of ON/OFF read window with a low program voltage of 4 V in 20 μs. Furthermore, a highly density 64-kbit TGI OTP array has been fabricated and successfully demonstrates the new superior isolation and reliability performances.

Low-voltage-operated organic one-time programmable memory using printed organic thin-film transistors and antifuse capacitors.

We demonstrate an organic one-time programmable memory cell formed entirely at plastic-compatible temperatures. All the processes are performed at below 130 degrees C. Our memory cell consists of a printed organic transistor and an organic capacitor. Inkjet-printed organic transistors are fabricated by using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) for low-voltage operation. P(NDI2OD-T2) transistors have a high field-effect mobility of 0.2 cm2/Vs and a low operation gate voltage of less than 10 V. The operation voltage effectively decreases owing to the high permittivity of the P(VDF-TrFE):PMMA blended film. The data in the memory cell are programmed by electrically breaking the organic capacitor. The organic capacitor acts like an antifuse capacitor, because it is initially open, and it becomes permanently short-circuited by applying a high voltage. The organic memory cells are programmed with 4 V, and they are read out with 2 V. The memory data are read out by sensing the current in the memory cell. The printed organic one-time programmable memory is suitable for applications storing small amount of data, such as low-cost radio-frequency identification (RFID) tag.

A Fully Integrated EPC Gen-2 UHF-Band Passive Tag IC Using an Efficient Power Management Technique

We present a system-on-chip passive tag integrated circuit (IC) for secure near-field RF identification applications. The design of the RF transceiver and the digital control of the tag IC are based on the EPCglobal ultrahigh-frequency Gen-2 protocol. A new design technique for the power management of the tag IC is presented, which includes a low-voltage bandgap, a low-dropout regulator with a bias-boosted gain stage, and an adaptive dc limiter. With the proposed design technique, we achieve a high power conversion efficiency of 47% at a low input power of -12 dBm. To support data security, we use one-time programmable (OTP) memory for nonvolatile data storage. The 4-kb (256 × 16 b) OTP memory array is based on a two-transistor (2-T) gate-oxide antifuse that can be programmed with a voltage of less than 6 V. The tag chip was fabricated in a 1-poly 6-metal standard 0.13- μm CMOS process. The power consumption levels of the tag IC are 29.2 and 71.2 μW for the read and programming modes, respectively. The size of the tag chip is 1.1×1 mm2.

A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications

A 4-kbit low-cost one-time programmable (OTP) memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor (1.5T) OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch (HVSW) circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification (RFID) tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm2. The 4-kbit OTP macro only consumes 200 × 260 μm2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.

Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs

The counterfeiting and recycling of integrated circuits (ICs) have become major issues in recent years, potentially impacting the security and reliability of electronic systems bound for military, financial, or other critical applications. With identical functionality and packaging, it would be extremely difficult to distinguish recycled ICs from unused ICs. In this paper, two types of on-chip lightweight sensors are proposed to identify recycled ICs by measuring circuit usage time when used in the field. Recycled ICs detection based on aging in ring oscillators (ROs-based) and antifuse (AF-based) are the two techniques presented in this paper. For RO-based sensors, statistical data analysis is used to separate process and temperature variations' effects on the sensor from aging experienced by the sensor in the ICs. For AF-based sensor, counters and embedded one-time programmable memory are used to record the usage time of ICs by counting the cycle of system clock or switching activities of a certain number of nets in the design. Simulation results using 90-nm technology and silicon results from 90-nm test chips show the effectiveness of RO-based sensors for identification of recycled ICs. In addition, the analysis of usage time stored in AF-based sensors shows that recycled ICs, even used for a very short period, can be accurately identified.

A new 28 nm high-k metal gate CMOS logic one-time programmable memory cell

This work presents a high density high-k metal gate (HKMG) one-time programmable (OTP) cell. Without additional processes and steps, this OTP cell is fully compatible to 28 nm HKMG CMOS process. The OTP cell adopts high-k dielectric breakdown as programming mechanism to obtain more than 105 times of on/off read window. Moreover, it features low power and fast program speed by 4.5 V program voltage in 100 µs. In addition to the ultrasmall cell area of 0.0425 µm2, the superior performance of disturb immunities and data retention further support the new logic OTP cell to be a very promising solution in advanced logic non-volatile memory (NVM) applications.

Inkjet-printed organic thin-film transistor and antifuse capacitor for flexible one-time programmable memory applications

We demonstrate a novel organic antifuse technology on plastic at entirely plastic-compatible temperatures. All processes were performed at temperatures below 135 °C. Our memory cell consists of a printed organic transistor and an organic capacitor. The data in the memory cell are selectively programmed by electrically breaking the capacitor. The organic capacitor acts like as an antifuse capacitor because it is initially open and becomes permanently shorted by applying a high voltage. The memory data are read out by sensing the current in the memory cell. The printed organic one-time programmable memory is suitable for storing small amounts of data such as in low-cost radio-frequency identification tag.

Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access

Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access

One-Time Programmable Memory Based on ${\rm ZrTiO}_{x}$ Antifuse for Crossbar Memory Application Featuring High Speed Operation and Low Power Consumption

TaN/ZrTiOx/Pt metal-insulator-metal structure was employed as the platform to evaluate the eligibility for antifuse one-time programmable (OTP) memory applications, and the impact of O2 plasma on device performance was also discussed. Owing to the oxygen radicals that enhance the dielectric integrity, the voltage for state switching increases with O2 plasma treatment. Memory cells without plasma treatment demonstrate promising characteristics for OTP memory applications in terms of a low dc switching voltage of 2 V, high programming speed of 60 ns, high read endurance up to 106 reading cycles, and desirable retention time and low switching power density of 6.4 mW/cm2. The memory cell technology not only exhibits the prominent performance which is advantageous over other dielectrics reported in the literature, but it also possesses the capability to from stackable 3-D architecture.

Printed Organic One-Time Programmable ROM Array Using Anti-fuse Capacitor

This paper proposes printed organic one-time programmable read-only memory (PROM). The organic PROM cell consists of a capacitor and an organic p-type metal-oxide semiconductor (PMOS) transistor. Initially, all organic PROM cells with unbroken capacitors store “0.” Some organic PROM cells are programmed to “1” by electrically breaking each capacitor with a high voltage. After the capacitor breaking, the current flowing through the PROM cell significantly increases. The memory data is read out by sensing the current in the PROM cell. 16-bit organic PROM cell arrays are fabricated with the printed organic PMOS transistor and capacitor process. The organic PROM cells are programmed with –50 V, and they are read out with –20 V. The area of the 16-bit organic PROM array is 70.6 mm

A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 $\mu$m CMOS Process

We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively.

Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array

A differential paired eFuse OTP (one-time programmable) memory cell which can be configured into a 2D (two-dimensional) eFuse cell array was proposed. The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage. With this 2D array of differential paired eFuse OTP memory cells, we design a 32-bit eFuse OTP memory IP. We use a sense amplifier based D F/F circuit as the BL (bit-line) SA (sense amplifier) and design a sensing margin test circuit with a variable pull-up load. It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.

Design of 32 kbit one-time programmable memory for microcontroller units

A 32 kbit OTP (one-time programmable) memory for MCUs (micro-controller units) used in remote controllers was designed. This OTP memory is used for program and data storage. It is required to apply 5.5 V to BL (bit-line) and 11 V to WL (word-line) for a OTP cell of 0.35 μm ETOX (EEPROM tunnel oxide) type by MagnaChip. We use 5 V transistors on column data paths to reduce the area of column data paths since they require small areas. In addition, we secure device reliability by using HV (high-voltage) transistors in the WL driver. Furthermore, we change from a static logic to a dynamic logic used for the WL driver in the core circuit. Also, we optimize the WD (write data) switch circuit. Thus, we can implement them with a small-area design. In addition, we implement the address predecoder with a small-area logic circuit. The area of the designed 32 kbit OTP with 5 V and HV devices is 674.725 μm×258.75 μm (=0.1745 mm2) and is 56.3% smaller than that using 3.3 V devices.

One-Time-Programmable Memory in LTPS TFT Technology With Metal-Induced Lateral Crystallization

A simple and reliable one-time-programmable (OTP) memory for low-temperature polysilicon thin-film-transistor technology with metal-induced lateral crystallization (MILC) is developed. The antifuse memory element is based on the breakdown of thin silicon dioxide deposited on smooth surface achieved by MILC. The effects of crystallization process and electrode configurations on the memory characteristics, including statistical variations, are studied. A read current margin of 106 is achieved for the fresh and programmed memory element. Functional OTP memory array with compact layout and high disturb immunity using a split supply configuration is also demonstrated.

Design of 1-Kb eFuse OTP Memory IP with Reliability Considered

In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the nonprogrammed eFuse is reduced from 728 ㎂ to 61 ㎂ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 ㏀ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).

Fabrication and Operation Methods of a One-time Programmable (OTP) Nonvolatile Memory (NVM) Based on a Metal-oxide-semiconductor Structure

In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array based on a metal-insulator-semiconductor (MIS) structure is proposed. The Iindividual memory device has a vertical channel of a silicon diode. Historically, OTP memories were widely used for read-only-memories (ROMs), in which the most basic system architecture model was to store central processing unit (CPU) instructions. By grafting the nanoscale fabrication technology and novel structuring onto the concept of the OTP memory, innovative high-density NVM appliances for mobile storage media may be possible. The program operation is performed by breaking down the thin oxide layer between the pn diode structure and the wordline (WL). The programmed state can be identified by an operation that reads the leakage currents through the broken oxide. Since the proposed OTP NVM is based on neither a transistor structure nor a charge storing mechanism, it is highly reliable and functional for realizing the ultra-large scale integration. The operation physics and the fabrication processes are also explained in detail.

Design of 1 kbit antifuse one time programmable memory IP using dual program voltage

A 1 kbit antifuse one time programmable (OTP) memory IP, which is one of the non-volatile memory IPs, was designed and used for power management integrated circuits (ICs). A conventional antifuse OTP cell using a single positive program voltage (VPP) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time, securing the reliability of medium voltage (VM) devices that are thick gate transistors. A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop. For the newly proposed cell, a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse. The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek’s 0.18 μm Bipolar-CMOS-DMOS (BCD) process is 567.9 μm×205.135 μm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.

Investigation of silicon nanowire breakdown properties for the realization of one-time programmable memories

In this work the breakdown properties of silicon nanowires fabricated with a top-down approach are investigated. The breaking voltages and currents of devices based on suspended silicon nanowires with different cross-section widths have been determined. It has been found that devices can be fused using a bias current in the range of 20μA for sufficiently thin nanowires. In this way a device based on a single nanowire can be used for the fabrication of a fully CMOS-compatible one-time programmable (OTP) memory cell, where the wire conductance distinguishes the ON/OFF states. In the normal operation mode (ON state) the dissipated power can be very low. The solution seems to be promising in terms of scalability and low power consumption, which is a key factor in portable systems.